19-1399; Rev 0; 10/98 Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs The MAX1108/MAX1109 low-power, 8-bit, dual-channel, analog-to-digital converters (ADCs) feature an internal track/hold (T/H) voltage reference, clock, and serial interface. The MAX1108 is specified from +2.7V to +3.6V and consumes only 105µA. The MAX1109 is specified from +4.5V to +5.5V and consumes only 130µA. The analog inputs are software configurable, allowing unipolar/bipolar and single-ended/differential operation; battery monitoring capability is also included. The full-scale analog input range is determined by the internal reference of +2.048V (MAX1108) or +4.096V (MAX1109), or by an externally applied reference ranging from 1V to VDD. The MAX1108/MAX1109 also feature a software power-down mode that reduces power consumption to 0.5µA when the device is not in use. The 4-wire serial interface directly connects to SPI™, QSPI™, and MICROWIRE™ devices without external logic. Conversions up to 50ksps are performed using either the internal clock or an external serial-interface clock. The MAX1108 and MAX1109 are available in a 10-pin µMAX package with a footprint that is just 20% of an 8-pin plastic DIP. Applications Portable Data Logging Hand-Held Measurement Devices Medical Instruments System Diagnostics Solar-Powered Remote Systems 4–20mA-Powered Remote Systems Receive-Signal Strength Indicators Features ♦ Single Supply: +2.7V to +3.6V (MAX1108) +4.5V to +5.5V (MAX1109) ♦ Low Power: 105µA at +3V and 50ksps 0.5µA in Power-Down Mode ♦ Software-Configurable Unipolar or Bipolar Inputs ♦ Input Voltage Range: 0 to VDD ♦ Internal Track/Hold ♦ Internal Reference: +2.048V (MAX1108) +4.096V (MAX1109) ♦ Reference Input Range: 1V to VDD ♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface ♦ VDD Monitoring Mode ♦ Small 10-Pin µMAX Package Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX1108CUB 0°C to +70°C 10 µMAX MAX1108EUB -40°C to +85°C 10 µMAX MAX1109CUB 0°C to +70°C 10 µMAX MAX1109EUB -40°C to +85°C 10 µMAX Functional Diagram VDD CS SCLK Pin Configuration OUTPUT SHIFT REGISTER INPUT SHIFT REGISTER DIN MAX1108 MAX1109 TOP VIEW DOUT INTERNAL OSCILLATOR CONTROL LOGIC VDD 1 10 SCLK CH0 2 9 DOUT CH1 CH1 3 8 DIN COM GND 4 7 CS REF 5 6 COM MAX1108 MAX1109 CH0 ANALOG INPUT MUX INTERNAL REFERENCE T/H SAR CHARGE REDISTRIBUTION DAC REF µMAX GND SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX1108/MAX1109 General Description MAX1108/MAX1109 Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V CH0, CH1, COM, REF, DOUT to GND .......-0.3V to (VDD + 0.3V) DIN, SCLK, CS to GND ............................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C) 10-pin µMAX (derate 5.6mW/°C above +70°C) ............444mW Operating Temperature Ranges MAX110_CUB ......................................................0°C to +70°C MAX110_EUB ...................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX1108 (VDD = +2.7V to +3.6V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock mode (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1µF capacitor at REF, external +2.048V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX VDD = 2.7V to 3.6V ±0.15 ±0.5 VDD = 5.5V (Note 2) ±0.2 UNITS DC ACCURACY Resolution 8 Relative Accuracy (Note 1) INL Differential Nonlinearity DNL Offset Error bits No missing codes over temperature ±1 VDD = 2.7V to 3.6V ±0.2 VDD = 5.5V (Note 2) ±0.5 Gain Error (Note 3) ±1 Gain Temperature Coefficient Total Unadjusted Error ±1 ±0.8 TUE TA = +25°C ±0.5 Channel-to-Channel Offset Matching LSB LSB LSB ppm/°C ±1 TA = TMIN to TMAX LSB LSB ±0.1 LSB 50 mV SINAD 49 dB THD -70 dB VDD / 2 Sampling Accuracy DYNAMIC PERFORMANCE (10kHz sine-wave input, 2.048Vp-p, 50ksps, 500kHz external clock) Signal-to-Noise Plus Distortion Total Harmonic Distortion (up to the 5th harmonic) Spurious-Free Dynamic Range Small-Signal Bandwidth SFDR BW-3dB -3dB rolloff Full-Power Bandwidth 68 dB 1.5 MHz 0.8 MHz ANALOG INPUTS Unipolar input, VCOM = 0 Input Voltage Range (Note 4) VCH_ On/off-leakage current, VCOM or VCH = 0 or VDD Multiplexer Leakage Current Input Capacitance 2 CIN 0 VREF Bipolar input, VCOM or VCH1 = VREF / 2, referenced to COM or CH1 ±VREF / 2 ±0.01 18 _______________________________________________________________________________________ ±1 V µA pF Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs (VDD = +2.7V to +3.6V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock mode (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1µF capacitor at REF, external +2.048V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TRACK/HOLD Conversion Time (Note 5) tCONV Track/Hold Acquisition Time tACQ Internal clock 35 External clock, 500kHz, 10 sclks/conv 20 External clock, 2MHz 1 µs µs Aperture Delay 10 ns Aperture Jitter <50 ps Internal Clock Frequency 400 kHz 50 External Clock Frequency Range For data transfer only 500 kHz 2 MHz INTERNAL REFERENCE Output Voltage VREF REF Short-Circuit Current IREFSC 1.968 (Note 6) REF Tempco Load Regulation 0 to 0.5mA (Note 7) Capacitive Bypass at REF 2.048 2.128 V 150 µA ±50 ppm/°C 2.5 mV 1 µF EXTERNAL REFERENCE Input Voltage Range 1.0 +2.048V at REF, full scale, 500kHz external clock Input Current VDD + 0.05 1 V 20 µA 3 5.5 V 105 250 POWER REQUIREMENTS Supply Voltage VDD Supply Current (Notes 2, 8) IDD 2.7 VDD = 2.7V to 3.6V, CL = 10pF Internal reference External reference 70 VDD = 5.5V, CL = 10pF Internal reference 130 External reference 95 Power down, VDD = 2.7V to 3.6V Power-Supply Rejection (Note 9) PSR µA µA 0.5 2.5 ±0.4 ±4 mV VDD ≤ 3.6V 2 V VDD > 3.6V 3 V Full-scale input, VDD = 2.7V to 3.6V DIGITAL INPUTS (DIN, SCLK, and CS) Threshold Voltage High VIH Threshold Voltage Low VIL Input Hysteresis VHYST 0.8 V 0.2 V Input Current High IIH ±1 µA Input Current Low IIL ±1 µA Input Capacitance CIN 15 pF _______________________________________________________________________________________ 3 MAX1108/MAX1109 ELECTRICAL CHARACTERISTICS—MAX1108 (continued) MAX1108/MAX1109 Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs ELECTRICAL CHARACTERISTICS—MAX1108 (continued) (VDD = +2.7V to +3.6V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock mode (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1µF capacitor at REF, external +2.048V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance VOH VOL ISOURCE = 0.5mA VDD - 0.5 V ISINK = 5mA ISINK = 16mA 0.4 V ±10 µA 0.8 IL CS = VDD ±0.01 COUT CS = VDD 15 V pF TIMING CHARACTERISTICS (Figures 8, 9, and 10) Acquisition Time tACQ 1.0 µs DIN to SCLK Setup Time tDS 100 ns DIN to SCLK Hold Time tDH 0 ns SCLK Fall to Output Data Valid tDO Figure 1, CLOAD = 100pF 200 ns CS Fall to Output Enable tDV Figure 1, CLOAD = 100pF 240 ns CS Rise to Output Disable tTR Figure 2, CLOAD = 100pF 240 ns 20 CS to SCLK Rise Setup tCSS 100 ns CS to SCLK Rise Hold tCSH 0 ns SCLK Pulse Width High tCH 200 ns SCLK Pulse Width Low tCL Wake-Up Time Wake-Up Time tWAKE 200 ns External reference 20 µs Internal reference (Note 10) 12 ms ELECTRICAL CHARACTERISTICS—MAX1109 (VDD = +4.5V to +5.5V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1µF capacitor at REF, external +4.096V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Relative Accuracy (Note 1) INL VDD = 4.5V to 5.5V Differential Nonlinearity DNL No missing codes over temperature Offset Error VDD = 4.5V to 5.5V bits ±0.15 ±0.2 Gain Error (Note 3) Gain Temperature Coefficient Total Unadjusted Error Channel-to-Channel Offset Matching VDD / 2 Sampling Accuracy 4 ±0.5 LSB ±1 LSB ±1 LSB ±1 LSB ±0.8 TUE TA = +25°C TA = TMIN to TMAX ppm/°C ±1 ±0.5 LSB ±0.1 LSB 50 mV _______________________________________________________________________________________ Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs (VDD = +4.5V to +5.5V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1µF capacitor at REF, external +4.096V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE (10kHz sine-wave input, 4.096Vp-p, 50ksps, 500kHz external clock) Signal-to-Noise Plus Distortion SINAD 49 dB Total Harmonic Distortion (up to the 5th harmonic) THD -70 dB Spurious Free Dynamic Range SFDR 68 dB 1.5 MHz 0.8 MHz Small-Signal Bandwidth BW-3dB -3dB rolloff Full-Power Bandwidth ANALOG INPUTS Unipolar input, VCOM = 0 Input Voltage Range (Note 4) VCH_ VREF ±VREF / 2 On/off-leakage current, VCH = 0 or VDD Multiplexer Leakage Current Input Capacitance 0 Bipolar input, VCOM or VCH1 = VREF / 2, referenced to COM or CH1 ±0.01 CIN ±1 18 V µA pF TRACK/HOLD Conversion Time (Note 5) tCONV Track/Hold Acquisition Time tACQ Internal clock 35 External clock, 500kHz, 10 sclks/conv 20 External clock, 2MHz 1 µs µs Aperture Delay 10 ns Aperture Jitter <50 ps Internal Clock Frequency 400 kHz 50 External Clock Frequency Range For data transfer only 500 kHz 2 MHz INTERNAL REFERENCE Output Voltage VREF REF Short-Circuit Current REF Tempco 3.936 IREFSC 0 to 0.5mA (Note 7) Load Regulation Capacitive Bypass at REF 4.096 4.256 V 5 mA ±50 ppm/°C 2.5 mV 1 µF EXTERNAL REFERENCE Input Voltage Range Input Current 1.0 +4.096V at REF, full scale, 500kHz external clock VDD + 0.05 1 20 V µA _______________________________________________________________________________________ 5 MAX1108/MAX1109 ELECTRICAL CHARACTERISTICS—MAX1109 (continued) MAX1108/MAX1109 Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs ELECTRICAL CHARACTERISTICS—MAX1109 (continued) (VDD = +4.5V to +5.5V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1µF capacitor at REF, external +4.096V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.5 5 5.5 V Internal reference 130 250 External reference 95 POWER REQUIREMENTS Supply Voltage Supply Current (Notes 2, 8) VDD IDD VDD = 4.5V to 5.5V, CL = 10pF, full-scale input Power down, VDD = 4.5V to 5.5V Power-Supply Rejection (Note 9) PSR External reference = +4.096V, full-scale input, VDD = 4.5V to 5.5V µA µA 0.5 2.5 ±0.4 ±4 mV 3 V DIGITAL INPUTS (DIN, SCLK, and CS) Threshold Voltage High Threshold Voltage Low Input Hysteresis Input Current High VIH VIL 0.8 VHYST V 0.2 IIH Input Current Low IIL Input Capacitance CIN V ±1 µA ±1 µA 15 pF DIGITAL OUTPUT (DOUT) Output High Voltage VOH Output Low Voltage VOL Three-State Leakage Current Three-State Output Capacitance ISOURCE = 0.5mA VDD - 0.5 V ISINK = 5mA 0.4 ISINK = 16mA 0.8 IL CS = VDD ±0.01 COUT CS = VDD 15 ±10 V µA pF TIMING CHARACTERISTICS (Figures 8, 9, and 10) Acquisition Time DIN to SCLK Setup Time tACQ 1.0 µs tDS 100 ns DIN to SCLK Hold Time tDH SCLK Fall to Output Data Valid tDO Figure 1, CLOAD = 100pF CS Fall to Output Enable tDV CS Rise to Output Disable tTR 6 0 20 ns 200 ns Figure 1, CLOAD = 100pF 240 ns Figure 2, CLOAD = 100pF 240 ns _______________________________________________________________________________________ Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs (VDD = +4.5V to +5.5V; unipolar input mode; COM = GND, fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1µF capacitor at REF, external +4.096V reference at REF; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CS to SCLK Rise Setup tCSS CS to SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Low Wake-Up Time CONDITIONS MIN TYP MAX UNITS 100 ns tCSH 0 ns tCH 200 ns tCL 200 ns tWAKE External reference 20 µs Internal reference (Note 10) 12 ms Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 2: See Typical Operating Characteristics. Note 3: VREF = +2.048V (MAX1108), VREF = +4.096V (MAX1109), offset nulled. Note 4: Common-mode range (CH0, CH1, COM) GND to VDD. Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle (Figures 6 and 8). Note 6: REF supplies typically 2.5mA under normal operating conditions. Note 7: External load should not change during the conversion for specified accuracy. Note 8: Power consumption with CMOS levels. Note 9: Measured as VFS(2.7V) - VFS(3.6V) for MAX1108, and measured as VFS(4.5V) - VFS(5.5V) for MAX1109. Note 10: 1µF at REF, internal reference settling to 0.5LSB. Typical Operating Characteristics (VDD = +3.0V (MAX1108), VDD = +5.0V (MAX1109); external conversion mode; fSCLK = 500kHz; 50ksps; external reference; 1µF at REF; TA = +25°C; unless otherwise noted.) CLOAD = 10pF 100 80 60 DOUT = 10101010 MAX1108 (2.7V TO 5.5V) MAX1109 (4.5V TO 5.5V) INTERNAL REFERENCE 40 20 VDD = 5V 160 140 120 VDD = 3V 100 80 60 DOUT = 10101010 CLOAD = 10pF INTERNAL REFERENCE 40 20 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 6 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 0 0.50 MAX1108/09-03 180 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 140 MAX1108/09-02 CLOAD = 47pF 160 120 200 MAX1108/09-01 200 180 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE SHUTDOWN CURRENT (µA) SUPPLY CURRENT vs. SUPPLY VOLTAGE -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 7 MAX1108/MAX1109 ELECTRICAL CHARACTERISTICS—MAX1109 (continued) Typical Operating Characteristics (continued) (VDD = +3.0V (MAX1108), VDD = +5.0V (MAX1109); external conversion mode; fSCLK = 500kHz; 50ksps; external reference; 1µF at REF; TA = +25°C; unless otherwise noted.) OFFSET ERROR vs. TEMPERATURE 0.4 0.2 0.1 0 -0.1 -0.2 0.2 0.1 0 -0.1 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 3.5 4.0 4.5 5.0 5.5 0 -0.05 -0.15 -0.20 -40 -20 0 SUPPLY VOLTAGE (V) 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE (°C) GAIN ERROR vs. SUPPLY VOLTAGE 0.8 0.6 GAIN ERROR (LSB) 0.2 0.1 0 -0.1 1.0 0.4 0.8 0.6 GAIN ERROR (LSB) 0.3 GAIN ERROR vs. REFERENCE VOLTAGE GAIN ERROR vs. TEMPERATURE MAX1108/09-08 0.4 REFERENCE VOLTAGE (V) 1.0 MAX1108/09-07 0.5 0.2 0 -0.2 0.4 0.2 0 -0.2 -0.2 -0.4 -0.4 -0.3 -0.6 -0.6 -0.4 -0.8 -0.8 -0.5 -1.0 3.0 3.5 4.0 4.5 5.0 5.5 -1.0 -40 -20 0 20 40 60 80 SUPPLY VOLTAGE (V) TEMPERATURE (°C) REFERENCE VOLTAGE (V) INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs. CODE DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE 0.2 0.4 0.3 DNL (LSB) 0.1 0 -0.1 -0.2 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 0.4 0.3 0.2 0.2 0.1 0.1 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.3 0.5 MAX1108/09-12 0.5 MAX1108/09-10 0.3 2.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 100 DNL (LSB) 2.5 MAX1108/09-11 GAIN ERROR (LSB) 0.05 MAX1108/09-09 3.0 0.10 -0.10 -0.5 2.5 8 0.15 OFFSET ERROR (LSB) 0.3 OFFSET ERROR (LSB) 0.3 OFFSET ERROR vs. REFERENCE VOLTAGE 0.20 MAX1108/09-05 MAX1108/09-04 0.4 OFFSET ERROR (LSB) 0.5 MAX1108/09-06 OFFSET ERROR vs. SUPPLY VOLTAGE 0.5 INL (LSB) MAX1108/MAX1109 Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs -0.5 0 50 100 150 200 DIGITAL CODE 250 300 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5.0 5.5 Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs FFT PLOT 0 -20 AMPLITUDE (dB) 0.2 0.1 0 -0.1 fCH_ = 9997Hz, 2Vp-p fSAMPLE = 53.25kHz -40 -60 -0.2 -0.3 INTERNAL CONVERSION MODE 20.5 CONVERSION TIME(µs) 0.3 CONVERSION TIME vs. SUPPLY VOLTAGE 21.0 MAX1108/09-14 0.4 INL (LSB) 20 MAX1108/09-13 0.5 MAX1108/09-15 INTEGRAL NONLINEARITY vs. CODE -80 20.0 19.5 19.0 18.5 -0.4 -100 -0.5 0 50 100 150 200 250 5 10 15 20 30 25 0 1 2 3 4 5 DIGITAL CODE FREQUENCY (kHz) SUPPLY VOLTAGE (V) CONVERSION TIME vs. TEMPERATURE NORMALIZED REFERENCE VOLTAGE vs. TEMPERATURE CHANNEL-TO-CHANNEL CROSSTALK vs. FREQUENCY VDD = 3V 20 VDD = 5V 18 17 1.0000 0.9995 0.9990 6 MAX1108/09-18 VCH_OFF = VREFp-p -10 -20 CROSSTALK (dB) 22 19 1.0005 REFERENCE VOLTAGE (V) 23 0 MAX1108/09-17 INTERNAL CONVERSION MODE 21 1.0010 MAX1108/09-16 25 24 CONVERSION TIME (µs) 18.0 0 300 -30 -40 -50 -60 -70 -80 0.9985 16 -90 15 0.9980 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) -100 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) 0 5 10 15 20 25 FREQUENCY (kHz) Pin Description PIN NAME 1 VDD Positive Supply Voltage FUNCTION 2, 3 CH0, CH1 Sampling Analog Inputs 4 GND Ground 5 REF Reference voltage for analog-to-digital conversion (internal or external reference). Reference input for external reference. Bypass internal reference with 1µF capacitor to GND. 6 COM Common reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to ±0.5LSB during conversion. 7 CS Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. 8 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK. 9 DOUT Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is high. 10 SCLK Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. _______________________________________________________________________________________ 9 MAX1108/MAX1109 Typical Operating Characteristics (continued) (VDD = +3.0V (MAX1108), VDD = +5.0V (MAX1109); external conversion mode; fSCLK = 500kHz; 50ksps; external reference; 1µF at REF; TA = +25°C; unless otherwise noted.) MAX1108/MAX1109 Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs VDD VDD DOUT DOUT 3k 3k DOUT DGND CLOAD CLOAD DGND DGND b) High-Z to VOL and VOH to VOL Figure 1. Load Circuits for Enable Time DOUT 3k CLOAD CLOAD a) High-Z to VOH and VOL to VOH 3k DGND a) VOH to High-Z b) VOL to High-Z Figure 2. Load Circuits for Disable Time _______________Detailed Description The MAX1108/MAX1109 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to an 8-bit digital output. A flexible serial interface provides easy interface to microprocessors (µPs). No external hold capacitors are required. All of the MAX1108/MAX1109 operating modes are software-configurable: internal or external reference, internal or external conversion clock, single-ended unipolar or pseudo-differential unipolar/bipolar conversion, and power down (Table 1). Analog Inputs Track/Hold The input architecture of the ADCs is illustrated in the equivalent-input circuit of Figure 4 and is composed of the T/H, the input multiplexer, the input comparator, the switched capacitor DAC, the reference, and the autozero rail. The analog-inputs configuration is determined by the control-byte through the serial interface as shown in Table 2 (see Modes of Operation section and Table 1). The eight modes of operation include single-ended, pseudo-differential, unipolar/bipolar, and a VDD monitoring mode. During acquisition and conversion, only one of the switches in Figure 4 is closed at any time. The T/H enters its tracking mode on the falling clock edge after bit 4 (SEL0) of the control byte has been shifted in. It enters its hold mode on the falling edge after the bit 2 (I/EREF) of the control byte has been shifted in. For example, If CH0 and COM are chosen (SEL2 = SEL1 = SEL0 = 1) for conversion, CH0 is defined as the sampled input (SI), and COM is defined as the reference input (RI). During acquisition mode, the CH0 switch and the T/H switch are closed, charging the 10 VDD VDD VDD CH0 0.1µF ANALOG INPUTS 1µF GND CH1 COM CPU MAX1108 MAX1109 REF 1µF I/O CS SCLK SCK (SK) MOSI (SO) DIN DOUT MISO (SI) VSS Figure 3. Typical Operating Circuit GND CAPACITIVE DAC REF CH1 CHOLD COMPARATOR CH0 18pF COM VDD / 2 RIN 6.5k HOLD TRACK GND AUTOZERO RAIL Figure 4. Equivalent Input Circuit ______________________________________________________________________________________ Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs where R IN = 6.5kΩ, RS = the source impedance of the input signal, and t ACQ is never less than 1µs. Note that source impedances below 2.7kΩ do not significantly affect the AC performance of the ADC at the maximum clock speed. If the input-source impedance is higher than 3kΩ, the clock speed must be reduced accordingly. Pseudo-Differential Input The MAX1108/MAX1109 input configuration is pseudodifferential to the extent that only the signal at the sampled input (SI) is stored in the holding capacitor (CHOLD). The reference input (RI) must remain stable within ±0.5LSB (±0.1LSB for best results) in relation to GND during a conversion. Sampled input and reference input configuration is determined by bit6–bit4 (SEL2–SEL0) of the control byte (Table 2). If a varying signal is applied at the selected reference input, its amplitude and frequency need to be limited. The following equations determine the relationship between the maximum signal amplitude and its frequency to maintain ±0.5LSB accuracy: Assuming a sinusoidal signal at the reference input vRI = VRIsin(2πft) the maximum voltage variation is determined by: max dvRI dt = 2πf ⋅ vRI ≤ 1 LSB t CONV = VREF 28 t CONV a 60Hz signal at RI with an amplitude of 1.2V will generate a ±0.5LSB of error. This is with a 35µs conversion time (maximum tCONV in internal conversion mode) and a reference voltage of +4.096V. When a DC reference voltage is used at RI, connect a 0.1µF capacitor to GND to minimize noise at the input. The input configuration selection also determines unipolar or bipolar conversion mode. The commonmode input range of CH0, CH1, and COM is 0 to +VDD. In unipolar mode, full scale is achieved when (SI - RI) = VREF; in bipolar mode, full scale is achieved when (SI - RI) = VREF / 2. In unipolar mode, SI must be higher than RI; in bipolar mode, SI can span above and below RI provided that it is within the common-mode range. Conversion Process The comparator negative input is connected to the autozero rail. Since the device requires only a single supply, the ZERO node at the input of the comparator equals VDD/2. The capacitive DAC restores node ZERO to have 0V difference at the comparator inputs within the limits of 8-bit resolution. This action is equivalent to transferring a charge of 18pF(VIN+ - VIN-) from CHOLD to the binary-weighted capacitive DAC which, in turn, forms a digital representation of the analog-input signal. Input Voltage Range Internal protection diodes that clamp the analog input to VDD and AGND allow the channel input pins (CH0, CH1, and COM) to swing from (AGND - 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions, the inputs must not exceed (VDD + 50mV) or be less than (GND - 50mV). If the analog input voltage on an “off” channel exceeds 50mV beyond the supplies, the current should be limited to 2mA to maintain conversion accuracy on the “on” channel. The MAX1108/MAX1109 input range is from 0 to VDD; unipolar or bipolar conversion is available. In unipolar mode, the output code is invalid (code zero) when a negative input voltage (or a negative differential input voltage) is applied. The reference input-voltage range at REF is from 1V to (VDD + 50mV.) Input Bandwidth The ADC’s input tracking circuitry has a 1.5MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Serial Interface The MAX1108/MAX1109 have a 4-wire serial interface. The CS, DIN, and SCLK inputs are used to control the device, while the three-state DOUT pin is used to access the result of conversion. ______________________________________________________________________________________ 11 MAX1108/MAX1109 holding capacitor CHOLD through RIN. At the end of acquisition the T/H switch opens and CHOLD is connected to COM, retaining charge on CHOLD as a sample of the signal at CH0, and the difference between CH0 and COM is the converted signal. Once conversion is complete, the T/H returns immediately to its tracking mode. This procedure holds for the different combinations summarized in Table 2. The time available for the T/H to acquire an input signal (tACQ) is determined by the clock frequency, and is 1µs at the maximum clock frequency of 2MHz. The acquisition time is also the minimum time needed for the signal to be acquired. It is calculated by: tACQ = 6(RS + RIN)18pF MAX1108/MAX1109 Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs The serial interface provides easy connection to microcontrollers with SPI, QSPI and MICROWIRE serial interfaces at clock rates up to 2MHz. For SPI and QSPI, set CPOL = CPHA = 0 in the SPI control registers of the microcontroller. Figure 5 shows the MAX1108/MAX1109 common serial-interface connections. DOUT is active when CS is low and high impedance when CS is high. DOUT does not accept external voltages greater than VDD. In external-clock mode, data is clocked out at the maximum clock rate of 500kHz while conversion is in progress. In internal-clock mode, data can be clocked out at up to 2MHz clock rate. Digital Inputs The logic levels of the MAX1108/MAX1109 digital input are set to accept voltage levels from both +3V and +5V systems, regardless of the supply voltages. Input data (control byte) is clocked in at the DIN pin on the rising edge of serial clock (SCLK). CS is the standard chipselect signal which enables communication with the device. SCLK is used to clock data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. The MAX1108/MAX1109 feature single-ended or pseudo-differential operation in unipolar or bipolar configuration. The device is programmed through the input control-byte at the DIN pin of the serial interface (Table 1). Table 2 shows the analog-input configuration and Table 3 shows the input-voltage ranges in unipolar and bipolar configuration. Digital Output Output data is read on the rising edge of SCLK at DOUT, MSB first (D7). In unipolar input mode, the output is straight binary. For bipolar input mode, the output is twos-complement (see Transfer Function section). I/O CS SCK SCLK MISO MOSI DOUT DIN +3V MAX1108 MAX1109 SS How to Start a Conversion A conversion is started by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1108/MAX1109’s internal shift register. After CS falls, the first arriving logic “1” bit at DIN defines the MSB of the control byte. Until this first start bit arrives, any number of logic “0” bits can be clocked into DIN with no effect. Table 1 shows the control-byte format. Using the Typical Operating Circuit (Figure 3), the simplest software interface requires two 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and one 8-bit transfer to clock out the 8-bit conversion result). Figure 6 shows a single-conversion timing diagram using external clock mode. Clock Modes a) SPI CS CS SCK SCLK MISO MOSI DOUT DIN +3V MAX1108 MAX1109 SS b) QSPI I/O CS SK SCLK SI SO DOUT DIN MAX1108 MAX1109 c) MICROWIRE Figure 5. Common Serial-Interface Connections 12 Modes of Operation The MAX1108/MAX1109 can use either an external serial clock or the internal clock to perform the successiveapproximation conversion. In both clock modes, the external clock shifts data in and out of the devices. Bit 3 of control-byte (I/ECLK) programs the clock mode. Figure 8 shows the timing characteristics common to both modes. External Clock In external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital conversion steps. In this mode the clock frequency must be between 50kHz and 500kHz. Single-conversion timing using an external clock begins with a falling edge on CS. When this occurs, DOUT leaves the high impedance state and goes low. The first “1” clocked into DIN by SCLK after CS is set low is considered as the start bit. The next seven clocks latch in the rest of the control byte. On the falling edge of the fourth clock, track mode is enabled, and on the falling edge of the sixth clock, acquisition is complete and conversion is ______________________________________________________________________________________ Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) START SEL2 SEL1 SEL0 I/ECLK I/EREF REFSHDN SHDN BIT NAME 7 (MSB) START 6 5 4 SEL2 SEL1 SEL0 3 I/ECLK 1 = external clock, 0 = internal clock. The SAR can be driven by the internal oscillator, or with the SCLK signal. 2 I/EREF 1 = internal reference, 0 = external reference. Internal reference selects +2.048V (MAX1108) or +4.096V (MAX1109), or an external reference can be applied to the REF pin. 1 REFSHDN 0 (LSB) SHDN DESCRIPTION The first logic “1” bit after CS goes low defines the beginning of the control byte. Selects the mode of operation (Table 2). 1 = operational (if I / EREF = 1), 0 = reference shutdown. When using an external reference, power consumption can be minimized by powering down the internal reference separately (I / EREF = 0). REFSHDN must be set to 0 when SHDN = 0. 1 = operational, 0 = power down. For a full power down set REFSHDN = SHDN = 0. (See PowerDown Mode section.) Table 2. Conversion Configuration SEL2 SEL1 SEL0 SAMPLED INPUT (SI) REFERENCE INPUT (RI) CONVERSION MODE 1 1 1 CH0 COM Unipolar 1 1 0 CH1 COM Unipolar 1 0 1 CH0 GND Unipolar 1 0 0 CH1 GND Unipolar 0 1 1 CH0 COM Bipolar 0 1 0 CH1 COM Bipolar 0 0 1 CH0 CH1 Bipolar 0 0 0 VDD / 2 GND Unipolar Table 3. Full- and Zero-Scale Voltages UNIPOLAR MODE BIPOLAR MODE Zero Scale Full Scale Negative Full Scale Zero Scale Positive Full Scale RI* RI + VREF RI - VREF / 2 RI RI + VREF / 2 *RI = Reference Input (Table 2) ______________________________________________________________________________________ 13 MAX1108/MAX1109 Table 1. Control Byte Format MAX1108/MAX1109 Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs Internal Clock Internal clock mode frees the µP from the burden of running the SAR conversion clock. This allows the conversion results to be read back at the processor’s convenience, at any clock rate up to 2MHz. An internal register stores data when the conversion is in progress. On the falling edge of the fourth SCLK, track mode is enabled, and on the falling edge of the eighth SCLK, acquisition is complete and internal conversion is initiated. The internal 400kHz clock completes the conversion in 20µs typically (35µs max), at which time the MSB of the conversion is present at the DOUT pin. The falling edge of SCLK clocks the remaining data out of this register at any time after the conversion is complete (Figure 8). initiated. The MSB successive-approximation bit decision is made on the rising edge of the seventh SCLK. On the falling edge of the eighth SCLK, the MSB is clocked out on the DOUT pin; on each of the next seven SCLK falling edges, the remaining bits of conversion are clocked out. Zeros are clocked out on DOUT after the LSB has been clocked out, until CS is disabled. Then DOUT becomes high impedance and the part is ready for another conversion (Figure 6). The conversion must complete in 1ms, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if the serial-clock frequency is less than 50kHz, or if serial-clock interruptions could cause the conversion interval to exceed 1ms. CS 1 SCLK 4 8 MSB 12 16 20 LSB SEL2 SEL1 SEL0 I/ECLK I/EREF DIN REF SHDN SHDN START MSB D7 DOUT LSB D6 tACQ A/D STATE D5 D4 D3 D2 D1 D0 tCONV IDLE IDLE Figure 6. Single Conversion Timing, External Clock Mode CS ••• tCSH tCSS tCL SCLK tCH tCSH ••• tDS tDH ••• DIN tDV DOUT tDO ••• Figure 7. Detailed Serial-Interface Timing 14 ______________________________________________________________________________________ tTR Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs Quick Look To quickly evaluate the MAX1108/MAX1109’s analog performance, use the circuit of Figure 9. The device requires a control byte to be written to DIN before each conversion. Tying CS to GND and DIN to VDD feeds in control bytes of FFH. In turn, this triggers single-ended, unipolar conversions on CH0 in relation to COM in external clock mode without powering down between conversions. Apply an external 50kHz to 500kHz clock CS 1 SCLK 4 8 SEL2 SEL0 SEL1 I/EREF I/ECLK DIN 10 14 18 REF SHDN SHDN START DOUT D7 D5 D4 D3 D2 D1 D0 tCONV tACQ IDLE A/D STATE D6 IDLE 35µs MAX Figure 8. Single Conversion Timing, Internal Clock Mode VDD OSCILLOSCOPE VSUPPLY 0.1µF 1µF DOUT* MAX1108 MAX1109 ANALOG INPUT 0.01µF CH0 MSB GND LSB SCLK CS SCLK COM DIN VDD 500kHz OSCILLATOR 5µs/div CH1 CH2 DOUT REF C1 1µF *CONVERSION RESULT = 10101010 Figure 9. Quick-Look Schematic ______________________________________________________________________________________ 15 MAX1108/MAX1109 CS does not need to be held low once a conversion is started. Pulling CS high prevents data from being clocked into the MAX1108/MAX1109 and three-states DOUT, but it does not adversely affect an internal clock-mode conversion already in progress. In this mode, data can be shifted in and out of the MAX1108/MAX1109 at clock rates up to 2MHz, provided that the minimum acquisition time (t ACQ) is kept above 1µs. MAX1108/MAX1109 Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs In external clock mode, the first high bit clocked into DIN after the bit 5 (D5) of a conversion in progress is clocked onto the DOUT pin. OR In internal clock mode, the first high bit clocked into DIN after the bit 4 (D4) is clocked onto the DOUT pin. The MAX1108/MAX1109 can run at a maximum speed of 10 clocks per conversion. Figure 10 shows the serialinterface timing necessary to perform a conversion every 10 SCLK cycles in external clock mode. Many microcontrollers require that conversions occur in multiples of 8 SCLK clocks; 16 clocks per conversion is typically the fastest that a microcontroller can drive the MAX1108/MAX1109. Figure 11 shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles in external clock mode. to the SCLK pin; varying the analog input alters the result of conversion that is clocked out at the DOUT pin. A total of 10 clock cycles is required per conversion. Data Framing The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. Acquisition starts on the falling edge of the fourth SCLK and lasts for two SCLKs in external clock mode or four SCLKs in internal clock mode. Conversion starts immediately after acquisition is completed. The start bit is defined as: The first high bit clocked into DIN with CS low any time the converter is idle; e.g., after VDD is applied. OR CS 1 8 10 1 1 10 10 1 SCLK S DIN S CONTROL BYTE 0 S CONTROL BYTE 1 CONVERSION RESULT 1 CONVERSION RESULT 0 DOUT D7 IDLE A/D STATE D5 tCONV tACQ S CONTROL BYTE 2 D0 D7 tACQ D5 tCONV D0 tACQ D7 tCONV Figure 10. Continuous Conversion, External Clock Mode, 10 Clocks/Conversion Timing CS 1 8 17 25 SCLK DIN S CONTROL BYTE 0 S S CONTROL BYTE 1 CONVERSION RESULT 1 CONVERSION RESULT 0 DOUT D7 D0 D7 Figure 11. Continuous Conversion, External Clock Mode, 16 Clocks/Conversion Timing 16 ______________________________________________________________________________________ D0 Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs Table 4. Power-Down Modes of the MAX1108/MAX1109 BIT 2–BIT 0 OF CONTROL BYTE I/EREF REFSHDN 1 1 OPERATING MODE SHDN 1 Device Active/Internal Reference Active 1 0 1 Device Active; Internal reference powered down after conversion, powered up at next start bit. 0 X 1 Device Active/External Reference Mode 1 0 0 Device and internal reference powered down after conversion, powered up at next start bit. 0 X 0 Device powered down after each conversion, powered up at next start bit. External Reference Mode. 1 1 0 Reserved. Do not use. __________Applications Information Battery Monitoring Mode This mode of operation samples and converts the midsupply voltage, VDD / 2, which is internally generated. Set SEL2 = SEL1 = SEL0 = 0 in the control byte to select this configuration. This allows the user to monitor the condition of a battery providing VDD. The reference voltage must be larger than VDD / 2 for this mode of operation to work properly. From the result of conversion (CODE), V DD is determined as follows: VDD = CODE · VREF / 128. Power-On Configuration When power is first applied, the MAX1108/MAX1109’s reference is powered down and SHDN is not enabled. The device needs to be configured by setting CS low and writing the control byte. Conversion can be started within 20µs if an external reference is used. When using the internal reference, allow 12ms for the reference to settle. This is done by first performing a configuration conversion to power up the reference and then performing a second conversion once the reference is settled. No conversions should be considered correct until the reference voltage (internal or external) has stabilized. Power-Down Modes To save power, place the converter into low-current power-down mode between conversions. Minimum power consumption is achieved by programming REFSHDN = 0 and SHDN = 0 in the input control byte (Table 4). When software power-down is asserted, it becomes effective only after the conversion. If the control byte contains REFSHDN = 0, then the reference will turn off at the end of conversion. If SHDN = 0, then the chip will power-down at the end of conversion (in this mode I/EREF or REFSHDN should also be set to zero). Table 4 lists the power-down modes of the MAX1108/ MAX1109. X = Don’t care The first logical 1 clocked into DIN after CS falls powers up the MAX1108/MAX1109 (20µs required for the device to power up). The reference is powered up only if internal reference was selected during the previous conversion. When the reference is powered up after being disabled, consider the settling time before using the result of conversion. Typically, 12ms are required for the reference to settle from a discharge state; less time may be considered if the external capacitor is not discharged completely when exiting shutdown. In all power-down modes, the interface remains active and conversion results may be read. Use the double clocking technique described in the Data Framing section to allow more time for the reference to settle before starting a conversion after short power-down. Voltage Reference The MAX1108/MAX1109 operate from a single supply and feature a software-controlled internal reference of +2.048V (MAX1108) and +4.096V (MAX1109). The device can operate with either the internal reference or an external reference applied at the REF pin. See the Power-Down Modes and Modes of Operation sections for detailed instructions on reference configuration. The reference voltage determines the full-scale range: in unipolar mode, the input range is from 0 to VREF; in bipolar mode, the input range spans RI ±VREF / 2 with RI = VREF / 2. ______________________________________________________________________________________ 17 MAX1108/MAX1109 In external clock mode, if CS is toggled before the current conversion is complete, the current conversion is terminated, and the next high bit clocked into DIN is recognized as a new start bit. This can be useful in extending acquisition time by selecting conversion on the same channel with the second control byte (doubleclocking mode), effectively extending acquisition to 6 SCLKs. This technique is ideal if the analog input source has high impedance, or if it requires more than 1µs to settle; it can also be used to allow the device and the reference to settle when using power downmodes (see Power-Down Modes section). MAX1108/MAX1109 Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs External Reference To use an external reference, set bit 2 (I/EREF) and bit 1 (REFSHDN) of control byte to 0 and connect the external reference (VREF between 1V and VDD) directly at the REF pin. The DC input impedance at REF is extremely high, consisting of leakage current only (typically 10nA). During a conversion, the reference must be able to deliver up to 20µA average load current and have an output impedance of 1kΩ or less at the conversion clock frequency. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 0.1µF capacitor. MAX1109 has an internal reference of +4.096V. To use the device with supply voltages below 4.5V, external reference mode is required. With an external reference voltage of less than +2.048V (MAX1108) or +4.096V (MAX1109) at REF, the increase in the ratio of the RMS noise to the LSB value (FS / 256) results in performance degradation and decreased dynamic range. Internal Reference To use the internal reference, set bit 2 (I/EREF) and bit 1 (REFSHDN) of the control byte to 1 and bypass REF with a 1µF capacitor to ground. The internal reference can be powered down after a conversion by setting bit 1 (REFSHDN) of the control byte to 0. When using the internal reference, use MAX1108 and MAX1109 with supply voltage below 4.5V and above 4.5V, respectively. Transfer Function Table 4 shows the full-scale voltage ranges for unipolar and bipolar modes. Figure 12a depicts the nominal, unipolar I/O transfer function, and Figure 12b shows the bipolar I/O transfer function. The zero scale is determined by the input selection setting and is either COM, GND, or CH1. Code transitions occur at integer LSB values. Output coding is straight binary for unipolar operation and two’s complement for bipolar operation. With a +2.048V reference, 1LSB = 8mV (VREF / 256). OUTPUT CODE FULL-SCALE TRANSITION 11111111 11111110 11111101 FS = VREF + COM 1LSB = VREF 256 00000011 00000010 00000001 00000000 0 1 2 (COM) 3 FS INPUT VOLTAGE (LSB) FS - 1LSB Figure 12a. Unipolar Transfer Function OUTPUT CODE 01111111 01111110 00000010 00000001 00000000 VREF + COM 2 V COM = REF 2 -VREF -FS = + COM 2 VREF 1LSB = 256 +FS = 11111111 11111110 11111101 10000001 10000000 -FS COM INPUT VOLTAGE (LSB) +FS - 1 LSB 2 Layout, Grounding, and Bypassing For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or run digital lines underneath the ADC package. Figure 13 shows the recommended system-ground connections. A single-point analog ground (star-ground point) should be established at the A/D ground. Connect all analog grounds to the star ground. No digital-system ground should be connected to this point. 18 Figure 12b. Bipolar Transfer Function The ground return to the power supply for the star ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply may affect the comparator in the ADC. Bypass the supply to the star ground with 0.1µF and 1µF capacitors close to the V DD pin of the MAX1108/MAX1109. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, a 10Ω resistor can be connected to form a lowpass filter. ______________________________________________________________________________________ Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs TRANSISTOR COUNT: 2373 SYSTEM POWER SUPPLIES GND +3V/+5V 1µF 10Ω 0.1µF GND COM VDD MAX1108 MAX1109 DGND VDD DIGITAL CIRCUITRY Figure 13. Power-Supply Connections ______________________________________________________________________________________ 19 MAX1108/MAX1109 Chip Information Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs 10LUMAXB.EPS MAX1108/MAX1109 Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.