MAXIM DS2408S

DS2408
1-Wire 8-Channel Addressable Switch
www.maxim-ic.com
FEATURES
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Eight Channels of Programmable I/O with
Open-Drain Outputs
On-Resistance of PIO Pulldown Transistor
100W (max); Off-Resistance 10MW (typ)
Individual Activity Latches Capture
Asynchronous State Changes at PIO Inputs
for Interrogation by the Bus Master
Data-Strobe Output to Synchronize PIO
Logic States to External Read/Write Circuitry
Built-in Multidrop Controller Ensures
Compatibility with Other Dallas
Semiconductor 1-Wire® Net Products
Supports 1-Wire Conditional Search
Command with Response Controlled by
Programmable PIO Conditions
Unique Factory-Lasered 64-Bit Registration
Number Ensures Error-Free Device Selection
and Absolute Part Identity
Communicates to Host with a Single Digital
Signal at 15.3kbps or 100kbps using 1-Wire
Protocol
Operating Range: 2.8V to 5.25V, -40°C to
+85°C
PIN CONFIGURATION
N.C.
1
16
N.C.
P0
2
15
N.C.
VCC
3
14
P1
I/O
4
13
P2
GND
5
12
P3
N.C.
6
11
P4
P7
7
10
RSTZ
P6
8
9
P5
150-mil SO
ORDERING INFORMATION
PART
DS2408S
DS2408S
/T&R
TEMP
RANGE
-40°C to +85°C
-40°C to +85°C
PACKAGE
16-Pin SO, 150 mil
Tape-and-Reel of
DS2408S
DESCRIPTION
The DS2408 is an 8-channel, programmable I/O 1-Wire chip. PIO outputs are configured as open-drain
and provide an on resistance of 100W max. A robust PIO channel-access communication protocol ensures
that PIO output-setting changes occur error-free. A data-valid strobe output can be used to latch PIO logic
states into external circuitry such as a D/A converter (DAC) or microcontroller data bus.
DS2408 operation is controlled over the single-conductor 1-Wire bus. Device communication follows the
standard Dallas Semiconductor 1-Wire protocol. Each DS2408 has its own unalterable and unique 64-bit
ROM registration number that is factory lasered into the chip. The registration number guarantees unique
identification and is used to address the device in a multidrop 1-Wire net environment. Multiple DS2408
devices can reside on a common 1-Wire bus and can operate independently of each other. The DS2408
also supports 1-Wire conditional search capability based on PIO conditions or power-on-reset activity;
the conditions to cause participation in the conditional search are programmable. The DS2408 has an
optional VCC supply connection. When an external supply is absent, device power is supplied parasitically
from the 1-Wire bus. When an external supply is present, PIO states are maintained in the absence of the
1-Wire bus power source. The RSTZ signal is configurable to serve as either a hard-wired reset for the
PIO output or as a strobe for external circuitry to indicate that a PIO write or PIO read has completed.
1-Wire is a registered trademark of Dallas Semiconductor.
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061604
DS2408
ABSOLUTE MAXIMUM RATINGS*
P0 to P7, RSTZ, I/O Voltage to GND
P0 to P7, RSTZ, I/O combined sink current
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Lead Temperature (10s)
*
-0.5V, +6V
20mA
-40°C to +85°C
+150°C
-55°C to +125°C
See J-STD-020A specification
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 0V or ³ VPUP, TA = -40°C or +85°C.)
PARAMETER
SYMBOL
CONDITIONS
1-Wire Pullup
Standard speed
VPUP
Voltage
Overdrive speed
Standby Supply
VCC at VPUP,
ICCS
Current
I/O pin at 0.3V
I/O Pin General Data
1-Wire Pullup
RPUP
(Notes 1, 2)
Resistance
Input Capacitance
CIO
(Notes 3, 4)
I/O pin at VPUP,
Input Load Current
IL
VCC at 0V
High-to-Low
VTL
(Notes 4, 5, 6)
Switching Threshold
Input-Low Voltage
VIL
(Notes 1, 7)
Low-to-High
VTH
(Notes 4, 5, 8)
Switching Threshold
Switching Hysteresis
VHY
(Notes 9, 4)
Output-Low Voltage
VOL
(Note 10)
at 4mA
Standard speed, RPUP =
2.2kW
Overdrive speed, RPUP =
Recovery Time
tREC
2.2kW
(Note 1)
Overdrive speed, Directly
prior to reset pulse; RPUP
= 2.2kW
Rising-Edge Hold-off
Standard speed
tREH
Time (Notes 11, 4)
Overdrive speed
Timeslot Duration
Standard speed
tSLOT
(Notes 1, 12)
Overdrive speed
2 of 36
MIN
2.8
3.3
MAX
5.25
5.25
UNITS
1
µA
2.2
kW
1200
pF
1
µA
3.2
V
0.30
V
0.8
3.4
V
0.16
0.73
V
0.4
V
0.5
TYP
V
5
2
µs
5
0.5
0.5
65
10
5
2
µs
µs
DS2408
PARAMETER
SYMBOL
CONDITIONS
I/O Pin, 1-Wire Reset, Presence-Detect Cycle
Standard speed, VPUP >
4.5V
Reset-Low Time
tRSTL
(Notes 1, 12)
Standard speed
Overdrive speed
Presence-Detect High
Standard speed
tPDH
Time (Note 12)
Overdrive speed
Standard speed, VPUP >
4.5V
Presence-Detect Fall
tFPD
Time (Note 13)
Standard speed
Overdrive speed
Standard speed, VPUP >
4.5V
Presence-Detect Low
tPDL
Time (Note 12)
Standard speed
Overdrive speed
Standard speed, VPUP >
4.5V
Presence-Detect
tMSP
Sample Time (Note 1)
Standard speed
Overdrive speed
I/O Pin, 1-Wire Write
Write-0 Low Time
Standard speed
tW0L
(Notes 1, 12)
Overdrive speed
Write-1 Low Time
Standard speed
t
W1L
(Notes 1, 12, 14)
Overdrive speed
Write Sample Time
Standard speed
tSLS
(Slave Sampling)
Overdrive speed
(Note 12)
I/O Pin, 1-Wire Read
Read-Low Time
Standard speed
tRL
(Notes 1, 15)
Overdrive speed
Read-0 Low Time
Standard speed
tSPD
(Data From Slave)
Overdrive speed
(Note 12)
Read-Sample Time
Standard speed
tMSR
(Notes 1, 12, 15)
Overdrive speed
P0 to P7, RSTZ Pin
Input-Low Voltage
VIL
(Notes 1, 7)
VX = max (VPUP,VCC)
Input-High Voltage
VIH
(Note 1)
Output-Low Voltage
VOL
(Note 10)
at 4mA
Leakage Current
ILP
5.25V at the pin
Output Fall Time
tFPIO
(Notes 4, 16)
Minimum-Sensed
tPWMIN (Notes 4, 17)
PIO Pulse
3 of 36
MIN
TYP
MAX
UNITS
480
720
660
53
15
2
720
80
60
7
1
5
1
8
1
60
240
60
7
280
27
65
75
68
8
75
9
60
8
5
1
15
120
13
15 - e
1.8 - e
60
1.8
8
5
1
15
15 - d
1.8 - d
60
1.8
8
tRL + d
tRL + d
15
1.8
µs
0.30
V
5.25
V
0.4
V
1
µA
ns
5
µs
VX - 0.8
100
1
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
DS2408
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
System Requirement
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only one
device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an
active pullup such as that found in the DS2480B may be required.
If a 2.2kW resistor is used to pull up the data line to VPUP, 5µs after power has been applied,
the parasite capacitance does not affect normal communications.
Guaranteed by design—not production tested.
VTL, VTH are a function of the internal supply voltage.
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line
low.
Voltage above which, during a rising edge on I/O, a logic '1' is detected.
After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to be
detected as logic '0'.
The I-V characteristic is linear for voltages less than 1V.
The earliest recognition of a negative edge is possible at tREH after VTH has been reached
before.
Highlighted numbers are NOT in compliance with the published 1-Wire standards. See
comparison table below.
Interval during the negative edge on I/O at the beginning of a presence detect pulse between
the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of
VPUP.
e represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL
to VTH.
d represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL
to the input high threshold of the bus master.
Interval during the device-generated negative edge on any PIO pin or the RSTZ pin between
the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of
VPUP. PIO pullup resistor = 2.2kW.
Width of the narrowest pulse which trips the activity latch (for any PIO pin) or causes a reset
(for the RSTZ pin). For a pulse duration tPW: If tPW < tPWMIN(min), the pulse will be rejected. If
tPWMIN(min) < tPW < tPWMIN(max), the pulse may or may not be rejected. If tPW > tPWMIN(max) the
pulse will be recognized and latched.
Maximum instantaneous pulldown current through all port pins and the RSTZ pin combined.
No requirement for current balance among different pins.
STANDARD VALUES
DS2408 VALUES
PARAMETER
STANDARD
OVERDRIVE
STANDARD
OVERDRIVE
NAME
SPEED
SPEED
SPEED
SPEED
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tSLOT (incl. tREC)
61µs
(undef.)
7µs
(undef.) 65µs 1) (undef.)
10µs
(undef.)
tRSTL
480µs
(undef.)
48µs
80µs
660µs
720µs
53µs
80µs
tPDH
15µs
60µs
2µs
6µs
15µs
60µs
2µs
7µs
tPDL
60µs
240µs
8µs
24µs
60µs
280µs
7µs
27µs
tW0L
60µs
120µs
6µs
16µs
60µs
120µs
8µs
13µs
tSLS, tSPD
15µs
60µs
2µs
6µs
15µs
60µs
1.8µs
8µs
1)
Intentional change, longer recovery-time requirement due to modified 1-Wire front end.
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DS2408
PIN DESCRIPTION
PIN
1
NAME
N.C.
2
P0
3
VCC
4
5
6
7
8
9
I/O
GND
N.C.
P7
P6
P5
10
RSTZ
11
12
13
14
15
16
P4
P3
P2
P1
N.C.
N.C.
DESCRIPTION
Not Connected
I/O Pin of Channel 0. Logic input/open-drain output with 100W maximum
on-resistance; 0V to 5.25V operating range. Power-on default is
indeterminate. If it is application-critical for the outputs to power up in the
"off" state, the user should attach an appropriate power-on-reset circuit or
supervisor IC to the RSTZ pin.
Optional Power Supply Input. Range 2.8V to 5.25V; must be tied to GND
if not used.
1-Wire Interface. Open-drain, requires external pullup resistor.
Ground
Not Connected
I/O Pin of Channel 7. Same characteristics as P0.
I/O Pin of Channel 6. Same characteristics as P0.
I/O Pin of Channel 5. Same characteristics as P0.
SW configurable PIO reset input ( RST ) or open-drain strobe output
( STRB ). When configured as RST , a LOW input sets all PIO outputs to
the "off" state by setting all bits in the PIO Output Latch State Register.
When configured as STRB , an output strobe will occur after a PIO write
(see Channel-Access Write command) or after a PIO Read (see ChannelAccess Read command). The power-on default function of this pin is
RST .
I/O pin of channel 4; same characteristics as P0
I/O pin of channel 3; same characteristics as P0
I/O pin of channel 2; same characteristics as P0
I/O pin of channel 1; same characteristics as P0
Not connected
Not connected
APPLICATION
The DS2408 is a multipurpose device. Typical applications include port expander for microcontrollers,
remote multichannel sensor/actuator, communication and control unit of a microterminal, or as network
interface of a microcontroller. Typical application circuits and communication examples are found later
in this data sheet (Figures 17 to 22).
OVERVIEW
Figure 1 shows the relationships between the major function blocks of the DS2408. The device has two
main data components: 1) 64-bit lasered ROM, and 2) 64-bit register page of control and status registers.
Figure 2 shows the hierarchical structure of the 1-Wire protocol. The bus master must first provide one of
the eight ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Conditional
Search ROM, 5) Skip ROM, 6) Overdrive-Skip ROM, 7) Overdrive-Match ROM, or 8) Resume. Upon
completion of an Overdrive ROM command byte executed at standard speed, the device will enter
overdrive mode, where all subsequent communication occurs at a higher speed. The protocol required for
these ROM function commands is described in Figure 12. After a ROM function command is successfully executed, the control functions become accessible and the master may provide any one of the five
available commands. The protocol for these control commands is described in Figure 8. All data is read
and written least significant bit first.
5 of 36
DS2408
Figure 1. DS2408 BLOCK DIAGRAM
PARASITE POWER
INTERNAL VCC
VCC
I/O
1-WIRE
FUNCTION
CONTROL
64-BIT
LASERED ROM
REGISTER
FUNCTION
CONTROL
PORT
FUNCTION
CONTROL
GND
CRC16
GENERATOR
PORT
INTERFACE
REGISTER
PAGE
RSTZ
P0
P1
P2
P3
P4
P5
P6
P7
Figure 2. HIERARCHICAL STRUCTURE FOR 1-Wire PROTOCOL
1-Wire Net
Bus
Master
Other
Devices
DS2408
Command
Level:
1-Wire ROM Function
Commands
DS2408-Specific
Control Function
Commands
Available
Commands:
Cmd. Data Field
Codes: Affected:
Read ROM
Match ROM
Search ROM
Skip ROM
Conditional Search
ROM
Overdrive Match
Overdrive Skip
Resume
33h
55h
F0h
CCh
ECh
69h
3Ch
A5h
64-BIT ROM, RC-FLAG
64-BIT ROM, RC-FLAG
64-BIT ROM, RC-FLAG
RC-FLAG
64-BIT ROM, RC-FLAG, Port Status,
Cond. Search Settings,
64-BIT ROM, RC-FLAG, OD-Flag
RC-FLAG, OD-Flag
RC-FLAG
Read PIO Registers
Channel Access Read
Channel Access Write
Write Conditional
Search Register
Reset Activity Latches
F0h
F5h
5Ah
CCh
PIO Registers
Port Input Latches
Port Output Latches
Conditional Search Register
C3h
Activity Latches
6 of 36
DS2408
PARASITE POWER
The DS2408 can derive its power entirely from the 1-Wire bus by storing energy on an internal capacitor
during periods of time when the signal line is high. During low times the device continues to operate from
this “parasite” power source until the 1-Wire bus returns high to replenish the parasite (capacitor) supply.
If power is available, the VCC pin should be connected to the external voltage supply.
Figure 3. 64-BIT LASERED ROM
MSB
LSB
8-BIT
CRC CODE
MSB
8-BIT FAMILY
CODE (29h)
48-BIT SERIAL NUMBER
LSB
MSB
LSB
MSB
LSB
64-BIT LASERED ROM
Each DS2408 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. See Figure 3
for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the
Dallas 1-Wire Cyclic Redundancy Check is available in Application Note 27.
The shift register bits are initialized to 0. Then, starting with the least significant bit of the family code,
one bit at a time is shifted in. After the eighth bit of the family code has been entered, the serial number is
entered. After the serial number has been entered, the shift register contains the CRC value. Shifting in
the eight bits of CRC returns the shift register to all 0s.
Figure 4. 1-Wire CRC GENERATOR
8
5
4
POLYNOMIAL = X + X + X + 1
st
nd
1
STAGE
X
0
rd
2
STAGE
X
1
th
3
STAGE
X
2
th
4
STAGE
X
3
th
5
STAGE
X
4
th
6
STAGE
X
5
th
7
STAGE
X
6
8
STAGE
X
7
X
8
INPUT DATA
REGISTER ACCESS
The registers needed to operate the DS2408 are organized as a Register Page, as shown in Figure 5. All
registers are volatile, i. e., they lose their state when the device is powered down. PIO, Conditional
Search, and Control/Status registers are read/written using the device level Read PIO Registers and Write
Conditional Search Register commands described in subsequent sections and Figure 8 of this document.
7 of 36
DS2408
Figure 5. DS2408 REGISTER ADDRESS MAP
ADDRESS RANGE
ACCESS TYPE
DESCRIPTION
0000h to 0087h
R
Undefined Data
0088h
R
PIO Logic State
0089h
R
PIO Output Latch State Register
008Ah
R
PIO Activity Latch State Register
008Bh
R/W
Conditional Search Channel Selection Mask
008Ch
R/W
Conditional Search Channel Polarity Selection
008Dh
R/W
Control/Status Register
008Eh to 008Fh
R
These Bytes Always Read FFh
PIO Logic-State Register
The logic state of the PIO pins can be obtained by reading this register using the Read PIO Registers
command. Reading this register does not generate a signal at the RSTZ pin, even if it is configured as
STRB . See the Channel-Access commands description for details on STRB .
PIO Logic State Register Bitmap
ADDR
0088h
b7
P7
b6
P6
b5
P5
b4
P4
b3
P3
b2
P2
b1
P1
b0
P0
This register is read-only. Each bit is associated with the pin of the respective PIO channel as shown in
Figure 6. The data in this register is sampled at the last (most significant) bit of the byte that proceeds
reading the first (least significant) bit of this register. See the Read PIO Registers command description
for details.
PIO Output Latch State Register
The data in this register represents the latest data written to the PIO through the Channel-access Write
command. This register is read using the Read PIO Registers command. Reading this register does not
generate a signal at the RSTZ pin, even if it is configured as STRB . See the Channel-access commands
description for details on STRB . This register is not affected if the device reinitializes itself after an ESD
hit.
PIO Output Latch State Register Bitmap
ADDR
0089h
b7
PL7
b6
PL6
b5
PL5
b4
PL4
b3
PL3
b2
PL2
b1
PL1
b0
PL0
This register is read-only. Each bit is associated with the output latch of the respective PIO channel as
shown in Figure 6.
The flip-flops of this register will power up in a random state. If the chip has to power up with all PIO
channels off, a LOW pulse must be generated on the RSTZ pin, e.g., by means of an open-drain CPU
supervisor chip (see Figure 20). When using an RC circuit to generate the power-on reset, make sure that
RSTZ is NOT configured as strobe output (ROS bit in control/status register 008Dh needs to be 0).
8 of 36
DS2408
PIO Activity Latch State Register
The data in this register represents the current state of the PIO activity latches. This register is read using
the Read PIO Registers command. Reading this register does not generate a signal at the RSTZ pin, even
if it is configured as STRB . See the Channel-access commands description for details on STRB .
PIO Activity Latch State Register Bitmap
ADDR
008Ah
b7
AL7
b6
AL6
b5
AL5
b4
AL4
b3
AL3
b2
AL2
b1
AL1
b0
AL0
This register is read-only. Each bit is associated with the activity latch of the respective PIO channel as
shown in Figure 6. This register is cleared to 00h by a power-on reset, by a low pulse on the RSTZ pin
(only if RSTZ is configured as RST input), or by successful execution of the Reset Activity Latches
command.
Figure 6. CHANNEL I/O AND RSTZ SIMPLIFIED LOGIC DIAGRAM
TO PIO LOGIC
STATE REGISTER
PIO ACTIVITY
LATCH
"1"
TO ACTIVITY LATCH
STATE REGISTER
D
Q
POWER ON
RESET
Q R
CLR ACT LATCH
TO PIO
OUTPUT LATCH
STATE REG.
DATA
D
CLOCK
S
CHANNEL
I/O PIN
EDGE
DETECTOR
Q
Q
PIO
OUTPUT
LATCH
PORT
FUNCTION
CONTROL
ROS
STRB
9 of 36
RSTZ
PIN
DS2408
Conditional Search Channel Selection Mask Register
The data in this register controls whether a PIO channel qualifies for participation in the conditional
search command. To include one or more of the PIO channels, the bits in this register that correspond to
those channels need to be set to 1. This register can only be written through the Write Conditional Search
Registers command.
Conditional Search Channel Selection Mask Register Bitmap
ADDR
008Bh
b7
SM7
b6
SM6
b5
SM5
b4
SM4
b3
SM3
b2
SM2
b1
SM1
b0
SM0
This register is read/write. Each bit is associated with the respective PIO channel as shown in Figure 7.
This register is cleared to 00h by a power-on reset
Conditional Search Channel Polarity Selection Register
The data in this register specifies the polarity of each selected PIO channel for the device to respond to
the conditional search command. Within a PIO channel, the data source may be either the channel's input
signal (pin) or the channel's activity latch, as specified by the PLS bit in the Control/Status register at address 008Dh. This register can only be written through the Write Conditional Search Registers command.
Conditional Search Channel Polarity Selection Register Bitmap
ADDR
008Ch
b7
SP7
b6
SP6
b5
SP5
b4
SP4
b3
SP3
b2
SP2
b1
SP1
b0
SP0
This register is read/write. Each bit is associated with the respective PIO channel as shown in Figure 7.
This register is cleared to 00h by a power-on reset.
Figure 7. Conditional Search Logic
PLS
CHANNEL 0
SP0
SM0
CT
AL0
P0
INPUT FROM
CHANNELS 1 TO 6
(NOT SHOWN)
CHANNEL 7
SP7
SM7
AL7
P7
10 of 36
CSR
DS2408
Control/Status Register
The data in this register reports status information, determines the function of the RSTZ pin and further
configures the device for conditional search. This register can only be written through the Write Conditional Search Registers command.
Control/Status Register Bitmap
ADDR
008Dh
b7
VCCP
b6
0
b5
0
b4
0
b3
PORL
b2
ROS
b1
CT
b0
PLS
This register is read/write. Without VCC supply, this register reads 08h after a power-on reset. The functional assignments of the individual bits are explained in the table below. Bits 4 to 6 have no function;
they will always read 0 and cannot be set to 1.
Control/Status Register Details
BIT DESCRIPTION
PLS: Pin or Activity
Latch Select
BIT(S)
b0
CT: Conditional Search
Logical Term
b1
DEFINITION
Selects either the PIO pins or the PIO activity latches as input for the
conditional search.
0: pin selected (default)
1: activity latch selected
Specifies whether the data of two or more channels needs to be OR’ed
or AND’ed to meet the qualifying condition for the device to respond to a
conditional search. If only a single channel is selected in the channel
selection mask (008Bh) this bit is a don't care.
0: bitwise OR (default)
1: bitwise AND
ROS: RSTZ Pin Mode
Control
b2
Configures RSTZ as either RST input or STRB output
0: configured as RST input (default)
PORL: Power-On Reset
Latch
b3
VCCP: VCC Power
Status (Read-Only)
b7
1: configured as STRB output
Specifies whether the device has performed a power-on reset. This bit
can only be cleared to 0 under software control. As long as this bit is 1
the device will always respond to a conditional search.
For VCC powered operation the VCC pin needs to be tied to a voltage
source ³ VPUP.
0: VCC pin is grounded
1: VCC -powered operation
The interaction of the various signals that determine whether the device responds to a conditional search
is illustrated in Figure 7. The selection mask SM selects the participating channels. The polarity selection
SP determines for each channel whether the channel signal needs to be 1 or 0 to qualify. The PLS bit
determines whether all channel signals are taken from the activity latches or I/O pins. The signals of all
channels are fed into an AND gate as well as an OR gate. The CT bit finally selects the AND’ed or
OR’ed result as the conditional search response signal CSR.
Note on CT bit:
OR
The qualifying condition is met if the input (pin state or activity latch) for one or more selected
channels matches the corresponding polarity.
AND For the qualifying condition to be met, the input (pin state or activity latch) for every selected
channel must match the corresponding polarity.
11 of 36
DS2408
Figure 8-1. CONTROL FUNCTIONS FLOW CHART
From ROM Functions
Flow Chart (Figure 12)
Bus Master TX Control
Function Command
F0h
Read PIO Reg.?
To Figure 8
nd
2 Part
N
Note:
To read the three PIO state and latch
register bytes, the target address should
be 0088h. Returned data for a target
address <0088h is undefined.
Y
Bus Master TX
TA1 (T7:T0), TA2 (T15:T8)
N
Address
< 90h?
Y
Address
= 88h?
Y
DS2408 Samples
PIO Pin Status
N
DS2408 sets Register
Address = (T15:T0)
Bus Master RX Data Byte
from Register Address
DS2408 Increments Address
Counter
Master
TX Reset?
Note 1)
See the command
description for the
exact timing of the
PIO pin sampling.
Y
N
Y
Address
< 90h?
N
Master
TX Reset?
Y
N
Bus Master RX CRC16
of Command, Address,
Data Bytes
Bus Master
RX “1”s
N
Master
TX Reset?
Y
To ROM Functions
Flow Chart (Figure 12)
12 of 36
1)
From Figure 8
nd
2 Part
DS2408
Figure 8-2. CONTROL FUNCTIONS FLOW CHART
From Figure 8
st
1 Part
F5h
Channel Access
Read?
5Ah
Channel Access
Write?
N
Y
Note 1)
See the command
description for the
exact timing of the
PIO pin sampling
and updating.
DS2408 Samples
PIO Pin Status
Y
Bus Master RX
PIO Pin Status
2)
1)
Bus Master TX new
PIO Output Data Byte
Bus Master TX
inverted new PIO
Output Data Byte
Sample Count
= 31?
N
Transmission
OK?
Y
2)
DS2408 Updates
PIO Pin Status
N
1)
2)
Bus Master RX
Confirmation AAh
Bus Master RX
CRC16 of Command
and 32 Bytes of PIO
st
Pin Status (1 Pass)
CRC16 of 32 Bytes
of PIO Pin Status
(Subsequent Passes)
DS2408 Samples
PIO Pin Status
To Figure 8
rd
3 Part
Y
PIO Sample
Counter = 0
Bus Master RX
PIO Pin Status
N
Bus Master
RX “1”s
Master
TX Reset?
1) DS2408 Samples
PIO Pin Status
PIO Sample
Counter = 0
Note 2)
If the RSTZ pin is configured as output, a
STRB\ is generated
during the first two bits
of this byte.
1)
DS2408 Samples
PIO Pin Status
DS2408 Increments
PIO Sample Counter
Master
TX Reset?
1)
N
Y
Bus Master RX
PIO Pin Status
N
N
Master
TX Reset?
Y
Y
To Figure 8
st
1 Part
From Figure 8
rd
3 Part
13 of 36
DS2408
Figure 8-3. CONTROL FUNCTIONS FLOW CHART
From Figure 8
nd
2 Part
CCh
Write C. Search
Reg.?
C3h
Reset Activity
Latches?
N
Y
N
Y
Bus Master TX
TA1 (T7:T0), TA2 (T15:T8)
DS2408 Clears all
PIO Activity Latches
Note:
To read 8Bh to 8Dh
use the Read PIO
Registers command.
N
Master
TX Reset?
8Bh£ Address £
8Dh?
Y
Y
Bus Master TX
Data Byte
Bus Master
RX “1”s
Master
TX Reset?
DS2408 Increments Address
Counter
N
Y
DS2408 Copies
Data to Register
Master
TX Reset?
Bus Master RX
Confirmation AAh
N
N
Master
TX Reset?
Y
Y
To Figure 8
nd
2 Part
14 of 36
N
DS2408
CONTROL FUNCTION COMMANDS
Once a ROM function command is completed, the Control Function Commands can be issued. The
Control Functions Flow Chart (Figure 8) describes the protocols necessary for accessing the PIO
channels and the special function registers of the DS2408. The communication between the master and
the DS2408 takes place either at standard speed (default, OD = 0) or at overdrive speed (OD = 1). If not
explicitly set into the overdrive mode, the device operates at standard speed.
Read PIO Registers [F0h]
The Read PIO Registers command is used to read any of the device's registers. After issuing the
command, the master must provide the 2-byte target address. After these two bytes, the master reads data
beginning from the target address and may continue until address 008Fh. If the master continues reading,
it will receive an inverted 16-bit CRC of the command, address bytes, and all data bytes read from the
initial starting byte through the end of the register page. This CRC16 is the result of clearing the CRC
generator and then shifting in the command byte followed by the two address bytes and the data bytes
beginning at the first addressed location and continuing through to the last byte of the register page. After
the bus master has received the CRC16, the DS2408 responds to any subsequent read-time slots with
logical 1’s until a 1-Wire Reset command is issued. If this command is issued with target address 0088h
(PIO Logic State Register), the PIO sampling takes place during the transmission of the MS bit of TA2. If
the target address is lower than 0088h, the sampling takes place while the master reads the MS bit from
address 0087h.
Channel-Access Read [F5h]
In contrast to reading the PIO logical state from address 88h, this command reads the status in an endless
loop. After 32 bytes of PIO pin status the DS2408 inserts an inverted CRC16 into the data stream, which
allows the master to verify whether the data was received error-free. A Channel-Access Read can be
terminated at any time with a 1-Wire Reset.
Figure 9. CHANNEL-ACCESS READ TIMING
Example - Sampled State = 72h
MS 2 bits of previous byte (8Dh)
LS 2 bits of data
byte (72h)
IO (1-Wire)
STRB\
tSPD
Sampling Point
tSPD
tSPD
Notes:
1) The "previous byte" could be the command code, the data byte resulting from the previous PIO
sample, or the MS byte of a CRC16. The example shows a read-1 time slot.
2) The sample point timing also applies to the Channel-access Write command, with the "previous byte"
being the write confirmation byte (AAh). No STRB pulse results when sampling occurs during a
Channel-Access Write command.
15 of 36
DS2408
The status of all eight PIO channels is sampled at the same time. The first sampling occurs during the last
(most significant) bit of the command code F5h. While the master receives the MSB of the PIO status
(i.e., the status of pin P7) the next sampling occurs and so on until the master has received 31 PIO
samples. Next, the master receives the inverted CRC16 of the command byte and 32 PIO samples (first
pass) or the CRC of 32 PIO samples (subsequent passes). While the last (most significant) bit of the CRC
is transmitted the next PIO sampling takes place. The delay between the beginning of the time slot and
the sampling point is independent of the bit value being transmitted and the data direction (see Figure 9).
If the RSTZ pin is configured as STRB , a strobe signal will be generated during the transmission of the
first two (least significant) bits of PIO data. The strobe can signal a FIFO or a microcontroller to apply
the next data byte at the PIO for the master to read through the 1-Wire line.
Channel-Access Write [5Ah]
The Channel-Access Write command is the only way to write to the PIO output-latch state register
(address 0089h), which controls the open-drain output transistors of the PIO channels. In an endless loop
this command first writes new data to the PIO and then reads back the PIO status. The implicit read-afterwrite can be used by the master for status verification or for a fast communication with a microcontroller
that is connected to the port pins and RSTZ for synchronization. A Channel-Access Write can be terminated at any time with a 1-Wire Reset.
Figure 10. CHANNEL-ACCESS WRITE TIMING
Case #1 - MS Bit of new PIO state is 0
Example - Old State = 39h, New state = 72h
MS 2 bits of inverted
new-state byte (8Dh)
LS 2 bits of confirmation byte (AAh)
Case #2 - MS Bit of new PIO state is 1
Example - Old State = 72h, New state = 93h
MS 2 bits of inverted
new-state byte (6Ch)
VTH
IO (1-Wire)
PIO
LS 2 bits of confirmation byte (AAh)
39h
72h
72h
tSPD
STRB\
tSLS
tSPD
93h
tSPD
tSPD
Note:
Both examples assume that the RSTZ pin is configured as STRB output. If RSTZ is configured as RST
input (default), the RSTZ pin needs to be tied high (to VCC or VPUP) for the Channel-Access Write to
function properly. Leaving the pin floating will force the output transistors of the PIO channels to the
"off" state and the PIO output latches will all read "1". See Figure 6 for a schematic of the logic.
After the command code the master transmits a byte that determines the new state of the PIO output
transistors. The first (least significant) bit is associated to P0. To switch the output transistor off (nonconducting) the corresponding bit value is 1. To switch the transistor on that bit needs to be 0. This way
the data byte transmitted as the new PIO output state arrives in its true form at the PIO pins. To protect
the transmission against data errors, the master has to repeat the new PIO byte in its inverted form. Only
if the transmission was successful will the PIO status change. The actual transition at the PIO to the new
state occurs during the last (most significant) bit of the inverted new PIO data byte and depends on the
polarity of that bit, as shown in Figure 10. If this bit is a 1, the transition begins after tSLS is expired; in
case of a 0, the transition begins at the end of the time slot, when the VTH threshold is crossed. To inform
the master about the successful change of the PIO status, the DS2408 transmits a confirmation byte with
16 of 36
DS2408
the data pattern AAh. If the RSTZ pin is configured as STRB , a strobe signal will be generated during the
transmission of the first two (least significant) bits of the confirmation byte. The strobe can signal a FIFO
or a microcontroller to read the new data byte from the PIO. While the last bit of the confirmation byte is
transmitted, the DS2408 samples the status of the PIO pins, as shown in Figure 9, and sends it to the
master. Depending on the data, the master can either continue writing more data to the PIO or issue a 1Wire reset to end the command.
Write Conditional Search Register [CCh]
This command is used to tell the DS2408 the conditions that need to be met for the device to respond to a
Conditional Search command, to define the function of the RSTZ pin and to clear the power-on reset flag.
After issuing the command the master sends the 2-byte target address, which must be a value between
008Bh and 008Dh. Next the master sends the byte to be written to the addressed cell. If the address was
valid, the byte is immediately written to its location in the register page. The master now can either end
the command by issuing a 1-Wire reset or send another byte for the next higher address. Once register
address 008Dh has been written, any subsequent data bytes will be ignored. The master has to send a 1Wire reset to end the command. Since the Write Conditional Search Register flow does not include any
error-checking for the new register data, it is important to verify correct writing by reading the registers
using the Read PIO Registers command.
Reset Activity Latches [C3h]
Each PIO channel includes an activity latch that is set whenever there is a state transition at a PIO pin.
This change may be caused by an external event/signal or by writing to the PIO. Depending on the
application there may be a need to reset the activity latch after having captured and serviced an external
event. Since there is only read access to the PIO Activity Latch State Register, the DS2408 supports a
special command to reset the latches. After having received the command code, the device resets all
activity latches simultaneously. There are two ways for the master to verify the execution of the Reset
Activity Latches command. The easiest way is to start reading from the 1-Wire line right after the
command code is transmitted. In this case the master will read AAh bytes until it sends a 1-Wire reset.
The other way to verify execution is to read register address 008Ah.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the
DS2408 is a slave device. The bus master is typically a microcontroller or PC. For small configurations
the 1-Wire communication signals can be generated under software control using a single port pin. For
multisensor networks, the DS2480B 1-Wire line driver chip or serial port adapters based on this chip
(DS9097U series) are recommended. This simplifies the hardware design and frees the microprocessor
from responding in real time.
The discussion of this bus system is broken down into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in
terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from
the bus master.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or tri-state outputs. The 1-Wire port of the DS2408 is open-drain with an internal circuit equivalent
to that shown in Figure 11.
17 of 36
DS2408
Figure 11. HARDWARE CONFIGURATION
VPUP
SIMPLE BUS MASTER
RPUP
RX
DS2408 1-Wire PORT
SEE
TEXT
DATA
RX
TX
TX
RX = RECEIVE
100W
MOSFET
TX = TRANSMIT
OPEN-DRAIN
PORT PIN
DS2480B BUS MASTER
+5V
VDD VPP
HOST CPU
SERIAL
PORT
SERIAL IN
SERIAL OUT
POL
1-W
RXD
NC
TO 1-Wire DATA
TXD GND
DS2480B
A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed the 1-Wire bus
has a maximum data rate of 15.3kbps. Communication speed for 1-Wire devices can be typically boosted
to 142kbps by activating the overdrive mode; however, the maximum overdrive data rate for the DS2408
is 100kbps. The value of the pullup resistor primarily depends on the network size and load conditions.
For most applications the optimal value of the pullup resistor will be approximately 2.2kW for standard
speed and 1.5kW for overdrive speed.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 16µs (overdrive speed) or more than 120µs (standard speed), one or more devices on the
bus may be reset. With the DS2408 the bus must be left low for no longer than 13µs at overdrive speed to
ensure that none of the slave devices on the 1-Wire bus performs a reset. The DS2408 communicates
properly when used in conjunction with a DS2480B 1-Wire driver and serial port adapters that are based
on this driver chip. When operating the device in overdrive or below 4.5V, some 1-Wire I/O timing
values must be modified (see EC table).
18 of 36
DS2408
TRANSACTION SEQUENCE
The protocol for accessing the DS2408 through the 1-Wire port is as follows:
§ Initialization
§ ROM Function Command
§ Control Function Command
§ Transaction/Data
Illustrations of the transaction sequence for the various control function commands are found later in this
document.
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that the DS2408 is on the bus and is ready to
operate. For more details, see the 1-Wire Signaling section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the seven ROM function commands. All
ROM function commands are eight bits long. A list of these commands follows (see the flowchart in
Figure 12).
Read ROM [33h]
This command allows the bus master to read the DS2408's 8-bit family code, unique 48-bit serial number,
and 8-bit CRC. This command can only be used if there is a single device on the bus. If more than one
slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time
(open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will
result in a mismatch of the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS2408 on a multidrop bus. Only the DS2408 that exactly matches the 64-bit ROM sequence will
respond to the following control function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with either single or multiple devices on the
bus.
Search ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the
1-Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a
process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM
process is the repetition of a simple three-step routine: read a bit, read the complement of the bit, then
write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of
the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The
remaining number of devices and their ROM codes may be identified by additional passes. See
Application Note 187 for a detailed discussion on the Search ROM command process including a
software example.
Conditional Search [ECh]
The Conditional Search ROM command operates similarly to the Search ROM command except that only
devices fulfilling the specified condition will participate in the search. The condition is specified by the
Conditional Search channel and polarity selection (addresses 008Bh, 008Ch), the bit functions CT and
19 of 36
DS2408
PLS of the Control/Status Register (address 008Dh), and the state of the PIO channels. See Figure 7 for a
description of the Conditional Search logic. The device also responds to the Conditional Search if the
PORL bit is set. The Conditional Search ROM provides an efficient means for the bus master to determine devices on a multidrop system that have to signal an important event, such as a state change at a
PIO pin caused by an external signal. After each pass of the conditional search that successfully determined the 64-bit ROM for a specific device on the multidrop bus, that particular device can be individually accessed as if a Match ROM had been issued, since all other devices will have dropped out of the
search process and will be waiting for a reset pulse.
Skip ROM [CCh]
This command can save time in a single-drop bus system by allowing the bus master to access the control
functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a
Read command is issued following the Skip ROM command, data collision will occur on the bus as
multiple slaves transmit simultaneously (open-drain pulldowns will produce a wired-AND result).
Resume Command [A5h]
In a typical application the DS2408 can be accessed several times to complete a control or adjustment
function. In a multidrop environment this means that the 64-bit ROM sequence of a Match ROM command has to be repeated for every access. To maximize the data throughput in a multidrop environment,
the Resume Command function is implemented. This function checks the status of the RC flag and, if it is
set, directly transfers control to the control functions, similar to a Skip ROM command. The only way to
set the RC flag is through successfully executing the Match ROM, Search ROM, Conditional Search
ROM, or Overdrive-Match ROM command. Once the RC flag is set, the device can be repeatedly
accessed through the Resume Command function. Accessing another device on the bus will clear the RC
flag, preventing two or more devices from simultaneously responding to the Resume Command function.
Skip ROM [3Ch]
On a single-drop bus this command can save time by allowing the bus master to access the control
functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the
Overdrive Skip ROM sets the DS2408 in the overdrive mode (OD = 1). All communication following
this command has to occur at overdrive speed until a reset pulse of minimum 480µs duration resets all
devices on the bus to standard speed (OD = 0). When issued on a multidrop bus this command will set all
overdrive-supporting devices into overdrive mode. To subsequently address a specific overdrivesupporting device, a reset pulse at overdrive speed has to be issued followed by a Match ROM or Search
ROM command sequence. This will speed up the time for the search process. If more than one slave
supporting overdrive is present on the bus and the Overdrive Skip ROM command is followed by a Read
command, data collision will occur on the bus as multiple slaves transmit simultaneously (open-drain
pulldowns will produce a wired-AND result).
Overdrive Match ROM [69h]
The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at overdrive
speed allows the bus master to address a specific DS2408 on a multidrop bus and to simultaneously set it
in overdrive mode. Only the DS2408 that exactly matches the 64-bit ROM sequence will respond to the
subsequent control function command. Slaves already in overdrive mode from a previous Overdrive Skip
or Match command will remain in overdrive mode. All overdrive-capable slaves will return to standard
speed at the next Reset Pulse of minimum 480µs duration. The Overdrive Match ROM command can be
used with either single or multiple devices on the bus.
20 of 36
DS2408
Figure 12-1. ROM FUNCTIONS FLOW CHART
Bus Master TX
Reset Pulse
From Control Functions
Flow Chart (Figure 8)
From Figure 12, 2
OD
Reset Pulse?
N
nd
Part
OD = 0
Y
Bus Master TX ROM
Function Command
33h
Read ROM
Command?
Y
RC = 0
DS2408 TX
Presence Pulse
N
55h
Match ROM
Command?
F0h
Search ROM
Command?
N
Y
To Figure 12
nd
2 Part
ECh
Cond. Search
Command?
N
Y
RC = 0
N
Y
RC = 0
RC = 0
N
Condition Met?
Y
DS2408 TX
Family Code
(1 Byte)
N
Bit 0
Match?
N
N
N
DS2408 TX Bit 1
DS2408 TX Bit 1
Master TX Bit 1
N
Bit 1
Match?
Bit 1
Match?
Y
Y
DS2408 TX Bit 63
DS2408 TX Bit 63
Master TX Bit 63
DS2408 TX Bit 63
DS2408 TX Bit 63
Master TX Bit 63
Master TX Bit 63
N
Bit 63
Match?
Y
DS2408 TX Bit 1
DS2408 TX Bit 1
Master TX Bit 1
Y
DS2408 TX
CRC Byte
Bit 0
Match?
Y
Master TX Bit 1
Bit 1
Match?
N
Bit 0
Match?
Y
DS2408 TX
Serial Number
(6 Bytes)
DS2408 TX Bit 0
DS2408 TX Bit 0
Master TX Bit 0
DS2408 TX Bit 0
DS2408 TX Bit 0
Master TX Bit 0
Master TX Bit 0
N
N
Bit 63
Match?
Y
Bit 63
Match?
Y
RC = 1
RC = 1
To Control Functions
Flow Chart (Figure 8)
21 of 36
Y
RC = 1
To Figure 12
nd
2 Part
From Figure 12
nd
2 Part
DS2408
Figure 12-2. ROM FUNCTIONS FLOW CHART
To Figure 12, 1st Part
From Figure 12
1st Part
CCh
Skip ROM
Command?
Y
N
A5h
Resume
Command?
3Ch
Overdrive
Skip ROM?
N
N
Y
Y
Y
RC = 0 ; OD = 1
RC = 0 ; OD = 1
RC = 0
RC = 1 ?
69h
N
Overdrive Match
ROM?
N
Master TX Bit 0
Y
Master
TX Reset ?
Y
N
Bit 0
Match?
Y
N
Master TX Bit 1
Master
TX Reset ?
Y
N
Bit 1
Match?
Y
N
Master TX Bit 63
N
Bit 63
Match?
Y
From Figure 12
1st Part
RC = 1
To Figure 12
1st Part
22 of 36
DS2408
1-WIRE SIGNALING
The DS2408 requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write-Zero, Write-One, and
Read-Data. Except for the presence pulse, the bus master initiates all these signals. The DS2408 can
communicate at two different speeds, standard speed, and overdrive speed. If not explicitly set into the
overdrive mode, the DS2408 will communicate at standard speed. While in overdrive mode, the fast
timing applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the VTL threshold.
To get from active to idle, the voltage needs to rise from VILMAX past the VTH threshold. The VILMAX
voltage is relevant for the DS2408 when determining a logical level, not triggering any events.
Figure 13 shows the initialization sequence required to begin any communication with the DS2408. A
Reset Pulse followed by a Presence Pulse indicates the DS2408 is ready to receive data, given the correct
ROM and control function command. If the bus master uses slew-rate control on the falling edge, it must
pull down the line for tRSTL + tF to compensate for the edge. A tRSTL duration of 480µs or longer will exit
the overdrive mode returning the device to standard speed. If the DS2408 is in overdrive mode and tRSTL
is no longer than 80µs the device will remain in overdrive mode.
Figure 13. INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES”
MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”
VIHMASTER
VTH
VTL
VILMAX
0V
tMSP
e
VPUP
tF
tRSTL
RESISTOR
tPDH
MASTER
tPDL
tRSTH
tREC
DS2408
After the bus master has released the line it goes into receive mode (RX). The 1-Wire bus is then pulled
to VPUP via the pullup resistor or, in case of a DS2480B driver, by active circuitry. When the VTH
threshold is crossed, the DS2408 waits for tPDH and then transmits a Presence Pulse by pulling the line
low for tPDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP.
The tRSTH window must be at least the sum of tPDHMAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is
expired, the DS2408 is ready for data communication. In a mixed population network, tRSTH should be
extended to a minimum of 480µs at standard speed and 48µs at overdrive speed to accommodate other 1Wire devices.
23 of 36
DS2408
Read/Write Time Slots
Data communication with the DS2408 takes place in time slots, which carry a single bit each. Write time
slots transport data from bus master to slave. Read time slots transfer data from slave to master. The
definitions of the write and read time slots are illustrated in Figure 14.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line
falls below the threshold VTL, the DS2408 starts its internal time base. The tolerance of the slave time
base creates a slave-sampling window, which stretches from tSLSMIN to tSLSMAX. The voltage on the data
line at the sampling point determines whether the DS2408 decodes the time slot as 1 or 0.
Master-to-Slave
For a write-one time slot, the voltage on the data line must have crossed the VTHMAX threshold after the
write-one low time tW1LMAX has expired. For a write-zero time slot, the voltage on the data line must stay
below the VTHMIN threshold until the write-zero low time tW0LMIN has expired. For most reliable
communication, the voltage on the data line should not exceed VILMAX during the entire tW0L window.
After the VTHMAX threshold has been crossed, the DS2408 needs a recovery time tREC before it is ready for
the next time slot.
Figure 14. READ/WRITE TIMING DIAGRAM
Write-One Time Slot
tW1L
VPUP
VIHMASTER
VTH
DS2408
Sampling
Window
VTL
VILMAX
0V
tF
e
tSLSMIN
tSLSMAX
tSLOT
Write-Zero Time Slot
tW0L
VPUP
VIHMASTER
VTH
DS2408
Sampling
Window
VTL
VILMAX
0V
tF
tREC
tSLSMIN
tSLSMAX
24 of 36
tSLOT
DS2408
Read-Data Time Slot
tMSR
tRL
VPUP
VIHMASTER
VTH
Master
Sampling
Window
VTL
VILMAX
0V
tF
tREC
d
tSPDMIN
RESISTOR
tSPDMAX
MASTER
tSLOT
DS2408
Slave-to-Master
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below
VTLMIN until the read low time tRL has expired. During the tRL window, when responding with a 0, the
DS2408 starts pulling the data line low; its internal timing generator determines when this pulldown ends
and the voltage starts rising again. When responding with a 1, the DS2408 does not hold the data line low
at all, and the voltage starts rising as soon as tRL is over.
The sum of tRL + d (rise time) on one side and the internal timing generator of the DS2408 on the other
side define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read
from the data line. For most reliable communication, tRL should be as short as permissible and the master
should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until
tSLOT is expired. This guarantees sufficient recovery time tREC for the DS2408 to get ready for the next
time slot.
Improved Network Behavior
In a 1-Wire environment, line termination is possible only during transients controlled by the bus master
(1-Wire driver). 1-Wire networks therefore are susceptible to noise of various origins. Depending on the
physical size and topology of the network, reflections from end points and branch points can add up or
cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire
communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal
glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization
with the master and, as a consequence, result in a Search ROM command coming to a dead end or cause a
device level command to abort. For better performance in network applications, the DS2408 uses a new
1-Wire front end, which makes it less sensitive to noise and also reduces the magnitude of noise injected
by the slave device itself.
The 1-Wire front end of the DS2408 differs from traditional slave devices in four characteristics.
1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the
line impedance than a digitally switched transistor, converting the high-frequency ringing known
from traditional devices into a smoother low-bandwidth transition. The slew rate control is specified
by the parameter tFPD, which has different values for standard and overdrive speed.
2) There is additional lowpass filtering in the circuit that detects the falling edge at the beginning of a
time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply
at overdrive speed.
25 of 36
DS2408
3) The input buffer was designed with hysteresis. If a negative glitch crosses VTH but doesn’t go below
VTH - VHY, it will not be recognized (Figure 15, Case A). The hysteresis is effective at any 1-Wire
speed.
4) There is a time window specified by the rising edge hold-off time tREH during which glitches will be
ignored, even if they extend below the VTH - VHY threshold (Figure 15, Case B, tGL < tREH). Deep
voltage droops or glitches that appear late after crossing the VTH threshold and extend beyond the tREH
window cannot be filtered out and will be taken as the beginning of a new time slot (Figure 15, Case
C, tGL ³ tREH).
Figure 15. NOISE SUPPRESSION SCHEME
tREH
VPUP
tREH
VTH
VHY
Case A
0V
Case B
tGL
Case C
tGL
CRC GENERATION
The DS2408 has two different types of cyclic redundancy checks (CRCs). One CRC is an 8-bit type and
is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from
the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2408 to determine if
the ROM data has been received error free. The equivalent polynomial function of this CRC is X8 + X5 +
X4 + 1. This 8-bit CRC is received in the true (noninverted) form. It is computed at the factory and lasered
into the ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function X16
+ X15 + X2 + 1. This CRC is used for error detection when reading data through the end of the register
page using the Read PIO Registers command, for fast verification of the data transfer when writing to or
reading from the scratchpad, and when reading from the PIO using the Channel-access Read command.
In contrast to the 8-bit CRC, the 16-bit CRC is always communicated in the inverted form. A CRCgenerator inside the DS2408 chip (Figure 16) calculates a new 16-bit CRC as shown in the command
flow chart of Figure 8. The bus master compares the CRC value read from the device to the one it
calculates from the data and decides whether to continue with an operation or to reread the portion of the
data with the CRC error.
With the Read PIO Registers flow chart, the 16-bit CRC value is the result of shifting the command byte
into the cleared CRC generator, followed by the 2 address bytes and the data bytes beginning at the target
address and ending with the last byte of the register page, address 008Fh.
With the initial pass through the Channel-access Read command flow, the CRC is generated by first
clearing the CRC generator and then shifting in the command code followed by 32 bytes of PIO pin data.
Subsequent passes through the command flow will generate a 16-bit CRC that is the result of clearing the
CRC generator and then shifting in 32 bytes read from the PIO pins. For more information on generating
CRC values see Application Note 27.
26 of 36
DS2408
Figure 16. CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL
POLYNOMIAL = X
st
nd
1
STAGE
X
0
X
th
8
X
th
10
STAGE
X
9
X
th
3
STAGE
1
9
STAGE
X
rd
2
STAGE
th
th
11
STAGE
10
X
11
X
12
4
14
STAGE
X
13
X
2
+X +1
th
th
6
STAGE
X
th
13
STAGE
15
5
STAGE
X
th
12
STAGE
X
3
+X
th
4
STAGE
2
16
5
th
7
STAGE
X
6
8
STAGE
X
th
7
th
15
STAGE
16
STAGE
14
X
15
X
16
INPUT DATA
CRC
OUTPUT
Figure 17. DS2408 AS SLAVE INTERFACE FOR MICROCONTROLLER
PULLUP PROVIDED BY CPU
47U
VCC
VCC
GND
1W
3
4
5
VCC
IO
P0
P1
P2
P3
P4
P5
P6
P7
GND
RSTZ
2
14
13
12
11
9
8
7
3
4
5
6
7
8
9
10
10
12
42
DS2408
15
16
17
18
19
20
21
22
23
24
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
RST
ALE
PSEN
EA
P3.0/RXD0
P3.1/TXD0
P3 .2 / INT0
P3 .3 / INT1
P3.4/T0
P3.5/T1
P3 .6 / WR
P3 .7 / RD
P2.0/AD8
P2.1/AD9
P2.2/AD10
P2.3/AD11
P2.4/AD12
P2.5/AD13
P2.6/AD14
P2.7/AD15
XTAL2
XTAL1
RTCX1
RTCX2
DS80C520
8051 Equiv CPU
The data direction (upload/download) is determined by application-specific data protocol.
27 of 36
50
49
48
47
46
45
44
43
39
38
30
31
32
33
34
35
36
37
28
27
DS2408
Figure 18. DS2408 AS SLAVE INTERFACE FOR INTELLIGENT DISPLAY
1
6
2
5
4
LCD Display
DS9503
VCC
47U
1
2
3
4
5
6
VCC
5VDC
GND
1W
3
4
5
VCC
2
14
13
12
11
9
8
7
P0
P1
P2
P3
P4
P5
P6
P7
IO
GND
RSTZ
7
8
9
10
11
12
13
14
VCC
10
15
16
GND
VCC
CONTRAST
D/ C
R/ W
S TB
D0
D1
D2
D3
D4
D5
D6
D7
ACM1601B 16X1 Display
with Back Light
3
Local iButton Probe
47
LEDA
LEDK
DS2408
VCC
1 2 3 4 5 6 7 8 9 10
Up
10K
Down
Select
Figure 19. DS2408 AS MICROCONTROLLER PORT EXPANDER
VCC
DS2408
3
VCC
P0
P1
P2
P3
P4
P5
P6
P7
VC
C
4
5
MICROCONTROLLER
WITH FEW I/O PINS
VCC
OSC1/P5
OSC2/P4
CLR/P3
GND
P0
P1
P2/CK
GND
2.2K
RSTZ
VCC
1
2
3
4
IO
VCC
8
7
6
5
4
5
VCC
P0
P1
P2
P3
P4
P5
P6
P7
IO
GND
RSTZ
24 I/O LINES OR
3 BYTE-WIDE
BUSES FROM A
SINGLE PIN
VCC
2
14
13
12
11
9
8
7
10
DS2408
3
4
5
VCC
IO
P0
P1
P2
P3
P4
P5
P6
P7
GND
RSTZ
28 of 36
10
DS2408
3
PIC12C508
2
14
13
12
11
9
8
7
2
14
13
12
11
9
8
7
10
DS2408
Figure 20. DS2408 AS µC-OPERATED KEYBOARD SCANNER
10kW
10U
1 2 3 4 5 6 7 8 9 10
VCC
VCC
GND
1W
3
VCC
4
IO
5
2
14
13
12
11
9
8
7
P0
P1
P2
P3
P4
P5
P6
P7
GND
RSTZ
10
DS2408
VCC
POR Circuit
VCC
RST
GND
DS1811
The DS1811 has
an internal pull-up
resistor of 5.5 kW
To More Switch Rows
(Up to 4 x 4, 3 x 5 or 2 x 6)
Figure 21. DS2408 AS PARASITE-POWERED PUSH-BUTTON SENSOR
VCC
0.1U
3
VCC
P0
P1
P2
P3
P4
P5
P6
P7
1W
GND
4
5
IO
GND
RSTZ
2
14
13
12
11
9
8
7
10
DS2408
1 2 3 4 5 6 7 8 9 10
100k
BAT54
Parasite
Power
SWITCHES OR PUSH-BUTTONS
29 of 36
DS2408
Figure 22. DS2408 AS MULTIPURPOSE SENSOR/ACTUATOR
10kW
47U
1 2 3 4 5 6 7 8 9 10
SWITCHES
OR PUSHBUTTONS
VCC
VCC
1W
GND
3
4
5
VCC
IO
P0
P1
P2
P3
P4
P5
P6
P7
GND
RSTZ
2
14
13
12
11
9
8
7
VCC
4mA
10
1kW
OPTOISO
ISOLATED
OUTPUT
6
VCC
DS2408
1
5
2
BSS-84
4
DRY
CONTACT
1N4004
5V
LED
470W
30 of 36
8mA
VCC
LED INDICATOR
DS2408
Command-Specific 1-Wire Communication Protocol—Legend
SYMBOL
DESCRIPTION
RST
PD
Select
RPR
CAR
CAW
WCS
RAL
TA
<data>
CRC16\
FF loop
AA loop
<32 samples>,
CRC16\ loop
<new state>, <new
state\>
AAh, <read back>
<new state>,
<invalid>
1-Wire Reset Pulse generated by master.
1-Wire Presence Pulse generated by slave.
Command and data to satisfy the ROM function protocol.
Command "Read PIO Registers".
Command "Channel-Access Read".
Command "Channel-Access Write".
Command "Write Conditional Search Register".
Command "Reset Activity Latches".
Target Address TA1, TA2.
Transfer of an undetermined amount of data.
Transfer of an inverted CRC16.
Indefinite loop where the master reads FF bytes.
Indefinite loop where the master reads AA bytes.
Indefinite loop where the master reads 32 PIO samples followed by an inverted CRC16.
Transfer of 2 bytes, where the second byte is the bit-inverse of the first byte. The first
byte will be taken as the new PIO state.
Transfer of 2 bytes, where the first byte is a constant (AAh) and the second byte is the
current PIO state.
Transfer of 2 bytes, where the second byte is NOT the bit-inverse of the first byte.
Command-Specific 1-Wire Communication Protocol—Color Codes
Master to slave
Slave to master
Read PIO Registers (Success)
RST
PD
Select
RPR
TA
<data>
CRC16\
FF loop
Read PIO Registers (Fail Address)
RST
PD
Select
RPR
TA
FF loop
Channel-Access Read (Cannot Fail)
RST
PD
Select
CAR
<32 samples>, CRC16\ loop
31 of 36
DS2408
Channel-Access Write (Success)
RST
PD
Select
CAW
<new state>, <new state\>
AAh, <read back>
Loop
Channel-Access Write (Fail New State)
RST
PD
Select
CAW
<new state>, <invalid>
FF loop
Write Conditional Search Register (Success)
RST
PD
Select
WCS
TA
<data>
FF loop
Write Conditional Search Register (Fail Address)
RST
PD
Select
WCS
TA
FF loop
Reset Activity Latches (Cannot Fail)
RST
PD
Select
RAL
AA loop
COMMUNICATION EXAMPLES
The examples in this section demonstrate the use of ROM and control functions in typical situations. The
first two examples are related to Figure 17. They show how to write to the PIO with readback for
verification or for receiving an immediate response (example 1) and how to read from the PIO in an
endless loop (example 2). The third example assumes a network of multiple DS2408s where each of the
devices is connected to 8 pushbuttons, as in Figure 21.
Example 1
Task: Write to the PIO with readback for verification or for receiving an immediate response.
This task is broken into the following steps:
1) Configure RSTZ as STRB output.
2) Verify configuration setting.
3) Write to the PIO and read back the response.
With only a single DS2408 connected to the bus master, the communication is as follows:
MASTER MODE
Step 1
TX
RX
TX
TX
TX
TX
TX
DATA (LSB FIRST)
(Reset)
(Presence)
CCh
CCh
8Dh
00h
04h
32 of 36
COMMENTS
Reset pulse
Presence pulse
Issue Skip ROM command
Issue Write Conditional Search Register
command
TA1, target address = 8Dh
TA2, target address = 008Dh
Write byte to Control/Status Register
DS2408
MASTER MODE
TX
RX
Step 2
TX
TX
TX
TX
RX
TX
RX
Step 3
TX
TX
TX
TX
(—)
DATA (LSB FIRST)
(Reset)
(Presence)
CCh
F0h
8Dh
00h
84h
(Reset)
(Presence)
CCh
5Ah
<PIO output byte>
<inverted PIO output byte>
(—)
RX
(—)
RX
TX
TX
RX
RX
AAh
(—)
<PIO pin status byte>
<PIO output byte>
<inverted PIO output byte>
AAh
<PIO pin status byte>
(—)
(—)
TX
RX
(Reset)
(Presence)
COMMENTS
Reset pulse
Presence pulse
Issue Skip ROM command
Issue Read PIO Registers command
TA1, target address = 8Dh
TA2, target address = 008Dh
Read Control/Status Register and verify
Reset pulse
Presence pulse
Issue Skip ROM command
Issue Channel-access Write command
Write byte to PIO
Write inverted byte to PIO
DS2408 updates PIO status if transmission
was OK
Read for verification (AAh = success)
DS2408 samples PIO pin status
Read PIO pin status
Write byte to PIO (next byte)
Write inverted byte to PIO (next byte)
Read for verification (AAh = success)
Read PIO pin status
Repeat the previous 4 steps with more PIO
output data as needed in the application.
Reset pulse
Presence pulse
When using this communication example to send data to a remote microcontroller, as in Figure 17,
synchronization between the master and the remote microcontroller can be maintained by transmitting
data packets that begin with a length byte and end with a CRC16. See Application Note 114, section
"UNIVERSAL DATA PACKET" for details.
Example 2
Task: Read from the PIO in an endless loop.
This task is broken into the following steps:
1) Configure RSTZ as STRB output.
2) Verify configuration setting.
3) Read from the PIO.
With only a single DS2408 connected to the bus master, the communication is as follows:
MASTER MODE
Step 1
TX
RX
TX
DATA (LSB FIRST)
(Reset)
(Presence)
CCh
TX
CCh
TX
TX
8Dh
00h
33 of 36
COMMENTS
Reset pulse
Presence pulse
Issue Skip ROM command
Issue Write Conditional Search Register
command
TA1, target address = 8Dh
TA2, target address = 008Dh
MASTER MODE
TX
TX
RX
Step 2
TX
TX
TX
TX
RX
TX
RX
Step 3
TX
TX
DATA (LSB FIRST)
04h
(Reset)
(Presence)
CCh
F0h
8Dh
00h
84h
(Reset)
(Presence)
CCh
F5h
(—)
RX
(—)
<PIO pin status byte>
(—)
(—)
RX
<2 bytes CRC16>
(—)
(—)
TX
RX
(Reset)
(Presence)
DS2408
COMMENTS
Write byte to Control/Status Register
Reset pulse
Presence pulse
Issue Skip ROM command
Issue Read PIO Registers command
TA1, target address = 8Dh
TA2, target address = 008Dh
Read Control/Status Register and verify
Reset pulse
Presence pulse
Issue Skip ROM command
Issue Channel-access Read command
DS2408 samples PIO pin status
Read PIO pin status
Repeat the previous 2 steps until the master
has received a total of 32 bytes of PIO pin
status
Read CRC16
PIO pin status and CRC loop can be
continued as long as the application requires.
Reset pulse
Presence pulse
When using this communication example to read data from a remote microcontroller, as in Figure 17,
synchronization between the remote microcontroller and the master can be maintained by transmitting
data packets that begin with a length byte and end with a CRC16. See Application Note 114, section
"UNIVERSAL DATA PACKET" for details.
Example 3
Task: Detect the specific DS2408 where the button was pressed and identify the pin to which the
pushbutton is connected. This task is broken into the following steps:
1) Configure the conditional search and verify configuration setting.
2) Switch off all channel output transistors.
3) Clear the activity latches.
4) Search until a pushbutton is pressed.
5) Identify device and pushbutton; reset activity latches.
The device has to respond to the conditional search if the activity latch of at least one of the 8 channels is
set. This requires the following setup data for the conditional search registers:
Channel Selection Mask, select all channels Þ FFh
Channel Polarity Selection, select logic 1 for all channels Þ FFh
34 of 36
DS2408
Control/Status register,
Source is Activity Latch Þ PLS = 1
Term is OR Þ CT = 0
RSTZ = inactive (input) Þ ROS = 0
Clear Power-On Reset Latch Þ PORL = 0
The resulting setup data for the Control/Status Register is 01h.
For each DS2408 in the application, perform the following initialization:
MASTER MODE
Step 1
TX
RX
TX
TX
Step 2
Step 3
DATA (LSB FIRST)
(Reset)
(Presence)
55h
<8 byte ROM ID>
TX
CCh
TX
TX
TX
TX
TX
TX
RX
TX
TX
TX
TX
RX
TX
RX
TX
TX
TX
TX
8Bh
00h
FFh
FFh
01h
(Reset)
(Presence)
A5h
F0h
8Bh
00h
<FFh, FFh, 81h>
(Reset)
(Presence)
A5h
5Ah
FFh
00h
(—)
(—)
RX
RX
TX
RX
TX
TX
RX
TX
RX
AAh
FFh
(Reset)
(Presence)
A5h
C3
AAh
(Reset)
(Presence)
35 of 36
COMMENTS
Reset pulse
Presence pulse
Issue Match ROM command
Send ROM ID of the device to be accessed
Issue Write Conditional Search Register
command
TA1, target address = 8Bh
TA2, target address = 008Bh
Write Channel Selection Mask
Write Channel Polarity Selection
Write Control/Status Register
Reset pulse
Presence pulse
Issue Resume command
Issue Read PIO Registers command
TA1, target address = 8Bh
TA2, target address = 008Bh
Read Registers and verify
Reset pulse
Presence pulse
Issue Resume command
Issue Channel-access Write command
Write byte to PIO
Write inverted byte to PIO
DS2408 switches off all channel output
transistors if transmission was OK
Read for verification (AAh = success)
Read PIO pin status and verify; FFh = OK
Reset pulse
Presence pulse
Issue Resume command
Issue Reset Activity Latch command
Read for verification (AAh = success)
Reset pulse
Presence pulse
DS2408
After all DS2408s are initialized, perform the search process below as an endless loop:
MASTER MODE
Step 4
TX
RX
TX
Step 5
DATA (LSB FIRST)
(Reset)
(Presence)
ECh
RX
<2 bits>
TX
<1 bits>
RX
<2 bits>
TX
<1 bits>
(—)
(—)
TX
TX
TX
F0h
88h
00h
RX
<8 data bytes>
RX
<2 bytes CRC16>
TX
RX
TX
TX
RX
(Reset)
(Presence)
A5h
C3
AAh
(—)
(—)
COMMENTS
Reset pulse
Presence pulse
Issue Conditional Search ROM command
Read 2 bits; if both bits are 1, no push button
has been pressed; in this case return to Step
4. If the bit pattern is 01 or 10 or 00, a push
button has been pressed; in this case
continue with Step 5.
Identify and select the LS bit of the ROM ID
of the DS2408 that has responded to the
Conditional Search.
Read 2 bits; this relates to the next bit of the
ROM ID of the participating device(s).
Identify and select the next bit of the ROM ID
of the DS2408 that has responded to the
Conditional Search.
Repeat the previous 2 steps until one device
has been identified and accessed. (see Note
1)
Issue Read PIO Registers command
TA1, target address = 88h
TA2, target address = 0000h
Read register page; the data in the Activity
Latch State Register tells which button has
been pressed.
Read CRC16 and verify correct data
transmission.
Reset pulse
Presence pulse
Issue Resume command
Issue Reset Activity Latch command
Read for verification (AAh = success)
Now, as the device and push button are
identified and the Activity Latch is cleared,
continue at Step 4.
Note 1: For a full description of the Search Algorithm see Application Note 187.
36 of 36