Data Sheet No. PD60174-D IR2184(4)(S) HALF-BRIDGE DRIVER Features • Floating channel designed for bootstrap operation • • • • • • • Packages Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 10 to 20V Undervoltage lockout for both channels 3.3V and 5V input logic compatible Matched propagation delay for both channels Logic and power ground +/- 5V offset. Lower di/dt gate driver for better noise immunity Output source/sink current capability 1.4A/1.8A 14-Lead PDIP IR21844 8-Lead SOIC IR2184S 8-Lead PDIP IR2184 14-Lead SOIC IR21844S Description The IR2184(4)(S) are high voltage, high speed power MOSFET and IGBT IR2181/IR2183/IR2184 Feature Comparison drivers with dependent high and low Crossconduction Input side referenced output channels. ProDead-Time Ground Pins Ton/Toff Part prevention logic prietary HVIC and latch immune logic CMOS technologies enable rugge2181 COM HIN/LIN no none 180/220 ns 21814 VSS/COM dized monolithic construction. The 2183 Internal 500ns COM HIN/LIN yes 180/220 ns logic input is compatible with standard 21834 Program 0.4 ~ 5 us VSS/COM CMOS or LSTTL output, down to 3.3V 2184 Internal 500ns COM IN/SD yes 680/270 ns 21844 Program 0.4 ~ 5 us VSS/COM logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Typical Connection up to 600V V CC V CC VB IN IN HO SD SD VS COM LO TO LOAD up to 600V IR2184 HO V CC VB IN IN VS SD SD V CC (Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com IR21844 TO LOAD DT V SS RDT V SS COM LO 1 IR2184(4) (S) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition VB High side floating absolute voltage VS Min. Max. -0.3 625 Units High side floating supply offset voltage VB - 25 VB + 0.3 VHO High side floating output voltage VS - 0.3 VB + 0.3 VCC Low side and logic fixed supply voltage -0.3 25 VLO Low side output voltage -0.3 VCC + 0.3 DT Programmable dead-time pin voltage (IR21844 only) VSS - 0.3 VCC + 0.3 VIN Logic input voltage (IN & SD) VSS - 0.3 VSS + 10 VSS Logic ground (IR21844 only) VCC - 25 VCC + 0.3 — 50 dVS/dt PD RthJA Allowable offset supply voltage transient Package power dissipation @ TA ≤ +25°C Thermal resistance, junction to ambient (8-lead PDIP) — 1.0 (8-lead SOIC) — 0.625 (14-lead PDIP) — 1.6 (14-lead SOIC) — 1.0 (8-lead PDIP) — 125 (8-lead SOIC) — 200 (14-lead PDIP) — 75 (14-lead SOIC) — 120 TJ Junction temperature — 150 TS Storage temperature -50 150 TL Lead temperature (soldering, 10 seconds) — 300 V V/ns W °C/W °C Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset rating are tested with all supplies biased at 15V differential. Symbol Definition VB High side floating supply absolute voltage VS High side floating supply offset voltage Min. Max. VS + 10 VS + 20 Note 1 600 VHO High side floating output voltage VS VB VCC Low side and logic fixed supply voltage 10 20 VLO Low side output voltage 0 VCC VIN Logic input voltage (IN & SD) VSS VSS + 5 DT Programmable dead-time pin voltage (IR21844 only) VSS VCC VSS Logic ground (IR21844 only) -5 5 Ambient temperature -40 125 TA Units V °C Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -V BS. (Please refer to the Design Tip DT97-3 for more details). Note 2: IN and SD are internally clamped with a 5.2V zener diode. 2 www.irf.com IR2184(4) (S) Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 15V, VSS = COM, CL = 1000 pF, TA = 25°C, DT = VSS unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions ton Turn-on propagation delay — 680 900 VS = 0V toff Turn-off propagation delay — 270 400 VS = 0V or 600V tsd MTon Shut-down propagation delay Delay matching, HS & LS turn-on — 180 270 — 0 90 MToff Delay matching, HS & LS turn-off — 0 40 nsec tr Turn-on rise time — 40 60 VS = 0V tf Turn-off fall time — 20 35 VS = 0V Deadtime: LO turn-off to HO turn-on(DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) 280 4 400 5 520 6 Deadtime matching = DTLO - HO - DTHO-LO — 0 50 — 0 600 DT MDT µsec nsec RDT= 0 RDT = 200k RDT=0 RDT = 200k Static Electrical Characteristics VBIAS (VCC , VBS ) = 15V, VSS = COM, DT= V SS and TA = 25°C unless otherwise specified. The VIL, VIH and IIN parameters are referenced to VSS /COM and are applicable to the respective input leads: IN and SD. The VO, IO and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol Definition Min. Typ. Max. Units Test Conditions VIH Logic “1” input voltage for HO & logic “0” for LO 2.7 — — VCC = 10V to 20V VIL Logic “0” input voltage for HO & logic “1” for LO — — 0.8 VCC = 10V to 20V — — VSD,TH+ SD input positive going threshold VSD,TH- VCC = 10V to 20V SD input negative going threshold 2.7 — — 0.8 VOH High level output voltage, VBIAS - VO — — 1.2 IO = 0A VOL Low level output voltage, VO — — 0.1 IO = 0A ILK Offset supply leakage current — — 50 IQBS Quiescent VBS supply current 20 60 150 IQCC Quiescent VCC supply current 0.4 1.0 1.6 IIN+ Logic “1” input bias current — 5 20 IIN- Logic “0” input bias current VCC and VBS supply undervoltage positive going threshold VCC and VBS dupply undervoltage negative going threshold Hysteresis — 8.0 1 8.9 2 9.8 7.4 8.2 9.0 0.3 0.7 — IO+ Output high short circuit pulsed vurrent 1.4 1.9 — IO- Output low short circuit pulsed current 1.8 2.3 — VCCUV+ VBSUV+ VCCUVVBSUVVCCUVH V µA mA µA VCC = 10V to 20V VB = VS = 600V VIN = 0V or 5V VIN = 0V or 5V IN = 5V, SD = 0V IN = 0V, SD = 5V V VBSUVH www.irf.com A VO = 0V, PW ≤ 10 µs VO = 15V, PW ≤ 10 µs 3 IR2184(4) (S) Functional Block Diagrams VB 2184 UV DETECT HO R VSS/COM LEVEL SHIFT IN HV LEVEL SHIFTER R PULSE FILTER Q S VS PULSE GENERATOR VCC DEADTIME UV DETECT +5V VSS/COM LEVEL SHIFT SD LO DELAY COM VB 21844 UV DETECT HO R VSS/COM LEVEL SHIFT IN HV LEVEL SHIFTER Q S VS PULSE GENERATOR VCC DEADTIME DT UV DETECT +5V SD R PULSE FILTER VSS/COM LEVEL SHIFT LO DELAY COM VSS 4 www.irf.com IR2184(4) (S) Lead Definitions Symbol Description IN Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM for IR2184 and VSS for IR21844) Logic input for shutdown (referenced to COM for IR2184 and VSS for IR21844) SD DT Programmable dead-time lead, referenced to VSS. (IR21844 only) VSS Logic Ground (21844 only) VB High side floating supply HO High side gate drive output VS High side floating supply return VCC Low side and logic fixed supply LO Low side gate drive output COM Low side return Lead Assignments IN VB 2 SD HO 7 3 COM VS 6 4 LO VCC 5 1 1 www.irf.com 8 IN VB 8 2 SD HO 7 3 COM VS 6 4 LO VCC 5 1 8-Lead PDIP 8-Lead SOIC IR2184 IR2184S 14 IN 1 14 IN SD VB 13 2 SD VB 3 VSS HO 12 3 VSS HO 12 4 DT VS 11 4 DT VS 11 5 COM 10 5 COM 10 6 LO 9 6 LO 9 7 VCC 8 7 VCC 8 13 2 14-Lead PDIP 14-Lead SOIC IR21844 IR21844S 5 IR2184(4) (S) 01-6014 01-3003 01 (MS-001AB) 8-Lead PDIP D DIM B 5 A F OOT PRINT 6 8 7 6 5 H E 0.25 [.010] 1 2 3 A 4 6.46 [.255] MIN .0532 .0688 1.35 1.75 A1 .0040 3X 1.27 [.050] 8X 1.78 [.070] e1 MAX .0098 0.10 0.25 b .013 .020 0.33 0.51 c .0075 .0098 0.19 0.25 D .189 .1968 4.80 5.00 E .1497 .1574 3.80 4.00 e .050 BAS IC 1.27 BAS IC .025 BAS IC 0.635 BAS IC e1 6X e MILLIMETERS MAX A 8X 0.72 [.028] INCHES MIN H .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.27 y 0° 8° 0° 8° K x 45° A C y 0.10 [.004] 8X b 0.25 [.010] A1 8X L C A B NOT ES: 1. DIMENS IONING & T OLERANCING PE R ASME Y14.5M-1994. 2. CONT ROLLING DIMENSION: MILLIMET ER 3. DIMENS IONS ARE SHOWN IN MILLIME TE RS [INCHES]. 4. OUT LINE CONF ORMS T O JEDEC OUTLINE MS-012AA. 8-Lead SOIC 6 8X c 7 5 DIMENSION DOES NOT INCLUDE MOLD PROT RUS IONS. MOLD PROTRUSIONS NOT T O E XCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROT RUS IONS. MOLD PROTRUSIONS NOT T O E XCEED 0.25 [.010]. 7 DIMENSION IS T HE LE NGTH OF LEAD FOR SOLDE RING TO A SUBS TRAT E. 01-6027 01-0021 11 (MS-012AA) www.irf.com IR2184(4) (S) 14-Lead PDIP 14-Lead SOIC (narrow body) www.irf.com 01-6010 01-3002 03 (MS-001AC) 01-6019 01-3063 00 (MS-012AB) 7 IR2184(4) (S) IN(LO) IN 50% 50% SD IN(HO) ton toff tr 90% HO LO HO LO Figure 1. Input/Output Timing Diagram tf 90% 10% 10% Figure 2. Switching Time Waveform Definitions SD 50% 50% 50% IN tsd HO LO 90% 90% HO Figure 3. Shutdown Waveform Definitions LO DT LO-HO 10% DT HO-LO 90% 10% IN (LO) MDT= 50% 50% DT LO-HO - DT HO-LO IN (HO) Figure 4. Deadtime Waveform Definitions LO HO 10% MT MT 90% LO HO Figure 5. Delay Matching Waveform Definitions IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 7/24/2001 8 www.irf.com