SONY CXD1910AQ

CXD1910AQ
Digital Video Encoder
Description
The CXD1910AQ is a digital video encoder
designed for set top box, digital VCRs and other
digital video applications. The device accepts ITUR601 compatible Y, Cb, Cr data, and the data are
encoded to analog composite video and Y/C video
(S-Video) signal.
Features
• NTSC and PAL encoding mode
• Composite video and separate Y/C video (SVideo) outputs
• Y, U, and V outputs
• 8/16-bit pixel data input mode
• 13.5 Mpps pixel rate
• 10-bit 3 channels DACs
• Supports I2C bus (400kHz) and SONY SIO
• Closed Caption (Line 21, Line 284) encoding
• Macrovision Pay-Per-View copy protection system∗
Rev. 6.1
• Monolithic CMOS single 5.0V power supply
• 64-pin plastic QFP package
∗ This device is protected by U.S. patent numbers
4631603, 4577216 and 4819098 and other
intellectual property rights. Use of the Macrovision
anticopy process in the device is licensed by
Macrovision for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
64 pin QFP (Plastic)
Absolute Maximum Ratings
–0.3 to +7.0
• Supply voltage
VDD
• Input voltage
VI
–0.3 to +7.0
• Output voltage
VO
–0.3 to +7.0
• Operating temperature Topr
–20 to +75
• Storage temperature Tstg
–40 to +125
(Vss = 0V)
Recommended Operating Conditions
• Supply voltage
VDD
4.75 to 5.25
V
V
V
°C
°C
• Input voltage
VIN
• Operating temperature Topr
Vss to VDD
0 to +70
V
V
°C
I/O Capacitance
• Input pin
• Output pin
11 (Max.)
11 (Max.)
pF
pF
CI
CO
Note) Test conditions: VDD = VI = 0V
fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95235A66-ST
1 to 4,
6 to 9
–2–
XIICEN 64
XCS/SA 50
SCK/SCL 49
SI/SDA 48
F1 52
XVRST 51
FID 62
SIO and I2C-Bus
controller
CSYNC
SYNC gen.
and
timing controller
HSYNC 60
V
U
Y
BURST FLAG
1/2
Dempx,
level
translator
and
interpolator
4:2:2 to
4:4:4
VSYNC 59
SYSCLK 56
PDCLK 57
PD8 to 15 11 to 18
PD0 to 7
XRST 55
Block Diagram
MACRO VISION
signal gen.
Closed caption encoder
(for NTSC)
Sub carrier
gen.
LPF
LPF
Delay
Modulator
SYNC slope
gen.
CHROMA
Y, C/
Y, U, V
selector and
interpolator
10bit
DAC
10bit
DAC
10bit
DAC
37 to 39,
54
XTEST1 to 4
41 TRST
45 TCK
44 TMS
43 TDI
46 TDO
21 VREF
20 IREF
26 VG
32 C-OUT/U
24 COMP-O/V
29 Y-OUT/Y
25 VB
CXD1910AQ
CXD1910AQ
Pin Description
Pin
No.
Symbol
I/O
Description
1
PD7
I
2
PD6
I
3
PD5
I
4
PD4
I
5
VSS
—
6
PD3
I
7
PD2
I
8
PD1
I
9
PD0
I
10
VDD
—
11
PD15/TD7
I/O
12
PD14/TD6
I/O
13
PD13/TD5
I/O
14
PD12/TD4
I/O
15
PD11/TD3
I/O
16
PD10/TD2
I/O
17
PD9/TD1
I/O
18
PD8/TD0
I/O
19
VSS
—
Digital ground
20
IREF
O
The reference current output pin.
Connect resistance “16R” which is 16 times output resistance “R”.
21
VREF
I
The voltage reference input pin.
Sets output full scale value.
22
AVDD1
—
Analog power supply
23
AVSS1
—
Analog ground
8-bit pixel data input pins (PD0 to 7).
When control register bit “PIF MODE” = “0”:
These are inputs for multiplexed Y, Cb, and Cr signal.
When control register bit “PIF MODE” = “1”:
These are inputs for Y signal.
Digital ground
8-bit pixel data input pins (PD0 to 7).
When control register bit “PIF MODE” = “0”:
These are inputs for multiplexed Y, Cb, and Cr signal.
When control register bit “PIF MODE” = “1”
These are inputs for Y signal.
Digital power supply
8-bit pixel data input pins / Test data bus.
When control register bit “PIF MODE” = “0”:
These inputs are not used.
When control register bit “PIF MODE” = “1”:
These are inputs for multiplexed Cb and Cr signal.
When test mode, it's used for internal circuit test data bus.
Test mode is available only for device bender.
24
COMP-O/V
O
This is the output of 10-bit D/A converter.
When control register bit “YC/YUV” = “1”:
This pin outputs composite signal.
When control register bit “YC/YUV” = “0”:
This pin outputs color difference (V) signal.
25
VB
O
Connect to VSS with a capacitor of approximately 0.1µF.
26
VG
I
Connect to AVDD with a capacitor of approximately 0.1µF.
27
AVDD2
—
Analog power supply
28
AVSS2
—
Analog ground
29
Y-OUT/Y
O
This is the output of 10-bit D/A converter.
This pin outputs luminance (Y) signal.
–3–
CXD1910AQ
Pin
No.
Symbol
I/O
Description
30
AVDD3
—
Analog power supply
31
AVSS3
—
Analog ground
O
This is the output of 10-bit D/A converter.
When control register bit “YC/YUV” = “1”:
This pin outputs chroma (C) signal.
When control register bit “YC/YUV” = “0”:
This pin outputs color difference (U) signal.
32
C-OUT/U
33
TD10
I/O
Test data bus.
This pin should be open.
When test mode, it’s used for internal circuit test data bus.
Test mode is available only for device bender.
34
VDD
—
Digital power supply
35
TD9
I/O
36
TD8
I/O
Test data bus.
These pins should be open.
When test mode, it’s used for internal circuit test data bus.
Test mode is available only for device bender.
37
XTEST1
I
38
XTEST2
I
39
XTEST3
I
40
VSS
41
TRST
42
VDD
—
43
TDI
I
Test mode control input pins. This pin is pulled up.
44
TMS
I
Test mode control input pins. This pin is pulled up.
45
TCK
I
Test mode control input pins. This pin should be “H” input.
46
TDO
O
Test data bus. This pin should be open.
47
VSS
—
Digital ground
48
SI/SDA
49
50
51
SCK/SCL
XCS/SA
XVRST
—
I
Test mode control input pins. These pins are pulled up.
When these pins are “H”, the CXD1910AQ is not test mode.
Test mode is available only for device bender.
Digital ground
Test mode reset input pins.
When power on reset, set “L” for more than 40 clocks (SYSCLK).
Digital power supply
I
This pin's function is selected by XIICEN (Pin 64).
When XIICEN = “H”, this pin is SONY SIO mode; SI serial data input.
When XIICEN = “L”, this pin is I2C-BUS mode; SDA input/output.
I
This pin's function is selected by XIICEN (Pin 64).
When XIICEN = “H”, this pin is SONY SIO mode; SCK serial clock input.
When XIICEN = “L”, this pin is I2C-BUS mode; SCL input.
I
This pin's function is selected by XIICEN (Pin 64).
When XIICEN = “H”, this pin is SONY SIO mode; XCS chip select input.
When XIICEN = “L”, this pin is I2C-BUS mode; SA slave address select input
signal which selects I2C-BUS slave address.
I
Vertical sync reset input pin in active low. This pin is pulled up.
This is used to synchronize external vertical sync and internal vertical sync.
When XVRST is “L”, internal digital sync generator is reset according to F1 status.
–4–
CXD1910AQ
Pin
No.
Symbol
I/O
Function
Field ID input.
For external synchronization with XVRST signal, the field for resetting is determined
by the main signal.
“H” indicates 1st field.
“L” indicates 2nd field.
52
F1
I
53
VDD
—
54
XTEST4
I
Test mode control input pin. This pin is pulled up.
When this pin is “H”, the CXD1910AQ is not test mode.
Test mode is available only for device bender.
55
XRST
I
System reset input pin in active low.
When power on reset, set “L” for more than 40 clocks (SYSCLK).
56
SYSCLK
I
System clock input pin.
To generate correct subcarrier frequency, precise 27MHz is required.
57
PDCLK
O
Pixel data clock output pin for 13.5MHz.
This clock is divided from SYSCLK.
This is used when 16-bit pixel data mode.
58
VSS
—
Digital ground
59
VSYNC
O
Vertical sync signal output pin.
60
HSYNC
O
Horizontal sync signal output pin.
61
SO
O
This pin's function is selected by XIICEN (Pin 64).
When XIICEN = “H”, this pin is SONY SIO mode; SO serial out output pin.
When XIICEN = “L”, this pin is not used and output is high impedance.
Digital power supply
62
FID
O
Field ID output pin.
When control register bit “FIDS” = “1”:
“L” indicates 1st field, “H” indicates 2nd field.
When control register bit “FIDS” = “0”:
“H” indicates 1st field, “L” indicates 2nd field.
63
VDD
—
Digital power supply
64
XIICEN
I
Serial interface mode select input pin. This pin is pulled up.
When XIICEN = “L”, Pins 48 to 50 and 61 are I2C-BUS mode.
When XIICEN = “H”, Pins 48 to 50 and 61 are SONY SIO mode.
–5–
CXD1910AQ
Electrical Characteristics
DC characteristics
Item
(Ta = 0 to +70°C, Vss = 0V)
Symbol
Conditions
Min.
2.2
Input high voltage
VIH
VDD = 5.0V ± 5%
Input low voltage
VIL
VDD = 5.0V ± 5%
Output high voltage
VOH1
IOH = –2.4mA
VDD =4.75 to 5.25V
Output low voltage
VOL1
IOL = 4.8mA
VDD = 4.75 to 5.25V
Output high voltage
VOH2
IOH = –1.2mA
VDD = 4.75 to 5.25V
Output low voltage
VOL2
IOL = 2.4mA
VDD = 4.75 to 5.25V
Input leak current
II1
VI = 0 to 5.25V
VDD = 4.75 to 5.25V
–10
Input leak current
II2
VI = 0V
VDD = 5.0V ± 5%
–40
Supply current
IDD
VDD = 5.0V ± 5%
Typ.
Max.
Unit
Pins
V
∗1
V
∗1
V
∗2
V
∗2
V
∗3
0.4
V
∗3
10
µA
∗4
–240
µA
∗5
70∗6
mA
0.8
VDD–0.8
0.4
VDD–0.8
–100
∗1 PD0 to 15, TD8 to 10, XTEST1 to 4, TRST, TDI, TCK, SI/SDA, SCK/SCL, XCS/SA, XVRST, F1, XRST,
SYSCLK, XIICEN
∗2 PDCLK, VSYNC, HSYNC, FID, SO
∗3 TDO, TD0 to 10
∗4 PD0 to 15, TD8 to 10, TCK, SI/SDA, SCK/SCL, F1, XRST, SYSCLK
∗5 XTEST1 to 4, TRST, TDI, TMS, XCS/SA, XVRST, XIICEN
∗6 Not include analog supply current
DAC characteristics 1
Item
(AVDD = 5V, R = 200Ω, VREF = 1.35V, Ta = 25°C)
Symbol
Measurement conditions
Min.
Typ.
Max.
10
Unit
Resolution
n
Linearity error
EL
–2.5
2.5
LSB
Differential linearity error
ED
–1.5
1.5
LSB
Output full-scale current
IFS
6.25
7.25
mA
Output offset voltage
VOS
1
mV
Output full-scale voltage
VFS
1.25
1.35
1.45
V
Precision guaranteed output
voltage range
VOC
1.25
1.35
1.45
V
–6–
6.75
bit
CXD1910AQ
(AVDD = 5V, R = 200Ω, VREF = 2.0V, Ta = 25°C)
DAC characteristics 2
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
10
Unit
Resolution
n
bit
Linearity error
EL
–2.0
2.0
LSB
Differential linearity error
ED
–1.0
1.0
LSB
Output full-scale current
IFS
9.5
10.5
mA
Output offset voltage
VOS
1
mV
Output full-scale voltage
VFS
1.9
2.0
2.1
V
Precision guaranteed output
voltage range
VOC
1.9
2.0
2.1
V
10.0
AC characteristics
1. Pixel Data Interface
(1) 8-bit mode
SYSCLK
tPDS
tPDH
PD0 to 7
(Ta = 0 to +70°C, VDD = 4.25 to 5.25V, Vss = 0V)
Item
Pixel data setup time to SYSCLK
Pixel data hold time to SYSCLK
Symbol
Min.
Typ.
Max.
Unit
tPDS
tPDH
10
ns
3
ns
tPDS
tPDH
(2) 16-bit mode
PDCLK
PD0 to 15
(Ta = 0 to +70°C, VDD = 4.75 to 5.25V, Vss = 0V)
Item
Pixel data setup time to PDCLK
Pixel data hold time to PDCLK
Symbol
tPDS
tPDH
–7–
Min.
Typ.
Max.
Unit
20
ns
0
ns
CXD1910AQ
2. Serial Port Interface
fSCK
tPWLSCK
tPWHSCK
SCK
tCSS
tCSH
XCS
tSIS
tSIH
SI
tSOH
tSOD
SO
(Ta = 0 to +70°C, VDD = 4.75 to 5.25V, Vss = 0V)
Item
Symbol
Min.
Typ.
Max.
Unit
3
MHz
SCK clock rate
fSCK
DC
SCK pulse width Low
tPWLSCK
tPWHSCK
tCSS
tCSH
tSIS
tSIH
tSOD
tSOH
100
ns
100
ns
150
ns
150
ns
50
ns
10
ns
tVS
tVH
SCK pulse width High
Chip select setup time to SCK
Chip select hold time to SCK
Serial input setup time to SCK
Serial input hold time to SCK
Serial output delay time from SCK
Serial output hold time from SCK
30
3
ns
ns
3. XVRST, F1
PDCLK
XVRST
F1
(Ta = 0 to +70°C, VDD = 4.75 to 5.25V, Vss = 0V)
Item
XVRST, F1 setup time to PDCLK
XVRST, F1 hold time to PDCLK
Symbol
tVS
tVH
–8–
Min.
Typ.
Max.
Unit
20
ns
0
ns
CXD1910AQ
4. SYSCLK, PDCLK, VSYNC, HSYNC, FID
fSYSCLK
tPWHCLK
tPWLCLK
SYSCLK
tPDCLKD
tPDCLKD
PDCLK
tOD
tOH
VSYNC,
HSYNC,
FID
(Ta = 0 to +70°C, VDD = 4.75 to 5.25V, Vss = 0V)
Item
Symbol
fSYSCLK
SYSCLK pulse width Low
tPWLCLK
tPWHCLK
tPDCLKD
tCOD
tCOH
PDCLK delay time from SYSCLK
Control output delay time from SYSCLK
Control output hold time from SYSCLK
Typ.
Max.
27
SYSCLK clock rate
SYSCLK pulse width High
Min.
–9–
Unit
MHz
11
ns
11
ns
3
20
ns
25
ns
ns
CXD1910AQ
Description of Functions
The CXD1910AQ converts digital parallel data (ITU-R601 Y, Cb, Cr) into analog TV signals in NTSC (RS170A)
or PAL (ITU-R624; B, G, H, I) format.
The CXD1910AQ first receives image data in 8-bit parallel form (multiplexed Y, Cb, and Cr data), or in 16-bit
parallel form (8-bit Y and 8-bit multiplexed Cb and Cr data). After demultiplexing, it converts Cb and Cr signals
into U and V signals respectively, interpolates 4:2:2 to 4:4:4, and modulates the signals with the subcarrier
generated by digital subcarrier generator.
Y signal and modulated chroma signal are oversampled (at double) to reduce sin (x)/(x) rolloff.
10-bit DACs are used for converting digital composite and Y/C signals into analog signals.
1. Pixel Input Format
Pixel input format is determined by bit 4 (PIF MODE) of control register address 01H, as shown in Table 1-1.
When PIF MODE is “0”, the image data (Y, Cb, Cr) input from PD0 to PD7 is sampled at the rising edge of
SYSCLK.
When PIF MODE is “1”, Y data is input into PD0 to 7, multiplexed Cb and Cr data are input into PD8 to 15, and
these respective data are sampled at the rising edge of PDCLK.
PIF MODE
PD15 to 8
PD7 to 0
0 (8-bit mode)
NA
Y/Cb/Cr
1 (16-bit mode)
Cb/Cr
Y
Table 1-1
Pixel Data Input Timing
SYSCLK
PDCLK
HSYNC
[16-bit mode]
PD0 to 7
Y0
Y1
Y2
Y3
Y4
Y5
PD8 to 5
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
[8-bit mode]
Cb0
PD0 to 7
PD0
PD1
:
PD7
Pixel data 0 (LSB)
Pixel data 1
:
Pixel data 7 (MSB)
Y0
Cr0
PD8
PD9
:
PD15
Y1
Cb2
Y2
Cr2
Pixel data 0 (LSB)
Pixel data 1
:
Pixel data 7 (MSB)
– 10 –
Y3
Cb4
Y4
Cr4
Y5
Cb6
CXD1910AQ
2. Serial Interface
The CXD1910AQ supports both I2C-BUS (high-speed mode) and SONY's serial interface. These modes can
be selected by XIICEN input pin as shown in Table 2-1 below.
XIICEN
H
L
I2C
SONY SIO mode
SI/SDA
mode
SI
SDA
SCK/SCL
SCK
SCL
XCS/SA
XCS
SA
SO
High-Z
SO
Table 2-1
2-1. I2C-BUS interface
The CXD1910AQ becomes a slave transceiver of I2C-BUS, and supports the 7-bit slave address and the highspeed mode (400K bit/s).
2-1-1. Slave address
Two kinds of slave address (88H, 8CH) are selectable by the SA signal, as shown in Table 2-2 below.
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
0
1
SA
0
X
Table 2-2
2-1-2. Write cycle
AAAAAA
AA
AAAAAAAAAAAAAAAAA
AAAAAA
AAAAAA
AA
AAAA
AAAA
AAAA
AA
AA
AA
AA
S
slave address
W
A
start address
A
write data
A
write data
A
P
"0"
from master to slave
from slave to master
D7
D6
D5
D4
start address
D3
D2
D1
D0
ADR [4 : 0]
After the slave address is supplied from the master, the data in the next transfer cycle is set up inside the start
address register of this IC as start address of the control register. In subsequent cycles, the data supplied from
the master is written in the addresses indicated by the control register address. The set control register
address is automatically incremented with the completed transfer of each byte of data.
– 11 –
CXD1910AQ
2-1-3. Read cycle
AAAAAA
AA
AAAA
AA
AAA
AA
AAA
AAA
AA
AAAAAA
AA
AA AAA
AA
AA
AA
S
slave address
R
A
read data
A
read data
A
P
"1"
from master to slave
from slave to master
After the slave address is supplied from the master, subsequent cycles change immediately to read cycles and
only ID code (address 09H, 0AH) is read out. During the read cycle, the start address is automatically set to
09H.
Note) In the SONY SIO mode, addresses from 00H to 0AH can be read out.
2-1-4. Handling of general call address (00H)
General call address is neglected and there is no ACK response.
– 12 –
CXD1910AQ
2-2. SONY serial interface
SONY serial interface uses SCK, XCS, SI and SO signals.
Serial interface is activated when XCS signal is “Low”, and samples serial input data at the rising edge of SCK.
The first one byte after XCS activation is set up as a serial control command. The data includes a start control
register address and direction of the serial interface. The control register address is automatically incremented
with the transfer of each byte of data. In the write mode, the data of second byte and after are written in the
addresses indicated by the address generated by the address generator of the CXD1910AQ. In the read
mode, the serial input data is neglected and writing is not done.
Serial Interface Timing
SCK
XCS
SI
D0
D1
LSB
D2
D3
D4
D5
Serial control command
D6
D7
D0
MSB
LSB
D0
SO
D1
D2
D3
D4
D5
D6
Serial data
D1
D2
D3
D4
D7
MSB
D5
D6
D7
Serial Interface Sequence
SCK
XCS
SI
00H
Internl address generator
FFH
11H
00H
01H
Start control register address set Control register address
auto-increment
Control register address
00H
01H
02H
CEH
02H
Control register address
auto-increment
Control register data
FFH
11H
CEH
2-1. Serial control command format
D7
D6
D5
D4
D3
WR
WR
D2
D1
D0
ADR [4 : 0]
: Direction for serial interface
When this bit is “1”:
The serial interface is write mode.
Incoming serial data is set up inside the control register according to the control register
address.
When this bit is “0”:
The serial interface is read mode.
The control register data is output to SO according to the control register address.
ADR [4 : 0] : Start control register address
– 13 –
CXD1910AQ
3. XVRST, F1
XVRST and F1 signals are used to synchronize with external V. sync.
XVRST and F1 signals are sampled at the rising edge of PDCLK, and F1 signal is sampled when XVRST is
Low. When F1 is High, the internal sync generator is reset to the 1st field, and when F1 is Low, it is reset to the
2nd field. When XVRST is set at High, digital sync generator starts operation, and the sequence of 1st or 2nd
field starts.
XVRST Timing (1st Field)
PDCLK
XVRST
F1 "H"
Start of 1st field (NTSC : 4H)
(PAL : 1H)
VSYNC
F-ID
HSYNC
XVRST Timing (2nd Field)
PDCLK
XVRST
F1 "L"
Start of 2nd field (NTSC : 266H)
(PAL : 313H)
VSYNC
F-ID
1/2H
HSYNC
– 14 –
CXD1910AQ
4. Closed Caption
The CXD1910AQ supports closed caption encoding.
ASCII data for closed caption encodes line 21 and line 284 by adding parity bit to ASCII data (data #1 and data
#2 for line 21, data #1 and data #2 for line 284) which is set up for control registers 03H, 04H, 05H and 06H.
Control registers 03H to 06H are double-buffered and ASCII data which is set up by serial interface is
synchronized with VSYNC.
Double Buffer for Closed Caption
SI/SDA
VSYNC
03H
Load
ASCII data #1
Closed Caption Data Renewal Timing
VSYNC
Set control register 03H
SI/SDA
NEW DATA
Data#1
OLD DATA
NEW DATA
Closed Caption Signal Waveform
HSYNC
Color
burst
Clock run-in
Start
bits
ASCII data#1
ASCII data#2
S1 S2 S3 b0 b1 b2 b3 b4 b5 b6 P1 b0 b1 b2 b3 b4 b5 b6 P2
50 IRE
– 15 –
– 16 –
FID
VSYNC
HSYNC
FID
VSYNC
HSYNC
NTSC Vertical Interval
261
524
262
525
263
2
264
265
Fields 2 and 4
1
3H
Preequalization
3
Fields 1and 3
266
4
267
5
268
Vertical SYNC
3H
6
Vertical blanking
269
7
270
8
271
Postequalization
3H
9
272
10
273
11
274
19
282
20
283
21
284
22
285
23
CXD1910AQ
– 17 –
FID
VSYNC
HSYNC
FID
VSYNC
HSYNC
620
PAL Vertical Interval
308
621
309
622
310
623
311
624
625
312
2.5H
313
2
314
315
Fields 2 and 4
1
2.5H
3
Fields 1and 3
316
4
317
2.5H
5
318
6
319
7
320
8
321
20
333
21
334
22
335
23
336
24
CXD1910AQ
CXD1910AQ
Vertical Synchronization Timing
0.148µs
2.3µs
29.5µs
0.148µs
4.67µs
27.1µs
1/2H
63.555µs
NTSC Equalizing & Synchronizing Pulses
0.296µs
0.296µs
2.37µs
29.63µs
4.67µs
27.3µs
1/2H
64µs
PAL Equalizing & Synchronizing Pulses
– 18 –
CXD1910AQ
Control Register Map
Note) For the bit which is not assigned, use it by setting “0”.
BIT
Function Selection #1
Address
00H
7
6
5
4
3
2
FIDS
MASK
EN
PIX
EN
YC/YUV
BF
SET UP
ENC MODE
Encoding mode
0 : PAL encoding mode
1 : NTSC encoding mode (Default)
SET UP
Set up enable
0 : Non set up level, black = blanking level
1 : 7.5 IRE set up level insertion (Default)
BF
Burst flag enable
0 : Disable burst flag
1 : Enable burst flag (Default)
1
0
ENC
MODE
R/W
Color burst exists or not can be selected.
YC/YUV
DAC output function select
0 : Y, U, V output mode
1 : Video signal (Comp, Y, C) output mode (Default)
PIX EN
Pixel data enable
0 : Disable input pixel data
1 : Enable input pixel data (Default)
When input pixel data is disabled, output becomes blanking level or black level
regardless of input PD0 to PD15.
MASK EN
Mask enable
0 : When V-blanking, pixel data through
1 : When V-blanking, pixel data reject (Default)
When MASK EN = “0”, input pixel data during V-blanking interval are valid, and
output obeys input pixel data.
When MASK EN = “1”, input pixel data during V-blanking interval are all invalid,
and output becomes blanking level.
As for this mode, input pixel data under 16 (0 to 16) is limited to 16; input pixel
data more than 235 (235 to 255) is limited to 235.
FIDS
FID polarity select
0 : 1st field “H”, 2nd field “L”
1 : 1st field ”L“, 2nd field “H” (Default)
– 19 –
CXD1910AQ
BIT
Function Selection #2
7
Address
01H
6
5
4
3
2
1
0
PIF
MODE
DAC MODE
R/W
PIF MODE
Pixel input format
0 : 8-bit mode
Multiplexed Y, Cb, Cr (4:2:2) (Default)
1 : 16-bit mode Y and multiplexed Cb, Cr
DAC MODE
DAC output activity
0 0 : Non-active
0 1 : Y-OUT and C-OUT active
1 0 : Comp-out active
1 1 : Both active (Default)
BIT
Function Selection #3
7
6
5
Address
02H
4
3
2
ZERO
CC MODE
Closed caption encoding mode
0 0 : Disable closed caption encoding (Default)
0 1 : Enable encoding in 1st field (Line 21)
1 0 : Enable encoding in 2nd field (Line 284)
1 1 : Enable encoding in both fields
ZERO
Use it by setting “0”.
– 20 –
1
0
CC MODE
R/W
CXD1910AQ
BIT
Closed Caption Character #1 for 21H
7
6
5
Address
03H
4
3
2
1
ASCII data#1
(Default: 0H)
4
2
0
R/W
Closed Caption Character #2 for 21H
7
6
5
Address
04H
3
1
ASCII data#2
(Default: 0H)
4
2
0
R/W
Closed Caption Character #1 for 284H
7
6
5
Address
05H
3
1
ASCII data#1
(Default: 0H)
4
2
0
R/W
Closed Caption Character #2 for 284H
7
Address
06H
6
5
3
ASCII data#2
– 21 –
1
(Default: 0H)
0
R/W
CXD1910AQ
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Video Timing
806
806
WHITE LEVEL
748
655
597
506
100 IRE
448
7.5 IRE
355
297
BLACK LEVEL
BLANK LEVEL
256
40 IRE
SYNC LEVEL
36
NTSC Y (Luminance) Video Output Waveform
BLACK
BLUE (±227)
RED (±320)
MAGENTA (±299)
GREEN (±299)
CYAN (±320)
YELLOW (±227)
WHITE
7.5 IRE SETUP
832
622
20 IRE
BLANK LEVEL
512
402
COLOR BURST
192
NTSC C (Chroma) Video Output Waveform
7.5 IRE SETUP
– 22 –
CXD1910AQ
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Video Timing
806
806
WHITE LEVEL
744
643
580
100 IRE
482
419
318
BLANK LEVEL
256
40 IRE
SYNC LEVEL
36
BLACK
BLUE (±245)
RED (±347)
MAGENTA (±324)
GREEN (±324)
CYAN (±347)
YELLOW (±245)
WHITE
NTSC Y (Luminance) Video Output Waveform
No SETUP
859
622
20 IRE
BLANK LEVEL
512
402
COLOR BURST
165
NTSC C (Chroma) Video Output Waveform
No SETUP
– 23 –
CXD1910AQ
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Video Timing
806
806
WHITE LEVEL
744
643
580
100 IRE
482
419
318
BLANK LEVEL
256
43 IRE
SYNC LEVEL
20
BLACK
BLUE (±245)
RED (±347)
MAGENTA (±324)
GREEN (±324)
CYAN (±347)
YELLOW (±245)
WHITE
PAL Y (Luminance) Video Output Waveform
859
630
21.5 IRE
BLANK LEVEL
512
394
COLOR BURST
165
PAL C (Chroma) Video Output Waveform
– 24 –
CXD1910AQ
BLACK
752
(240)
670
(158)
593
(81)
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Video Timing
512
431
(–81)
354
(–158)
272
(–240)
795
(283)
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Color Difference (U) Video Output Waveform
850
(338)
566
(54)
512
458
(–54)
229
174 (–283)
(–338)
Color Difference (V) Video Output Waveform
– 25 –
CXD1910AQ
Internal Filter Characteristics
Interpolation Filter Characteristic
0
Attenuation [dB]
–10
–20
–30
–40
–50
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Frequency [MHz]
Chrominance Filter Characteristics
0
Attenuation [dB]
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
Frequency [MHz]
– 26 –
7
8
9
10
CXD1910AQ
Application Circuit 1
CXD1910AQ
AVDD
VG
0.1µF
VREF
(1.33V)
1kΩ
3.3kΩ
IREF
AVSS
Buff AMP
0.1µF
Video output
LPF
COMP-O
Y-OUT
C-OUT
75Ω
[6dB]
200Ω
VB
VSS
Application Circuit 2
CXD1900Q
(MPEG2 decoder)
CXD1910AQ
(Video encoder)
8
PD0 to 7
PD0 to 7
FLDID
F-ID
HSYNC
HSYNC
VRST
XVRST
F1
F1
SYSCLK
PXCLK
27MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 27 –
CXD1910AQ
Package Outline
Unit: mm
64PIN QFP(PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
51
0.15
64
20
1
16.3
32
+ 0.4
14.0 – 0.1
52
17.9 ± 0.4
33
+ 0.2
0.1 – 0.05
1.0
0.8 ± 0.2
19
+ 0.35
2.75 – 0.15
+ 0.15
0.4 – 0.1
± 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP–64P–L01
LEAD TREATMENT
EIAJ CODE
∗ QFP064–P–1420
LEAD MATERIAL
SOLDER/PALLADIUM
PLATING
COPPER /42 ALLOY
PACKAGE WEIGHT
1.5g
JEDEC CODE
– 28 –