AKM AK8813VG

ASAHIKASEI
[AK8813/14]
AK8813/14
NTSC/PAL Digital Video Encoder
GENERAL DESCRIPTION
The AK8813/14 is low voltage, low power and small packaged Digital Video Encoder. It is suitable
for a STB or Digital TV. It converts ITU-R.BT601/656 standard 8- bit parallel data into analog
composite video signal, S-video in NTSC and PAL formats.
AK8813/14 supports Copy protection, Closed Captioning and Video Blanking ID(CGMS-A) and WSS.
These functions are controlled by high-speed I2C Bus interface.
FEATURES
• NTSC-M, PAL-B,D,G,H,I,M,N encoding.
• Simultaneous composite video signal and S-video signal outputs
• ITU-R BT.656 4:2:2 8-bit Parallel Input
- EAV Decoding
• Master/Slave Operation
- Digital Field Sync I/O
- Digital Vertical/Horizontal Sync I/O
• Y filtering
2 x over-sampling
• C filtering
4 x over-sampling
• Single 27MHz Clock (The polarity could be inverted by SYSINV pin)
• Triple 10-bit DACs
• I2C Bus Interface (400kHz)
• Closed Caption encoding (NTSC: line 21,284-SMPTE PAL: line 22,335-CCIR)
• Macrovision Copy Protection Rev. 7.1 * (only AK8814 )
• VBID, CGMS-A(EIAJ CPR-1024)
• WSS
• On-chip color bar generator
• Low power consumption
• 2.8V to 3.3V operation CMOS Monolithic
• 48pin LQFP Package / 57pin FBGA Package
(*Note) This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other
intellectual rights. The use of Macrovision’s copy protection technology in the device must be authorized
by Macrovision and is intended for home and other limited pay-per -view use only, unless otherwise
authorized in written by Macrovision. Reverse engineering or disassembly is prohibited.
Rev.00
-1-
2004/Oct
ASAHIKASEI
[AK8813/14]
Block Diagram
SELA SCL SDA CLKNV CLK HSYNC VSYNC/PD /RESET
VREFOUT VREFIN
2
u-P I/F (I C)
&
Register
Timing Generator
Macrovision
CGMS-A
WSS
VREF
Generator
IREF
Sync-Form
Generator
Luma Filter
Input Formatter
EAV Decode
Data[7:0]
Y
Delay
(x 2 Interpolator)
4:2:2 to 4:4:4
(x 2 Interpolator)
Chroma
LPF Filter
(x 2 Interpolator)
Sub-Carrier
Generator
DVDD DVSS
Rev.00
C
Delay
10-bit
DAC
Y
10-bit
DAC
Composite
10-bit
DAC
C
AVDD AVSS
-3-
2004/Oct
ASAHIKASEI
[AK8813/14]
ORDERING GUIDE
AK8813VQ: LQFP48 Non-Macrovision (Pb Free)
AK8813VG: FBGA57 Non-Macrovision
AK8813VGP: FBGA57 Non-Macrovision (Pb Free)
AK8814VQ: LQFP48 Macrovision (Pb Free)
AK8814VG: FBGA57 Macrovision (Pb Free)
Rev.00
-4-
2004/Oct
ASAHIKASEI
[AK8813/14]
PIN LAYOUT
48pin LQFP
AVSS
AVDD
VREFOUT
VREFIN
IREF
DVSS
DVDD
UD0
UD1
UD2
UD3
UD4
UD5
37
36 35 34 33 32 31 30 29 28 27 26 25
24
CVBS
UD6
38
23
AVSS
UD7
39
22
C
DVSS
40
21
AVDD
SYSCLK
41
20
Y
DVDD
42
19
AVSS
UD8
43
18
/RESET
DVDD
44
17
PD
FID/VSYNC
45
16
SDA
HSYNC
46
15
SCL
DVSS
47
14
SELA
SYSINV
48
13
TEST
7
2
TEST
3
D0
D1
8
9 10 11 12
D2
9
8
D3
D4
6
DVSS
5
D5
2
DVDD
4
D6
UD9
3
D7
1
57pin FBGA
7
6
5
4
1
A
B
C
D
E
F
G
H
J
Bottom View
Rev.00
-5-
2004/Oct
ASAHIKASEI
[AK8813/14]
PIN/FUNCTION
48pin LQFP
No.
1
Pin Name
I/O
Description
UD9
I/O
Test pin. Open for normal operation
2-5,
8-11
D7 - D0
I
27MHz 8-Bit 4:2:2 multiplexed Y,Cb,Cr Data Input.
For Rec.656 format, AK8813/14 decodes EAV.
For non-Rec.656 format (without EAV), AK8813/14 operates in Master or
Slave mode.
12-13
TEST
I
Test pin. Ground for normal operation
14
SELA
I
The slave address is set with this pin.
“L”:40H “H”:42H
15
SCL
I
Serial interface clock
16
SDA
I/O
17
PD
I
18
/RESET
I
20
Y
O
Output of Luminance Signal.
22
C
O
Output of the Chrominance signal
24
COMPOSITE
O
Output of Composite Video signal
27
VREFOUT
O
Output of the Internal Vref. Terminate with 0.1uF or more capacitor.
28
VREFIN
I
Input of the Reference Voltage
29
IREF
O
The currents flow this pin adjusts the full-scale output current of the DAC.
Connect this pin to Analog ground via a 6.8kohm resistor ( better than +/1% accuracy ).
32-39
UD0-UD7
I/O
Test pin. Open for normal operation
41
SYSCLK
I
43
UD8
I/O
Serial interface data
Power Down Pin. After returning from PD mode to normal operation,
RESET Sequence should be done to AK8813/14.
After this pin becomes “L”, AK8813/14 starts the internal initializing
sequence.
After initializing sequence, AK8813/14 is set NTSC mode, Rec.656
decoding mode. All DACs Off condition.
After power up, AK8813/14 must be initialized with this pin.
(27MHz Clock is necessary for reset sequence.)
27MHz Clock Input. The polarity could be inverted by SYSINV.
Test pin. Open for normal operation
Either of FID or VSYNC selected by the register.
Rec.656 decode mode :Output
Master mode : Output
Slave mode : Input
FID shows that “L” is odd field and ”H” is even field.
Rec.656 decode mode : Output
Master mode : Output
Slave mode : Input
“L “ : data is latched with rising edge.
“H” : data is latched with falling edge.
45
FID
/VSYNC
I/O
46
HSYNC
I/O
48
SYSINV
I
21,26
AVDD
P
Analog Power Supply
6,31,
42,44
DVDD
P
Digital Power Supply
AVSS
G
Analog Ground
DVSS
G
Digital Ground
19,23,25
7,30,
40,47
Rev.00
-6-
2004/Oct
ASAHIKASEI
[AK8813/14]
57pin FBGA
No.
Pin Name
I/O
A1
NC
-
Open for normal operation
B1
AVSS
G
Analog Ground
C1
AVDD
P
Analog Power Supply
C2
VREFOUT
O
Output of the Internal Vref. Terminate with 0.1uF or more capacitor.
D1
VREFIN
I
Input of the Reference Voltage
D2
IREF
O
The currents flow this pin adjusts the full-scale output current of the DAC.
Connect this pin to Analog ground via a 6.8kohm resistor ( better than +/1% accuracy ).
E1
DVSS
G
Digital Ground
E2
DVDD
P
Digital Power Supply
F2
UD0
I/O
Test pin. Open for normal operation
F1
UD1
I/O
Test pin. Open for normal operation
G2
UD2
I/O
Test pin. Open for normal operation
G1
UD3
I/O
Test pin. Open for normal operation
H1
UD4
I/O
Test pin. Open for normal operation
J1
NC
-
J2
UD5
I/O
Test pin. Open for normal operation
H2
UD6
I/O
Test pin. Open for normal operation
H3
UD7
I/O
Test pin. Open for normal operation
J3
DVSS
G
Digital Ground
H4
SYSCLK
I
27MHz Clock Input. The polarity could be inverted by SYSINV.
J4
DVDD
P
Digital Power Supply
H5
UD8
J5
DVDD
I/O
P
Description
Open for normal operation
Test pin. Open for normal operation
Digital Power Supply
Either of FID or VSYNC selected by the register.
Rec.656 decode mode :Output
Master mode : Output
Slave mode : Input
FID shows that “L” is odd field and ”H” is even field.
Rec.656 decode mode : Output
Master mode : Output
Slave mode : Input
J6
FID/VSYNC
I/O
H6
HSYNC
I/O
H7
DVSS
G
J7
SYSINV
H8
UD9
I/O
J9
NC
-
Open for normal operation
J8
D7
I
Video data input (MSB)
G8
D6
I
Video data input
Rev.00
I
Digital Ground
“L “ : data is latched with rising edge.
“H” : data is latched with falling edge.
Test pin. Open for normal operation
-7-
2004/Oct
ASAHIKASEI
[AK8813/14]
H9
D5
I
Video data input
G9
D4
I
Video data input
F8
DVDD
P
Digital Power Supply
F9
DVSS
G
Digital Ground
E8
NC
-
Open for normal operation
E9
D3
I
Video data input
D8
D2
I
Video data input
D9
D1
I
Video data input
C8
D0
I
Video data input
C9
TEST
I
Open for normal operation
B9
TEST
I
Open for normal operation
A9
NC
-
Open for normal operation
A8
SELA
I
The slave address is set with this pin.
“L”:40H “H”:42H
B8
SCL
I
Serial interface clock
B7
SDA
I/O
Serial interface data
A7
PD
I
Power Down Pin. After returning from PD mode to normal operation,
RESET Sequence should be done to AK8813/14.
A6
/RESET
I
After this pin becomes “L”, AK8813/14 starts the internal initializing
sequence.
After initializing sequence, AK8813/14 is set NTSC mode, Rec.656
decoding mode. All DACs Off condition.
After power up, AK8813/14 must be initialized with this pin.
(27MHz Clock is necessary for reset sequence.)
B6
AVSS
G
Analog Ground
A5
NC
-
Open for normal operation
B5
Y
O
Output of Luminance Signal.
B4
AVDD
P
Analog Power Supply
A4
C
O
Output of the Chrominance signal
B3
AVSS
G
Analog Ground
A3
CVBS
O
Output of Composite Video signal
B2
NC
-
Open for normal operation
A2
NC
-
Open for normal operation
C3
NC
-
Open for normal operation
(Note1) At ITU-R.BT656 I/F mode operation, FID/VSYNC, HSYNC pins should be pulled up to VDD with
100k-ohm Resistor
(Note2) This device requires reset operation. Before resetting the state of the pin of I/O are unknown state. After
reset sequence, I/Opins (FID/VSYNC, HSYNC) turns Hi-Z states.
Rev.00
-8-
2004/Oct
ASAHIKASEI
[AK8813/14]
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Min
Max
Units
-0.3
4.6V
V
Input Pin Voltage (Vin)
-0.3
VDD+0.3
V
Input Pin Current (Iin)
-
±10
mA
Analog Reference Current (IREF)
-
0.37
mA
Analog Output Current
-
11.6
mA
Storage Temperature
-40
125
°C
Supply Voltage (VDD)
DVDD, AVDD
(Note) When all Ground pins(DVSS, AVSS) are set to 0V.
Recommended Operating Conditions
Parameter
Min
Typ.
Max
Units
Supply Voltage (VDD)
2.8
3.3
3.6
V
Operating Temperature
-20
85
°C
Rev.00
-9-
2004/Oct
ASAHIKASEI
[AK8813/14]
DC Characteristics
Parameter
[Power Supply:2.8 ~ 3.6V
Symbol
Min
Digital Input High Voltage
VIH1
0.7VDD
Digital Input Low Voltage
VIL1
Digital Input leak Current
IL
Digital Output High Voltage
VOH
Digital Output Low Voltage
VOL1
Max
Temperature:-20 ~ 85°C]
Units
Conditions
V
Note1)
0.3VDD
V
Note1)
±10
uA
Note1)
2.4/2.2
V
IOH =-1mA Note 2)
Note 3)
0.4
V
IOL = 2mA Note 2)
2
I C Input High Voltage
VIH2
2
I C(SDA,SCL)
I2C Input Low Voltage
2
I C(SDA,SCL)
I2C(SDA) Output Voltage
Note 1)
Note 2)
Note 3)
Note )
0.7VDD
V
VIL2
0.3VDD
V
VOL2
0.4
V
IOL = 3mA
D[9:0],FID/VSYNC, HSYNC, SYSCLK, /RESET pin
FID/VSYNC, HSYNC pin
DVDD=2.8V~3.0V VOH 2.2V
Connected Test Pin to Ground, SELA and SYSINV Pin are desired polarity.
Analog Characteristics
[AVDD:3.3V Temperature:25°C Load Resistance 220ohm IREF Resistance 6.8kohm]
Parameter
Min
DAC Resolution
Typ
Max
Units
10
Conditions
bit
DAC Integral linearity error
±0.6
±2
LSB
DAC Differential linearity error
±0.4
±1
LSB
1.28
1.35
V
Note1)
5.0
mV
Note2)
±5
%
Note3)
dB
1MHz Full Scale
30
pF
Note4)
1.30
V
DAC Output Full Scale Voltage
1.21
DAC Output offset Voltage
Unbalances between DACs
±1
Isolation between DACs
50
DAC Load Capacitance
Internal Reference Voltage
1.17
Internal Reference Drift
1.235
-50
ppm/°C
Note 1) Under the condition of output load 220Ω, IREF pin with 6.8kΩ, using internal reference. The output full-scale current IOUT is
calculated as Full scale output voltage (typ. 1.28V) /220Ω=typ. 5.82mA.
Note 2) DAC output when feeding code of 0 (Decimal).
Note 3) Deviation between the DAC output when feeding 1V generating code of 800(Decimal).
Note 4) The value is a design target. This value is not tested.
Dissipation Current
[AVDD=DVDD=:3.3V Temperature:-25~85°C ]
Parameter
Min
Typ
Max
Units
Conditions
DAC Current (Active mode)
24
mA
Note1)
DAC Current (Sleep mode)
10
uA
Note2)
Power Down Current
10
100
uA
Note3)
Total Current
50
65
mA
Note4)
Note 1) All DACs are operating.
Note 2) All DACs are turned off with no system clock.
Note 3) In case the value after power down sequence.
Note 4) NTSC internal color bar with 3ch DACs operation and slave mode operation. DAC output pins is connected with only 220Ω load.
Rev.00
- 10 -
2004/Oct
ASAHIKASEI
[AK8813/14]
AC Characteristics (2.8V - 3.6V Temperature –20 ~ 85°C CL=30pF)
(1). SYSCLK
fCLK
tCLKL
50%Level between VIH and VIL
tCLKH
VIH
CLK
VIL
Parameter
SYSCLK
Symbol
Min.
fSYSCLK
Typ.
Max
27
Unit
MHz
SYSCLK Pulse width H
tCLKH
15
nsec
SYSCLK Pulse width L
tCLKL
15
nsec
(2). Pixel Data Input Timing
(2-1) SYSINV = Low
VIH
VIL
CLK
tDH
tDS
D7:D0
(2-2) SYSINV = High
VIH
VIL
CLK
tDH
tDS
D7:D0
Parameter
Symbol
Min
Data Setup Time
tDS
5
nsec
Data Hold Time
tDH
8
nsec
Rev.00
- 11 -
Typ
Max
Units
2004/Oct
ASAHIKASEI
[AK8813/14]
(3). Synchronizing Signal ( FID/VSYNC, HSYNC )
(3-1) SYSINV=Low
(3-1-1) Input Timing
VIH
VIL
SYSCLK
tDH
tDS
FID/VSYNC, HSYNC
Parameter
Symbol
Min
Typ.
Max
Units
Data Setup Time
tDS
5
nsec
Data Hold Time
tDH
8
nsec
(3-1-2) Output Timing
VIH
SYSCLK
tDEL
FID/VSYNC, HSYNC
Parameter
Delay from SYSCLK
Rev.00
Symbol
Min
tDEL
- 12 -
Typ.
Max
Units
27
nsec
2004/Oct
ASAHIKASEI
[AK8813/14]
(3-2) SYSINV = High
(3-2-1) Input Timing
VIH
SYSCLK
VIL
tDH
tDS
FID/VSYNC, HSYNC
Parameter
Symbol
Min
Typ.
Max
Units
Data Setup Time
tDS
5
nsec
Data Hold Time
tDH
8
nsec
(3-2-2) Output Timing
SYSCLK
tDEL
FID/VSYNC, HSYNC
Parameter
Delay from SYSCLK
Rev.00
Symbol
Min
tDEL
- 13 -
Typ.
Max
Units
27
nsec
2004/Oct
ASAHIKASEI
[AK8813/14]
(4). Reset (Initialize)
Reset Timing
/RESET
pRES
1
2
9
10
SYSCLK
Hi-Z
HSYNC,VSYNC,SDA
Indefinite state
Parameter
/RESET Pulse Width
Symbol
Min
pRES
10
Typ.
Max
Units
SYSCLK
After power up, I/O pins of AK8813/14 are in the indefinite state. It should be initialize with Reset
sequence. While reset sequence system clock should be input to AK8813/14 and SCL, SDA should be
High state.
(5) Power Down Sequence
/RESET
VSS
VDD
PD
pPD
1
2
99
100
101
SYSCLK
Parameter
Symbol
Min
/RESET Pulse Width
pSTOP
100
Typ.
Max
Units
SYSCLK
During “Power Down” state, control signal should be set to VDD state or VSS state.
Rev.00
- 14 -
2004/Oct
ASAHIKASEI
[AK8813/14]
2
(5). I C Bus (SCL 400kHz cycle mode)
(5-1) I/O Timing 1
tR
tHD:STA
tBUF
tSU:STO
tF
SDA
tF
tR
SCL
tSU:STA
tLOW
Parameter
Symbol
Min
tBUF
1.3
usec
tHD:STA
0.6
usec
Clock Pulse Low Time
tLOW
1.3
usec
Bus Signal Rise Time
tR
300
nsec
Bus Signal Fall Time
tF
300
nsec
Bus Free Time
Hold Time (Start Condition)
Setup Time(Start Condition)
tSU:STA
Max
Units
0.6
usec
Setup Time(Stop Condition)
tSU:STO
0.6
usec
All the figures shown above list are not restricted by AK8813/14 but are restricted by I2C Bus standard.
Please see the I2C Bus standard for further details.
(5-2) I/O Timing 2
tHD:DAT
SDA
tHIGH
SCL
tSU:DAT
Parameter
Symbol
Min.
Data Setup Time
tSU:DAT
100 (1)
Data Hold Time
tHD:DAT
0.0
tHIGH
0.6
Clock Pulse High Time
Max.
Unit.
nsec
0.9 (2)
usec
usec
(Note1) In case of normal I2C bus mode tSU:DAT ≥250nsec
(Note2) Using under minimum tLOW, this value must be satisfied.
(Note3) I2C I/F reset is done by reset sequence of AK8813/14, System clock (27MHz) is necessary to do
reset sequence. However, SDA pin is always Hi-Z state when PD pin is set to High.
Rev.00
- 15 -
2004/Oct
ASAHIKASEI
[AK8813/14]
FUNCTIONAL DESCRIPTION
♦ Reset
When the reset pin [ /RESET ] set to “L”, AK8813/14 is in reset state. AK8813/14 starts in the internal
initializing sequence at the trailing edge of the first SYSCLK after the reset pin is “L”. All internal registers
are set to be default value by this initializing sequence. AK8813/14 needs at least 10 clock counts of
SYSCLK for this reset operation. After the reset operation, the video output pins are in high-impedance.
AK8813/14 requires SYSCLK for the reset operation.
♦ Master Clock
AK8813/14 requires 27MHz clock at SYSCLK pin for operation. Video input data (ITU-R BT.656) is
sampled at the trailing edge of this 27MHz. SYSINV decides the edge direction.
SYSINV = L
Data is sampled at rising edge of SYSCLK.
SYSINV = H
Data is sampled at falling edge of SYSCLK.
♦ Video Signal Interface
AK8813/14 can interface with the video input data by the following 3 modes. The mode is set by the
register [ Interface mode register(00H) ].
1. ITU-R BT.656 Format
AK8813/14 decodes EAV in stream data and manages an internal synchronization.
In this case, AK8813/14 outputs FID (odd : “L” even : “H”)/ VSYNC and HSYNC.
CCIR-bit of [ Interface mode register (00H) ] should be set “1” .
2. ITU-R BT.656 like Format (4:2:2 Y/Cb/Cr)
There are Master and Slave modes, for ITU-R BT.656 like Format which does not include EAV. In this
mode, CCIR-bit of [ Interface mode register(00H) ] should be set “0” .
<Master Mode>
AK8813/14 provides FID/VSYNC and HSYNC to an external device according to the AK8813/14
internal timing counter. AK8813/14 starts to sample the input data at the fixed value on the internal
pixel counter.
In this mode, following setting should be done to [Interface mode register(00H)].
CCIR-bit = 0
MAS-bit = 1
<Slave Mode>
FID/VSYNC and HSYNC are supplied by an external device. AK8813/14 samples the data as same
manner of Master mode.
In this mode, following setting should be done to [Interface mode register(00H)].
CCIR-bit = 0
MAS-bit = 0
Rev.00
- 16 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Video Signal Conversion
Video reconstruction module converts the multiplexed data (ITU-R. BT601 Y/Cb/Cr) to the interlace
format of NTSC-M, PAL-M, PAL-B,D,G,H,I,N and other formats (ex. NTSC-4.43 and PAL60). The video
reconstruction format, the line number, the color encode way(NTSC or PAL) and the frequency of Color
Sub-carrier is specified by [Video Process 1 register(01H)]. (cf. Burst Signal Table) The frequency and the
phase of Color Sub-carrier are also adjustable by [Sub C. Freq. register(06H)] and [Sub C. Phase
register(07H)]. The Sub-carrier has a free-running mode and a reset-mode. In the reset-mode, the
Sub-carrier is reset automatically to the initial phase for every 4 fields (NTSC) or 8 fields (PAL).
Rev.00
- 17 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Luminance Filter
Luminance signal passes through the 2x Low Pass filter with sin(x)/x compensation. Fig.1 is the
characteristic of Luminance Filter.
Luma Filter
10
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
Gain [dB]
-10
-20
-30
-40
-50
-60
Frequency [MHz]
Fig. 1 Luminance Filter
Rev.00
- 18 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Chrominance Filter
Chrominance signals (Cb,Cr) before Sub-carrier modulation pass through the 1.3 MHz Low pass filter
shown in Fig.2. Chrominance signal modulated by Sub-carrier passes through the filter shown in Fig.3.
Frequency [MHz]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
10
0
Gain [dB]
-10
-20
-30
-40
-50
-60
-70
Fig. 2 Chroma-1 LPF
0.0
1.0
2.0
3.0
4.0
Frequency [MHz]
5.0 6.0 7.0 8.0
9.0 10.0 11.0 12.0 13.0
10
0
Gain [dB]
-10
-20
-30
-40
-50
-60
-70
Fig. 3 Chroma-2 LPF
Rev.00
- 19 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Color burst signal
Color burst signal is generated by 32bits-length Digital Frequency Synthesizer. The Default frequency of
the color burst is selected by [Video Process 1 Register(0x01)].
NTSC-M
3.57954545
Video Process
1
[VM1,VM0]
[0,0]
PAL-M
3.57561188
[0,1]
PAL-B,D,G,H,I
4.43361875
[1,1]
PAL-N(Arg.)
PAL-N(non-Arg.)
PAL60
NTSC-4.43
3.5820558
4.43361875
4.43361875
4.43361875
[1,0]
Standard
Sub-carrier Freq.
[MHz]
[1,1]
[1,1]
[1,1]
Burst Signal Table
Sub-carrier frequency 3.57561188MHz is allowed when PAL-M mode is selected.
The burst frequency and initial phase resolution are as follows.
Frequency resolution
SCH Phase resolution
0.8046Hz
360°/256
♦ Video DAC
AK8813/14 has the three current driven 10bits-DACs at 27MHz operation. The full scale voltage of DAC
is determined by the current output from IREF pin. Typical output voltage is 1.28Vo-p under the condition
of VREFIN 1.235V, 6.8KΩ between IREF pin and Ground(AVSS) and DAC load resistance of 220Ω. This
full-scale voltage should be set in the range of 1.17V to 1.33V by adjusting the resistor which terminates
IREF pin. Each DAC output can be set to “active state” or to “inactive state” individually by [DAC Mode
register(05H)]. When DAC is in “inactive state”, the output is Hi-impedance. When all DACs are set to
“inactive state”, the analog part of AK8813/14 goes into sleep mode. In this case AK8813/14 stops
outputting the reference voltage(VREF) output. When any DAC is switched over in “active state” from sleep
mode, AK8813/14 starts outputting reference voltage. In this case AK8813/14 needs several milliseconds
for VREF wake-up time.
Using internal VREF as the reference voltage, connect [VREF OUT] pin with [VREF IN] pin and [VREF
OUT] pin is terminated with more than 0.1uF capacitor.
♦ Use external Reference Voltage
In order to improve the accuracy of DAC output, external reference voltage may be used. In this case,
VREFOUT pin still needs to be terminated with more than 0.1uF capacitor.
Rev.00
- 20 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Copy Protection
AK8814 has the function of Macrovision copy protection. Information about the Macrovision encoding
functions of the AK8814 is available to Macrovision licensees.
AK8813 doesn’t have this function.
Macrovision Corporation
2830 De La Cruz Boulevard
Santa Clara, California 95050 U.S.A.
Main Telephone (switchboard): +1 408 743-8600
Main Fax: +1 408 743-8610
Technical Support Group Fax: +1 408 743-8617
Rev.00
- 21 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Closed Caption and Extended Data
AK8813/14 supports both Closed Captioning and Extended Data. They are controlled “ON” or ”OFF”
respectively by [ Video Process 2 Register(02H) ]. Each data consists of 2 continuous bytes
register( Closed Caption R (16H,17H) ), and it is recognized as the data is renewed when the second
byte(17H register) is written in the register. After the data is renewed, AK8813/14 encodes Closed
Captioning and Extended Data at the designated line. If the data isn’t renewed, AK8813/14 outputs
“ASCII-NULL” code. The data is supposed as Odd Parity and 7 bit US-ASCII code. Host should provide a
parity bit.
*In PAL encoding mode, AK8813/14 outputs them at the same timing and same pattern as NTSC.
*The line where Closed Captioning data is encoded is as follows.
525/60 System (SMPTE)
625/50 System (CCIR)
Closed Caption
21 Line default
22 Line default
Extended Data
284 Line default
335 Line default
240+/- 48nsec
10.5 +/- 0.25usec
12.91 usec
240+/- 48nsec
Two 7-bit + PARITY ASCII
Characters Data
D0-D6
PARITY
D0-D6
PARITY
START
50 +/- 2 IRE
40IRE
10.003 +/- 0.25usec
27.382 usec
33.764 usec
61 usec
Fig. 4 Closed Captioning Wave form
Rev.00
- 22 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Video ID
AK8813/14 supports Video ID (EIAJ standard, CPR-1204) encoding for the distinction of an aspect ratio
or CGMS-A etc. Setting or Resetting the VBID-bit of [ Video Process 2 Register(02H) ], this function is
switched On/Off. The data is set by using [ Video ID Data Register(1AH, 1BH) ].
VBID Data Renewal Timing.
VSYNC
S et C ontro l R egister
2
I C SDA
N EW D AT A
DATA
O LD D A T A
N EW D AT A
Fig. 5 VBID Data renewal Timing
VBID Data Layout
VBID is consists of 20 bits and its format is shown as follows.
AK8813/14 generates CRC code automatically and appends it to the data. Initial value of the
Polynomial is 1.
DATA
bit1
WORD0
2bit
bit20
WORD1
4bit
WORD2
8bit
CRC
6bit
Fig. 6 VBID code assignment
Rev.00
- 23 -
2004/Oct
ASAHIKASEI
[AK8813/14]
VBID Waveform
Ref.
bit1 bit2 bit3
•••
bit20
70IRE +/- 10IRE
0IRE + 10 IRE
− 5 IRE
2.235usec +/- 50nsec
11.2usec +/- 0.3usec
11.2usec +/- 0.3usec
1H
Fig. 7 VBID Wave Form
525/60 system
625/50 system
Amplitude
70 IRE
490 mV
Encode Line
20/283
20/333
VBID parameter table
Rev.00
- 24 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ WSS
AK8813/14 supports WSS(ITU-R.Bt.1119) encoding for the distinction of an aspect ratio etc. Setting or
Resetting the WSS-bit of [ Video Process 2 Register(02H) ], this function is switched On/Off. The data is
set by using [ WSS Data Register(08H, 09H) ].
WSS Data Renewal Timing
VSYNC
S et C ontro l R egister
2
I C SDA
N EW D AT A
DATA
O LD D A T A
N EW D AT A
Fig. 8 WSS Data Renewal Timing
500mV +/- 50%
0H
27.4usec
1.5usec
10.5usec
11.0 +/- 0.25usec
38.4usec
44.5usec
Fig. 9 WSS Wave Form
Encode Line: Line 23
Coding: bi-phase modulation coding
Clock: 5MHz (Ts = 200ns)
Run-in
Start code
29 elements
24 elements
Group 1
Aspect ratio
24 elements
Bit numbering
0
1
2
3
LSB
MSB
0 : 000111
1 : 111000
0x1F1C71C7
Rev.00
Group 2
Enhanced
Services
24 elements
Bit numbering
4
5
6
7
LSB
MSB
0 : 000111
1 : 111000
Group 3
Subtitles
18 elements
Bit numbering
8
9
10
LSB
MSB
0 : 000111
1 : 111000
Group4
Reserved
18 elements
Bit numbering
11
12
0x1E3C1F
- 25 -
13
LSB MSB
0 : 000111
1 : 111000
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ AK8813/14 Interface Timing (Part 1) Master mode & ITU-R BT. 656 mode
On ITU-R BT.656 decoding mode or master mode operation, AK8813/14 outputs HSYNC and FID or
VSYNC (selected by register).
When AK8813/14 receives ITU-R BT. 656 signal, AK8813/14 decodes [EAV] code in the data for
synchronization then outputs the HSYNC. AK8813 outputs HSYNC at the rising edge of SYSCLK in the
timing of the 32nd/24th(NTSC/PAL) data slot, which is counted from the [EAV] starting point as below.
(See also AC Characteristics 2-2[Input Synchronizing Signal])
On master mode operation, the front device connected with AK8813/14 (ex. MPEG Decoder) starts to set
Cb on the 276th/288th(NTSC/PAL) slot, after starting to count HSYNC falling edge as
32nd/24th(NTSC/PAL) slot.
FID/VSYNC is output synchronously with HSYNC at the timing of solid line as in Fig. 10 Video Field.
Y/Cb/Cr
Data#
525system
Data#
625system
Cb
EAV
Y Cr
Y
Cb
Y
Cr
Y
Cb
Y
Cr
Y
Cb
SAV
Y Cr
Y
Cb
Y
Cr
Y
Cb
360 720 360 721 361 722 361 723
368 736 368
855 428 856 428 857
0
0
0
1
1
360 720 360 721 361 722 361 723
366 732 366
861 431 862 431 863
0
0
0
1
1
SYSCLK
33/ 25T(525/ 625)
243/ 263T(525/ 625)
276/ 288T(525/ 625)
HSYNC
TBDT
AnalogOUT
Fig. 10 Interface Timing (ITU-R BT.656 or Master mode)
Rev.00
- 26 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ AK8813/14 Interface Timing (Part 2) Slave mode
On slave mode operation, HSYNC and FID or VSYNC (Selected by register) are input to AK8813/14.
AK8813/14 monitors the transition of HSYNC at the timing of the rising edge of SYSCLK. (Refer to AC
Characteristic 2-1. [Input Synchronizing Signal]) After AK8813/14 recognizes HSYNC is Low-logic,
AK8813/14 sets the slot number to the 32nd/24th(NTSC/PAL), internally, then AK8813/14 starts to sample
the data as Cb on 276th/288th(NTSC/PAL) slot.
Video field is recognized the transition timing between FID/VSYNC and HSYNC. (Fig.10. Video Field) As
in the figure, there is a tolerance of ±1/4H.
244T / 264T (525/625)
27MHz
Data
Cb0
Y0
Cr0
Y1
Cb1
Y2
Cr1
HSYNC
TBD-clk
Fig. 11 Interfacing timing (Slave mode)
1/2 H
1/2 H
HSYNC
Start of 1st Field
1/4 H 1/4 H
VSYNC/FIELD
Start of 2nd Field
1/4 H1/4 H
VSYNC/FIELD
Fig. 12 Video Field
Rev.00
- 27 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ HSYNC FID/VSYNC Timing
525 System
Digital
Line-No.
525
1
2
3
262
263
264
265
622
623
624
4
5
6
7
8
9
10
11
HSYNC
VSYNC
FID
Digital
Line-No.
266
267
268
269
270
271
272
273
274
HSYNC
VSYNC
FID
625 System
Digital
Line-No.
625
1
2
3
4
5
6
7
8
HSYNC
VSYNC
FID
Digital
Line-No.
310
311
312
313
314
315
316
317
318
319
320
HSYNC
VSYNC
FID
Fig. 13 HSYNC FID/VSYNC Timing
Rev.00
- 28 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Internal Color Bars Generator
AK8813/14 generates the Common Color Bar signal for NTSC and PAL internally. The generated Color
Bar is “100% Amplitude, 100% Saturation”. When AK8813/14 is set to Black Burst output mode, AK8813/14
does not output Color bar even Color bar output register is set.
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Luminance
100%White
Blanking Level
Synctip Level
Chrominance
Fig. 14 Luminance and Chrominance waveform
The following values are code for ITU-R. BT601
Cb
Y
Cr
WHITE
128
235
128
YELLOW
16
210
146
CYAN
166
170
16
GREEN
54
145
34
MAGENTA
202
106
222
RED
90
81
240
BLUE
240
41
110
BLACK
128
16
128
♦ Internal Black Burst Generator
AK8813/14 generates Black burst signal for NTSC and PAL internally. When AK8813/14 is set to Black
burst output mode, AK8813/14 works same operation as that the input Y/Cb/Cr data is 16/128/128. In this
mode, AK8813/14 does not output Color bar even Color bar output register is set.
Rev.00
- 29 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Synchronizing Signal and Burst Waveform
(1-1) NTSC / NTSC-4.43 / PAL-M( Video Process 1 Register [VM3:VM2]-bit = 00 / 01 ) (SMPTE-170M)
H o r iz o n ta l B la n k in g r is e t im e
90%
50%
50%
B u r s t E n v e lo p e
r is e tim e
90%
S y n c r is e t im e
10%
10%
B u r s t H e ig h t
90%
B u rs t
H o r iz o n ta l
r e f e r e n c e p o in t
50%
50%
S yn c L e ve l
10%
S yn c
H . r e f . t o B u r s t S ta r t
H b la n k in g s ta r t
to H -re fe re n c e
H r e f e r e n c e t o B la n k in g E n d
Fig. 15 Synchronizing Signal and Burst Waveform
measurement
point
Total line period(derived)
Sync Level
Horizontal Blanking rise time
Sync rise time
Burst envelope rise time
H-Blanking start to H-reference
Horizontal Sync
Horizontal reference point to
burst start
H reference to H-blanking end
Burst
Burst Height *
value
Recommended
tolerance
units
10% - 90%
10% - 90%
10% - 90%
50%
50%
63.556
40
140
140
300
1.5
4.7
+/- 1
+/- 20
+/- 20
+200 -100
+/- 0.1
+/- 0.1
usec
IRE
nsec
nsec
nsec
usec
usec
50%
19
defined by SC/H
cycles
50%
50%
9.2
9
40
+ 0.2 –0.1
+/- 1
+/- 1
usec
cycles
IRE
* Burst height of PAL-M is 306mV
19 cycles +/-10°
9 cycles
50%
Fig. 16
Rev.00
Synchoronizing Signal and Burst Waveform(NTSC)
- 30 -
2004/Oct
ASAHIKASEI
[AK8813/14]
(1-2-1) HSYNC Timing (NTSC/NTSC4.43)
3H
B
A
1
3H
E
0 .5 H
2
3H
F
D
3
4
5
C
6
7
8
9
19
1 9 + 1 /- 2 L in e
(S e t C o n tro l R e g is te r)
3H
3H
3H
0 .5 H
263
264
265
266
267
268
269
270
271
272
283
273
Fig. 17 HSYNC Timing
Symbol
A
B
C
D
E
F
Duration
429T
858T
31T
429T
858T
63T
Measurement point
Reference
50%
13.5MHz Clock
G
I
H
I
I
Equalizing Pulse
Equalizing Pulse and Serration Pulse
Measurement
point
Symbol
H
G
I
286mV
Serration Pulse
Fig. 18
G
I
Field Period (derived)
Frame period (derived)
Vertical blanking start before
equalizing pulse
Vertical blanking
(63.556usec x 20lines + 1.5usec)
Pre-equalizing duration
Pre-equalizing pulse width
Vertical sync duration
Vertical serration pulse width
Post-equalizing duration
Post-equalizing pulse width
Sync rise time
Value
Recommended
tolerance
16.6833
33.3667
first
50%
50%
50%
50%
units
msec
msec
1.5
+/- 0.1
usec
19* lines + 1.5
usec
3
2.3
3
4.7
3
2.3
140
0
+/- 0.1
lines
usec
lines
usec
lines
usec
lines
usec
nsec
+/- 0.1
+/- 0.1
+/- 0.1
+/- 20
*This value can be set by the register.
Rev.00
- 31 -
2004/Oct
ASAHIKASEI
[AK8813/14]
(1-2-2) FID/VSYNC Timing and Phase of Burst (PAL-M)
A
519
257
520
258
521
259
522
523
260
524
261
525
262
1
263
2
264
3
265
4
266
5
267
6
268
7
269
8
9
A
B
270
271
A
519
257
520
258
521
259
522
260
523
524
261
525
262
263
1
2
264
3
265
4
266
5
267
6
268
269
10
272
B
7
8
A
B
270
B
9
271
10
272
Fig. 19 FID/VSYNC Timing and Phase of Burst
A : Phase of Burst : nominal Value + 135°
B : Phase of Burst : nominal Value - 135°
Rev.00
- 32 -
2004/Oct
ASAHIKASEI
[AK8813/14]
(2-1) PAL-B,D,G,H,I,N / PAL-60 ( Video Process 1 Register [VM3:VM2]-bit = 11)
H o r iz o n ta l B la n k in g r is e t im e
90%
50%
50%
B u r s t E n v e lo p e
r is e tim e
90%
S y n c r is e t im e
10%
10%
B u r s t H e ig h t
90%
B u rs t
H o r iz o n ta l
r e f e r e n c e p o in t
50%
50%
S yn c L e ve l
10%
H o r iz o n ta l S y n c
H . r e f . t o B u r s t S ta r t
H b la n k in g s ta r t
to H -re fe re n c e
H r e f e r e n c e t o B la n k in g E n d
Fig. 20 PAL Waveform
measurement
point
Total line period(derived)
Sync Level
Horizontal Blanking rise time
Sync rise time
Burst envelope rise time
H-Blanking start to H-reference
Horizontal Sync
Horizontal reference point to
burst start
H reference to H-blanking end
Burst *
Burst Height **
Rev.00
value
Recommended
tolerance
units
64.0
300
0.3
0.2
+/- 0.1
+/- 0.1
1.5
4.7
+/- 0.3
+/- 0.2
50%
19
defined by SC/H
cycles
50%
50%
10.5
10
300
+/- 1
usec
cycles
mV
10% - 90%
10% - 90%
10% - 90%
50%
50%
- 33 -
usec
mV
usec
usec
nsec
usec
usec
2004/Oct
ASAHIKASEI
[AK8813/14]
(2-2) FID/VSYNC Timing and Phase of Burst PAL-B,D,G,H,I,N / PAL-60
( Video Process 1 Register [VM3:VM2]-bit = 11)
A
308
620
308
620
309
621
309
621
310
622
311
623
310
622
312
624
311
623
625
312
624
313
314
1
313
625
315
2
314
1
316
3
315
2
317
4
316
3
318
5
317
4
319
320
A
B
6
7
A
B
318
319
A
B
5
6
B
322
321
322
8
320
7
321
8
Fig. 21 FID/VSYNC Timing and Phase of Burst
A : Phase of Burst : nominal Value + 135°
B : Phase of Burst : nominal Value - 135°
Rev.00
- 34 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ I2C Control Sequence
AK8813/14 is controlled by I2C bus. The slave address can be selected as 40H or 42H by selecting SELA
pin.
SELA
SLAVE Address
PULL Down [Low]
0x40
PULL UP [High]
0x42
Operation :
Write Sequence:
(a)1byte Write Sequence
Slave
Address
S
w
Sub
Address
A
1-
8-bits
A
1-
8-bits
bit
bit
Data
A
Stp
1-
8-bits
bit
(b) Sequential Write Operation
Slave
Address
S
w
A
Sub
Address(n)
1-
8-bits
bit
A
1-
8-bits
bit
Data(n)
A
Data(n+1)
1-
8-bits
bit
8-bits
A
•••
Data(n+m)
1-
8-bits
bit
A
stp
1bit
Read Sequence:
S
Slave
Address
8-bits
w
A
Sub
Address(n)
A
1
8-bits
1
rS
Slave
Address
8-bits
R
A
Data1
A
Data2
A
Data3
A
1
8-bits
1
8-bits
1
8-bits
1
•••
Data n
Ā
8-bits
1
S, rS : Start Condition
A:
Acknowledge (SDA Low )
Ā:
Not Acknowledge (SDA High)
stp : Stop Condition
R/W 1 : Read 0 : Write
: Master device (Host)
: Slave device (AK8813/14)
Rev.00
- 35 -
2004/Oct
stp
ASAHIKASEI
[AK8813/14]
♦ Register Map
Sub
Address
0x00
0x01
0x02
Register
Default
R/W
Function
Interface Mode Register
Video Process 1 Register
Video Process 2 Register
0x00
0x00
0x00
R/W
R/W
R/W
0x03
Video Process 3 Register
0x00
R/W
Setting Interface mode
Setting Standard (NTSC, PAL etc.)
Setting Closed Caption/Extended Data/VBID
Setting Composite signal or Component signal
Adjusting Chrominance/Luminance Delay
0x04
0x05
Reserved Register
DAC Mode Register
Sub Carrier Frequency
Register
Sub Carrier Phase
Register
WWS Data 1 Register
WWS Data 2 Register
0xAA
0x00
R/W
R/W
Each DAC On/Off Switch
0x00
R/W
Adjusting Sub-carrier frequency
0x00
R/W
Adjusting Sub-carrier phase
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
WSS Data Register
WSS Data Register
Closed Caption Lower byte Data
Closed Caption Upper byte Data
0x00
R/W
Extended Lower byte Data
0x00
R/W
Extended Upper byte Data
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R
R
R
Video ID Lower byte Data
Video ID Upper byte Data
Status
Device ID
Revision
0x06
0x07
0x08
0x09
0x16
0x17
0x18
0x19
0x1A
0x1B
0x24
0x25
0x26
Rev.00
Closed Caption 1 Register
Closed Caption 2 Register
Closed Caption Extended 1
Register
Closed Caption Extended 2
Register
Video ID 1 Register
Video ID 2 Register
Status Register
Device ID Register
Device Revision Register
- 36 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Interface Mode Register (R/W) [Address 0x00]
Default Value 0xA4
Sub Address 0x00
bit 7
BLN4
bit 6
BLN3
bit 5
BLN2
1
0
1
bit 4
bit 3
BLN1
BLN0
Default Value
0
0
bit 2
FID
bit 1
MAS
bit 0
REC656
1
0
0
Interface Mode Register Definition
BIT
Register Name
bit 0
REC656
REC656
I/F mode bit
R/W
bit 1
MAS
Master mode
Set bit
R/W
bit 2
FID
Field ID Set bit
R/W
bit 3
~
bit 7
BLN0
~
BLN4
Blanking Line
No bit
R/W
Rev.00
R/W
Definition
0 : REC656 non-decode
1 : REC656 decode
(At Rec.656 mode operation, MAS-bit should be 0.)
0 : Slave mode
1 : Master mode When REC=0,it’s valid
0 : Select VSYNC
1 : Select FID
Line Blanking No.
- 37 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Video Process 1 Register (R/W) [Address 0x01]
Sub Address 0x01
Default Value 0x30
bit 7
BBG
bit 6
CBG
bit 5
SETUP
0
0
1
bit 4
bit 3
SCR
VM3
Default Value
1
0
bit 2
VM2
bit 1
VM1
bit 0
VM0
0
0
0
Video Process 1 Register Definition
BIT
Register
Name
R/W
bit 0
~
bit 3
VM0
~
VM3
Video Mode 0
Register
~
Video Mode 3
Register
R/W
bit 4
SCR
Sub Carrier
Reset bit
R/W
bit 5
SETUP
Setup bit
R/W
bit 6
CBG
bit 7
BBG
Color Bar
Generator bit
Black Burst
Generator
R/W
R/W
Definition
[VM1:VM0]-bit
00 : 3.57954545 MHz
01 : 3.57561188 MHz
10 : 3.5820558 MHz
11 : 4.43361875 MHz
[VM3:VM2]-bit
00 : 525/60
01 : 525/60 PAL (PAL-M etc.)
10 : Reserved
11 : 625/50 PAL (PAL-B,D,G,H,I,N)
0 : Sub C. Phase Reset off
1 : Standard Field Reset
0 : No Set-up
1 : 7.5 IRE Set-up
0 : Video Encode
1 : Generates color bar
0 : Video Encode
1 : Generates black burst
Register Setting of each standard is shown as following ;
VM3-VM0
NTSC-M
0000
PAL-B,D,G,H,I
1111
PAL-M
0101
PAL-60
0111
NTSC4.43
0011
• When SCR is “ON”, the Subcarrier Phase is reset every 4 fields for NTSC, every 8 fields for PAL.
• Even when SETUP is “ON”, there is no Set-up (Pedestal) during the blanking lines.
Rev.00
- 38 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Video Process 2 Register (R/W) [Address 0x02]
Sub Address 0x02
default Value 0x00
bit 7
Reserved
bit 6
Reserved
bit 5
Reserved
0
0
0
bit 4
bit 3
Reserved
WSS
Default Value
0
0
bit 2
CC284
bit 1
CC21
bit 0
VBID
0
0
0
Video Process 2 Register Definition
BIT
Register
Name
bit 0
VBID
Video ID bit
R/W
bit 1
CC21
Closed Caption bit
R/W
bit 2
CC284
Closed Caption
Extended Data bit
R/W
bit 3
WSS
WSS set bit
R/W
bit 4
~
bit 7
Reserved
Reserved bit
R/W
R/W
Definition
0 : Video ID off
1 : Video ID on
0 : Closed caption off
1 : Closed Caption on
0 : Extended Data off
1 : Extended data on
0 : WSS off
1 : WSS on
Reserved
Video Process 3 Register (R/W) [Address 0x03]
Sub Address 0x03
default Value 0x00
bit 7
Reserved
bit 6
Reserved
bit 5
SYD2
0
0
0
bit 4
bit 3
SYD1
SYD0
Default Value
0
0
bit 2
CYD2
bit 1
CYD1
bit 0
CYD0
0
0
0
Video Process 3 Register Definition
BIT
bit 0
~
bit 2
bit 3
~
bit 5
bit 6
~
bit 7
Register
Name
CYD0
~
CYD2
SYD0
~
SYD2
Reserved
R/W
Definition
Composite Y
Delay bit
R/W
S-Video Y Component delay no. from Chroma: 2's comp.
S-video Y Delay bit
R/W
Composite Y Component delay no. from Chroma: 2's comp.
Reserved bit
R/W
Reserved
• S-video and Y component of the composite signal can be shifted for the chroma signal
independently at ±3-system clock (27MHz).
Rev.00
- 39 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Reserved Register (R/W) [Address 0x04]
Sub Address 0x04
default Value 0xAA
bit 7
Reserved
bit 6
Reserved
bit 5
Reserved
1
0
1
bit 4
bit 3
Reserved
Reserved
Default Value
0
1
bit 2
Reserved
bit 1
Reserved
bit 0
Reserved
0
1
0
Reserved
BIT
Register
Name
bit 0
~
bit 7
Reserved
R/W
Reserved bit.
R/W
Definition
Reserved
DAC Mode Register (R/W) [Address 0x05]
Sub Address 0x05
default Value 0x00
bit 7
Reserved
bit 6
Reserved
bit 5
Reserved
0
0
0
bit 4
bit 3
Reserved
Reserved
Default Value
0
0
bit 2
OUTCP
bit 1
OUTC
bit 0
OUTY
0
0
0
DAC Mode Register Definition
BIT
Register
Name
bit 0
OUTY
bit 1
bit 2
bit 3
~
bit 7
OUTC
OUTCP
Reserved
R/W
YDAC Out bit
CDAC Out bit
CPDAC Out bit
Reserved bit.
R/W
R/W
R/W
R/W
Definition
0: Y signal output : OFF
1: Y signal output : ON
0: Chrominance signal output : OFF
1: Chrominance signal output : ON
0: Composite video signal or U signal output : OFF
1: Composite video signal or U signal output : ON
Reserved
• Video output of AK8813/14 (DAC) can be forced “OFF” independently.
The output of DAC that is forced “OFF” is Hi-impedance. When three DACs are forced
“OFF”, then the internal VREF is also forced “OFF”. In this case, it takes several milliseconds
before the internal VREF reaches the proper voltage after any DAC becomes “ON”.
Rev.00
- 40 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Sub Carrier Frequency Control Register (R/W) [Address 0x06]
Sub Address 0x06
default Value 0x00
bit 7
SUBF7
Bit 6
SUBF6
bit 5
SUBF5
0
0
0
bit 4
bit 3
SUBF4
SUBF3
Default Value
0
0
bit 2
SUBF2
bit 1
SUBF1
bit 0
SUBF0
0
0
0
Sub Carrier Frequency Control Register Definition
Register
Name
SUBF0
~
SUBF7
BIT
bit 0
~
bit 7
R/W
Sub Carrier
Frequency Control
bit
Definition
Adjustment of frequency between
R/W
+127 and –128 step of 0.8Hz
Sub Carrier Phase Control Register (R/W) [Address 0x07]
Sub Address 0x07
default Value 0x00
bit 7
SUBP7
Bit 6
SUBP6
bit 5
SUBP5
0
0
0
bit 4
bit 3
SUBP4
SUBP3
Default Value
0
0
bit 2
SUBP2
bit 1
SUBP1
bit 0
SUBP0
0
0
0
Sub Carrier Phase Control Register Definition
Register
Name
SUBP0
~
SUBP7
BIT
bit 0
~
bit 7
R/W
Sub Carrier
Phase Control
bit
Definition
Adjustment of frequency between
R/W
+127 and –128 step of 0.8Hz
• Sub- carrier phase is adjustable by (360° /256) step.
WSS Data 1 Register (R/W) [Address 0x08]
WSS Data 2 Register (R/W) [Address 0x09]
Sub Address 0x08
default Value 0x00
bit 7
G2-7
bit 6
G2-6
bit 5
G2-5
0
0
0
bit 4
bit 3
G2-4
G1-3
Default Value
0
0
bit 2
G1-2
bit 1
G1-1
bit 0
G1-0
0
0
0
bit 4
bit 3
G4-12
G4-11
Default Value
0
0
bit 2
G3-10
bit 1
G3-9
bit 0
G3-8
0
0
0
Sub Address 0x09
default Value 0x00
bit 7
Reserved
bit 6
Reserved
bit 5
G4-13
0
0
0
• AK8813/14 generates the necessary sub-carrier frequency from a system clock by DFS
(Digital Frequency Synthesizer)
• Frequency of default is adjustable by specifying this bit. This bit adjusts the default
frequency.
Rev.00
- 41 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Closed Caption Data 1 Register (R/W) [Address 0x16]
Closed Caption Data 2 Register (R/W) [Address 0x17]
Sub Address 0x16
default Value 0x00
bit 7
CC7
bit 6
CC 6
bit 5
CC5
0
0
0
bit 4
bit 3
CC4
CC3
Default Value
0
0
bit 2
CC2
bit 1
CC1
bit 0
CC0
0
0
0
Sub Address 0x17
default Value 0x00
bit 7
CC15
bit 6
CC14
bit 5
CC13
0
0
0
bit 4
bit 3
CC12
CC11
Default Value
0
0
bit 2
CC10
bit 1
CC9
bit 0
CC8
0
0
0
bit 4
bit 3
EXT4
EXT3
Default Value
0
0
bit 2
EXT2
bit 1
EXT1
bit 0
EXT0
0
0
0
bit 4
bit 3
EXT12
EXT11
Default Value
0
0
bit 2
EXT10
bit 1
EXT9
bit 0
EXT8
0
0
0
Closed Caption Extended Data 1 Register (R/W) [Address 0x18]
Closed Caption Extended Data 2 Register (R/W) [Address 0x19]
Sub Address 0x18
default Value 0x00
bit 7
EXT7
bit 6
EXT6
bit 5
EXT5
0
0
0
Sub Address 0x19
default Value 0x00
bit 7
EXT15
bit 6
EXT14
bit 5
EXT13
0
0
0
• When the 2nd byte of Closed Caption Data and Extended Data is written in, AK8813/14
recognizes the renewed data and encodes it in the video line.
When the data is not renewed AK8813/14 outputs NULL code.
Rev.00
- 42 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Video ID 1 Register (R/W) [Address 0x1A]
Video ID 2 Register (R/W) [Address 0x1B]
Sub Address 0x1A
default Value 0x00
bit 7
Reserved
bit 6
Reserved
bit 5
VBID1
0
0
0
bit 4
bit 3
VBID2
VBID3
Default Value
0
0
bit 2
VBID4
bit 1
VBID5
bit 0
VBID6
0
0
0
bit 4
bit 3
VBID10
VBID11
Default Value
0
0
bit 2
VBID12
bit 1
VBID13
bit 0
VBID14
0
0
0
bit 2
STS2
bit 1
STS1
bit 0
STS0
Sub Address 0x1B
default Value 0x00
bit 7
VBID7
bit 6
VBID8
bit 5
VBID9
0
0
0
• Please write value 0 at Reserved bit.
• Bit numbers correspond to Fig. 5 VBID code assignment.
• AK8813/14 generates CRC 6 bit data automatically.
Status Register (R/W) [Address 0x24]
Sub Address 0x24
bit 7
Reserved
bit 6
Reserved
bit 5
EN284
bit 4
EN21
bit 3
SYNC
Status Register Definition
bit 0
~
bit 2
Register
Name
STS0
~
STS2
bit 3
SYNC bit
BIT
bit 4
bit 5
bit 6
~
bit 7
EN21
EN284
Reserved
R/W
Status bit
R
S-video Y Delay bit
R
Encode21 bit
Encode 284 bit
Reserved bit.
R
R
R
Definition
Shows the processing field No.
0 : Missing synchronization in slave mode.
1 : Synchronization was achieved.
0 : Wait for the appointed video line to encode.
1 : Ready for the C.C. data input to the register.
0 : Wait for the appointed video line to encode.
1 : Ready for the C.C. data input to the register.
Reserved
• Status Register becomes effective when SYNC bit turns to “1”.
When in master mode operation, this bit is ”1”.
• STS2-STS2 holds the field number of processing.
acquisition.
Some time lag is inevitable for theI2C
• Closed caption data should be renewed after firm that the EN* flag is “1”.
EN* flag bit is cleared after the second byte( Sub address 17H,19H) was accessed.
• Reserved-bit is always value 0.
Rev.00
- 43 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Device ID Register (R/W) [Address 0x25]
Sub Address 0x25
default Value 0x14
bit 7
DEV7
Bit 6
DEV6
bit 5
DEV5
0
0
0
bit 4
bit 3
DEV4
DEV3
Default Value
1
0
bit 2
DEV2
bit 1
DEV1
bit 0
DEV0
1
0
0
Device ID Register Definition
BIT
Register
Name
bit 0
~
bit 7
DEV0
~
DEV7
R/W
Definition
Shows the Device ID.
Device ID bit
“0x13” is assigned for AK8813.
R
“0x14” is assigned for AK8814.
Revision ID Register (R/W) [Address 0x26]
Sub Address 0x26
default Value 0x00
bit 7
REV7
Bit 6
REV6
bit 5
REV5
0
0
0
bit 4
bit 3
REV4
REV3
Default Value
0
0
bit 2
REV2
bit 1
REV1
bit 0
REV0
0
0
0
Revision ID Register Definition
BIT
Register
Name
bit 0
~
bit 7
REV0
~
REV7
Rev.00
R/W
Definition
This value will be modified when the control software
Revision ID bit
R
has to be modified.
Shows the Revision ID.
- 44 -
2004/Oct
ASAHIKASEI
[AK8813/14]
SYSTEM CONNECTION EXAMPLE
Amp + LPF
COMPOSITE D0 - D7
MPEG
Y C -
SYSCLK
220Ω
75Ω
Decoder
FID/ VSYNC
VREFOUT
HSYNC
I C Bus
0.1uF
AK8813/14
SDA
2
VREFIN
SCL
Digital 3.3V
10uF
IREF
DVDD
DVSS
0.1uF
AVSS
6.8kΩ
AVDD
0.1uF
Analog 3.3V
10uF
Digital GND
Rev.00
10uF
- 45 -
Analog GND
2004/Oct
ASAHIKASEI
[AK8813/14]
PACKAGE
48pin LQFP
1.70 Max
9.0 ± 0.2
1.4 TYP
7.0
9.0 ± 0.2
0.13 ± 0.13
48
1
0.5
0.22 ± 0.08
0.17 ± 0.08
0.10
M
0°∼10°
Units = mm
0.5 ± 0.2
0.10
Package & Lead frame material
Package molding compound :
Epoxy
Lead frame material :
Cu
Lead frame surface treatment :
Rev.00
- 46 -
Solder plate
2004/Oct
ASAHIKASEI
[AK8813/14]
57Pin FBGA
5.0 ± 0.1
A
57 − Φ0.3 ± 0.05
Φ0.05 M S AB
9 8 7 6
5 4 3 2 1
B
F
G
H
J
4.0
5.0 ± 0.1
A
B
C
D
E
0.5
4.0 = 0.5×8
0.5
0.20 S
S
SEATING PLANE
1.00MAX
0.25 ± 0.05
0.08 S
Package & Lead frame material
Package molding compound:
Interposer material:
Rev.00
Epoxy
BT resin
- 47 -
2004/Oct
ASAHIKASEI
[AK8813/14]
48pin LQFP (Pb Free Package)
1) Asahi Kasei Logo
2) Marketing Code : AK8813
3) Date Code : XXXXXXX (7 digits)
4) Pin #1 indication
AK8813VQ
Rev.00
- 48 -
2004/Oct
ASAHIKASEI
[AK8813/14]
57Pin FBGA
1) Pin #1 indication
2) Marketing Code : 8813
3) Date Code : YWWL (4 digits)
8813
YWWL
Y: Year
WW: week
L: Lot
57Pin FBGA (Pb Free Package)
1) Pin #1 indication
2) Marketing Code : 8813P
3) Date Code : YWWL (4 digits)
8813P
YWWL
Rev.00
Y: Year
WW: week
L: Lot
- 49 -
2004/Oct
ASAHIKASEI
[AK8813/14]
48pin LQFP (Pb Free Package)
1) Asahi Kasei Logo
2) Marketing Code : AK8814
3) Date Code : XXXXXXX (7 digits)
4) Pin #1 indication
AK8814VQ
Rev.00
- 50 -
2004/Oct
ASAHIKASEI
[AK8813/14]
57Pin FBGA (Pb Free Package)
1) Pin #1 indication
2) Marketing Code : 8814
3) Date Code : YWWL (4 digits)
8814
YWWL
Rev.00
Y: Year
WW: week
L: Lot
- 51 -
2004/Oct
ASAHIKASEI
[AK8813/14]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or
use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency
exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or
other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with
the express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, unclear energy, or other fields, in which its failure
to function or perform may reasonably be expected to result in loss of life or in significant injury or
damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise
places the product with a third party to notify that party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any
and all claims arising from the use of said product in the absence of such notification.
Rev.00
- 52 -
2004/Oct