SONY CXD1915R

CXD1915R
Digital Video Encoder
Description
The CXD1915R is a digital video encoder designed
for DVDs, set top boxes, digital VCRs and other
digital video equipment. This device accepts ITUR601 format Y, Cb and Cr data and ITU-R656 format
Y, Cb and Cr data, and the data are encoded to
composite video and separate Y/C video (S-video)
signals and converted to RGB/YUV signals.
Features
• NTSC, PAL, MPAL and 4.43NTSC encoding modes
• Composite video and separate Y/C video (S-video)
signal output
• R, G, B/Y, U, V (BetaCam/SMPTE level) signal
output
• 8/16-bit pixel data input modes
• 13.5Mpps pixel rate
• 12.27 and 14.75Mpps square pixel rates
• External synchronization using HSYNC, VSYNC
and FID inputs, or internal synchronization
• Supports interlace and non-interlace modes
• On-chip 100% color bar generator
• OSD function
• ITU-R656 code signal EAV decoding
• Supports I2C bus (400kHz) and Sony SIO
• Closed Caption (line 21, line 284) encoding
• VBID encoding
• WSS encoding
• 10-bit 6-channel DAC
• Macrovision Pay-Per-View copy protection system
Rev. 7.1.L1∗1
• Monolithic CMOS single 3.3V power supply
• 80-pin plastic LQFP
80 pin LQFP (Plastic)
Absolute Maximum Ratings
• Supply voltage
VDD
VSS – 0.5 to +4.6
V
• Input voltage
VI
VSS – 0.5 to +7.0
V
• Output voltage
VO VSS – 0.5 to VDD + 0.5 V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +150
°C
(VSS = 0V)
Recommended Operating Conditions
• Supply voltage
VDD
3.3 ± 0.3
• Input voltage
VIN
VSS to 5.5
• Operating temperature
Topr
0 to +70
°C
I/O Capacitance
• Input capacitance CI
• Output capacitance CO
pF
pF
9 (Max.)
11 (Max.)
V
V
Note) Test conditions: VDD = VI = 0V, fM = 1MHz
∗1 This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of
the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial home use only. Reverse
engineering or disassembly is prohibited.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99422-PS
32 to 35,
37 to 40
PD8 to 15
–2–
2
XVRST
3
4
5
6
8
14
10
XIICEN
XCS/SA
SI/SDA
SO
SCK/SCL
PDCLK
SYSCLK
SYNCM 72
1
F1
BF 20
CSYNC 19
HSYNC 18
VSYNC 17
FID 16
OSDSW 67
BOSD 70
GOSD 69
ROSD 68
XRST 12
PIXCON 73
22 to 25,
27 to 30
PD0 to 7
Block Diagram
1/2
Selector
CSYNC
BURST FLAG
Y, U, V
Y, U, V
Internal CLK
I2C Bus
and
SIO Controller
SYNC Gen.
and
Timing Controller
OSD
Gen.
Demultiplex,
Level
translator
and
Interpolator
4:2:2 to 4:4:4
V
U
Y
VBID & WSS
Gen.
MACRO VISION
Signal Gen.
Closed Caption Encoder
(for NTSC)
Sub Carrier
Gen.
LPF
LPF
Delay
Modulator
YUV/RGB
translator
SYNC Slope
Gen.
CROMA
Interpolater
Interpolater
G/Y-OUT
R/V-OUT
TRST
79
71 XTEST5
66 XTEST
62 to 64 TD8 to 10
61 TVSYNC
TCK
78
TDO
TMS
76
77
TDI
VB
VREF
IREF
VG
75
49
44
43
50
48 C-OUT
10bit
DAC
Y-OUT
CP-OUT
51
45
54 B/U-OUT
56
59
10bit
DAC
10bit
DAC
10bit
DAC
10bit
DAC
10bit
DAC
CXD1915R
CXD1915R
Pin Description
Pin
No.
Symbol
I/O
Description
F1
I
Field ID input.
This signal indicates the field ID when resetting the vertical sync.
High indicates 1st field.
Low indicates 2nd field.
2
XVRST
I
Vertical sync reset input in active Low. This pin is pulled up. This is used for
synchronizing the phases of the external and internal vertical sync signals. When
XVRST = Low, the internal digital sync generator is reset according to the F1 status.
3
XIICEN
I
Serial interface mode select input. This pin is pulled up.
When XIICEN = Low, Pins 4, 5, 6 and 8 are I2C bus mode.
When XIICEN = High, Pins 4, 5, 6 and 8 are Sony SIO mode.
This pin's function is selected by XIICEN (Pin 3). This pin is pulled up.
When XIICEN = High, this pin is Sony SIO mode; XCS chip select input.
When XIICEN = Low, this pin is I2C bus mode; SA slave address select input
signal which selects the I2C bus slave address.
1
4
XCS/SA
I
5
SI/SDA
I/O
This pin's function is selected by XIICEN (Pin 3).
When XIICEN = High, this pin is Sony SIO mode; SI serial data input.
When XIICEN = Low, this pin is I2C bus mode; SDA input/output.
6
SO
O
This pin's function is selected by XIICEN (Pin 3).
When XIICEN = High, this pin is Sony SIO mode; SO serial output.
When XIICEN = Low, this pin is not used and output is high impedance.
7
VSS1
—
Digital ground.
I
This pin's function is selected by XIICEN (Pin 3).
When XIICEN = High, this pin is Sony SIO mode; SCK serial clock input.
When XIICEN = Low, this pin is I2C bus mode; SCL input.
8
SCK/SCL
9
VSS2
10
SYSCLK
11
VSS3
—
12
XRST
I
13
VSS4
—
Digital ground.
14
PDCLK
O
Pixel data clock signal output for 13.5MHz.
A 13.5MHz signal frequency divided from the system clock (SYSCLK) is output
and used as the clock signal when 16-bit pixel data is input.
15
VDD1
—
Digital power supply.
I/O
Field ID input/output.
When SYNCM (Pin 72) = High, the CXD1915R is set to master mode and outputs
as follows.
When control register bit "FIDS" = "1":
Low indicates 1st field and High indicates 2nd field.
When control register bit "FIDS" = "0":
High indicates 1st field and Low indicates 2nd field.
When SYNCM (Pin 72) = Low, the CXD1915R is set to slave mode and this pin
becomes the field ID input.
16
FID
—
I
Digital ground.
System clock input.
To generate the correct subcarrier frequency, precise 27MHz is required.
Digital ground.
System reset input in active Low.
Set to Low for 40 clocks (SYSCLK) or more during power-on reset.
–3–
CXD1915R
Pin
No.
17
Symbol
VSYNC
I/O
Description
I/O
Vertical sync signal input/output.
When SYNCM (Pin 72) = High, this pin is the vertical sync signal output.
When SYNCM = Low, this pin is the vertical sync signal input, and the falling
edge is detected during the 1st field to reset the internal circuits.
18
HSYNC
I/O
Horizontal sync signal input/output.
When SYNCM (Pin 72) = High, this pin is the horizontal sync signal output.
When SYNCM = Low, this pin is the horizontal sync signal input, and the falling
edge is detected during the 1st field to reset the internal circuits.
19
CSYNC
O
Composite sync output when using RGB output.
20
BF
O
Burst flag output. The burst flag is synchronized with the composite video signal
(CP-OUT) and indicates its color burst signal position.
21
VSS5
—
Digital ground.
22
PD0
I
23
PD1
I
24
PD2
I
25
PD3
I
26
VDD2
—
27
PD4
I
28
PD5
I
29
PD6
I
30
PD7
I
31
VSS6
—
Digital ground.
32
PD8/TD0
I/O
33
PD9/TD1
I/O
34
PD10/TD2
I/O
35
PD11/TD3
I/O
Upper 8-bit pixel data inputs when 16-bit pixel data is input/test data bus. [PD8 to PD15]
When control register bit "PIF MODE" = "0", these inputs are not used. When control
register bit "PIF MODE" = "1", these are multiplexed Cb and Cr signal inputs.
In test mode, these are used for the internal circuit test data bus. The test data
bus is available only for the device vendor.
36
VSS7
—
Digital ground.
37
PD12/TD4
I/O
38
PD13/TD5
I/O
39
PD14/TD6
I/O
40
PD15/TD7
I/O
Upper 8-bit pixel data inputs when 16-bit pixel data is input/test data bus. [PD8 to PD15]
When control register bit "PIF MODE" = "0", these inputs are not used. When control
register bit "PIF MODE" = "1", these are multiplexed Cb and Cr signal inputs.
In test mode, these are used for the internal circuit test data bus. The test data
bus is available only for the device vendor.
41
VDD3
—
Digital power supply.
42
NC
—
Not connected inside the IC.
43
IREF
O
DAC reference current output.
Connect resistance "16R" which is 16 times output resistance "R".
44
VREF
I
DAC reference voltage input.
Sets the DAC output full-scale width.
45
CP-OUT
O
10-bit DAC output. This pin outputs the composite signal.
8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is
input. [PD0 to PD7]
When control register bit "PIF MODE" = "0", these are multiplexed Y, Cb, and Cr
signal inputs. When control register bit "PIF MODE" = "1", these are Y signal
inputs.
Digital power supply.
8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is
input. [PD0 to PD7]
When control register bit "PIF MODE" = "0", these are multiplexed Y, Cb, and Cr
signal inputs. When control register bit "PIF MODE" = "1", these are Y signal
inputs.
–4–
CXD1915R
Pin
No.
Symbol
I/O
Description
46
AVDD1
—
Analog power supply.
47
AVSS1
—
Analog ground.
48
C-OUT
O
10-bit DAC output. This pin outputs the chroma (C) signal.
49
VB
O
Connect to ground via a capacitor of approximately 0.1µF.
50
VG
O
Connect to analog power supply via a capacitor of approximately 0.1µF.
51
Y-OUT
O
10-bit DAC output. This pin outputs the luminance (Y) signal.
52
AVDD2
—
Analog power supply.
53
AVSS2
—
Analog ground.
54
B-OUT
O
10-bit DAC output. This pin outputs the B and U signals.
55
AVSS4
—
Analog ground.
56
G-OUT
O
10-bit DAC output. This pin outputs the G and Y signals.
57
AVDD3
—
Analog power supply.
58
AVSS3
—
Analog ground.
59
R-OUT
O
10-bit DAC output. This pin outputs the R and V signals.
60
VSS8
—
Digital ground.
61
TVSYNC
62
TD8
I/O
63
TD9
I/O
64
TD10
I/O
65
VDD4
—
66
XTEST
I
67
OSDSW/
XTEST1
I
68
ROSD/
XTEST2
I
69
GOSD/
XTEST3
I
70
BOSD/
XTEST4
I
71
XTEST5
I
Test pin. This pin is pulled up. Normally this pin should be open.
72
SYNCM
I
Master/slave switching. This pin is pulled up.
When SYNCM = High, the CXD1915R is set to master mode.
When SYNCM = Low, the CXD1915R is set to slave mode.
73
PIXCON
I
Control register bit "PIX_EN" default value control.
This pin is pulled up.
74
VSS9
—
75
TDI
I
I
Test pin. This pin is pulled up. Normally this pin should be open.
Test data inputs/outputs. These pins should be open.
In test mode, these are used for the internal circuit test data bus.
The test data bus is available only for the device vendor.
Digital power supply.
Test mode control. This pin is pulled up.
Normally this pin should be open.
These pins are pulled up. The functions of these pins are selected by XTEST
(Pin 66).
When XTEST = High, these are OSD data inputs.
When XTEST = Low, these are test mode control inputs.
The test mode is available only for the device vendor.
Digital ground.
Test mode control input. This pin is pulled up.
–5–
CXD1915R
Pin
No.
Symbol
I/O
Description
76
TMS
I
Test mode control input. This pin is pulled up.
77
TDO
O
Test output. This pin should be open.
78
TCK
I
Test mode control input. Fix to High.
79
TRST
I
Test mode reset input. Set to Low for 40 clocks (SYSCLK) or more during poweron reset.
80
VDD5
—
Digital power supply.
–6–
CXD1915R
Electrical Characteristics
DC Characteristics
Item
(Ta = 0 to +70°C, VSS = 0V)
Symbol
Measurement
conditions
Max.
Unit
Measurement pins
0.7VDD
∗8
V
∗1
V
∗1
0.7VDD
0.2VDD
∗8
V
∗2
0.3VDD
V
∗2
V
∗3
V
∗3
V
∗4
V
∗4
V
∗5
0.4
V
∗5
–40
µA
∗6
40
µA
∗7
35∗9
mA
Min.
Input High voltage
VIH1
VDD = 3.3 ± 0.3V
Input Low voltage
VIL1
VDD = 3.3 ± 0.3V
Input High voltage
VIH2
VDD = 3.3 ± 0.3V
Input Low voltage
VIL2
VDD = 3.3 ± 0.3V
Output High voltage
VOH1
IOH = –8.0mA
VDD = 3.3 ± 0.3V
Output Low voltage
VOL1
IOL = 8.0mA
VDD = 3.3 ± 0.3V
Output High voltage
VOH2
IOH = –4.0mA
VDD = 3.3 ± 0.3V
Output Low voltage
VOL2
IOL = 4.0mA
VDD = 3.3 ± 0.3V
Output High voltage
VOH3
IOH = –2.0mA
VDD = 3.3 ± 0.3V
Output Low voltage
VOL3
IOL = 4.0mA
VDD = 3.3 ± 0.3V
Input leak current
IIL1
VI = 0V
VDD = 3.3 ± 0.3V
–240
Input leak current
II2
VI = 0 to 5.5V
VDD = 3.3 ± 0.3V
–40
Supply current
IDD
VDD = 3.3 ± 0.3V
Typ.
VDD – 0.4
0.4
VDD – 0.4
0.4
2.4
–100
Notes:
∗1 F1, XVRST, XIICEN, XCS/SA, SYSCLK, XRST, FID, VSYNC, HSYNC, PD0 to PD15, TVSYNC,
TD8 to TD10, XTEST, OSDSW, ROSD, GOSD, BOSD, XTEST5, SYNCM, PIXCON, TDI, TMS, TCK, TRST
∗2 SI/SDA, SCK/SCL
∗3 SO, PDCLK, CSYNC, BF
∗4 TDO
∗5 FID, VSYNC, HSYNC, TD0 to TD10
∗6 XVRST, XIICEN, XCS, TVSYNC, XTEST, OSDSW, ROSD, GOSD, BOSD, XTEST5, SYNCM, PIXCON,
TDI, TMS
∗7 F1, SI/SDA, SCK/SCL, SYSCLK, XRST, FID, VSYNC, HSYNC, PD0 to PD15, TD8 to TD10, TCK, TRST
∗8 The CXD1915R supports input from 5V devices.
∗9 Not including analog current
–7–
CXD1915R
DAC Characteristics
Item
(AVDD = 3.3V, R = 200Ω, VREF = 1.35V, Ta = 25°C)
Symbol
Measurement conditions
Min.
Typ.
Max.
10
Unit
Resolution
n
Linearity error
EL
–2.4
2.4
LSB
Differential linearity error
ED
–0.9
0.9
LSB
Output full-scale current
IFS
6.25
7.25
mA
Output offset voltage
VOS
2
mV
Output full-scale voltage
VFS
1.20
1.35
1.50
V
Precision guaranteed output
voltage range
VOC
1.20
1.35
1.50
V
–8–
6.75
bit
CXD1915R
AC Characteristics
1. Serial port interface
fSCK
tPWLSCK
tPWHSCK
SCK
tCSS
tCSH
XCS
tSIS
tSIH
SI
tSOD
tSOH
SO
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Symbol
Min.
Typ.
Max.
Unit
3
MHz
SCK clock rate
fSCK
DC
SCK pulse width Low
tPWLSCK
tPWHSCK
tCSS
tCSH
tSIS
tSIH
tSOD∗
tSOH∗
100
ns
100
ns
150
ns
150
ns
50
ns
10
ns
SCK pulse width High
Chip select setup time to SCK
Chip select hold time to SCK
Serial input setup time to SCK
Serial input hold time to SCK
Serial output delay time from SCK
Serial output hold time from SCK
30
3
ns
ns
∗ CL = 35pF
–9–
CXD1915R
2. F1
SYSCLK
tFS
tFH
F1
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
F1 setup time to SYSCLK
F1 hold time to SYSCLK
Symbol
Min.
tFS
tFH
Typ.
Max.
Unit
10
ns
0
ns
3. OSDSW, ROSD, GOSD, BOSD
SYSCLK
tOS
tOH
OSDSW
ROSD
GOSD
BOSD
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
OSD setup time to SYSCLK
OSD hold time to SYSCLK
Symbol
tOS
tOH
– 10 –
Min.
Typ.
Max.
Unit
10
ns
0
ns
CXD1915R
4. SYSCLK, PDCLK, BF, CSYNC, HSYNC, VSYNC, FID
fSYSCLK
tPWHCLK
tPWLCLK
SYSCLK
tPDCLKD
tPDCLKD
PDCLK
tCOD
VSYNC∗1
HSYNC∗1
FID∗1
tCOH
CSYNC
BF
∗1 In master mode
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Symbol
SYSCLK clock rate
fSYSCLK
SYSCLK pulse width Low
tPWLCLK
tPWHCLK
tPDCLKD∗
tCOD∗
tCOH∗
SYSCLK pulse width High
PDCLK delay time from SYSCLK
Control output delay time from SYSCLK
Control output hold time from SYSCLK
Min.
Typ.
Max.
27
Unit
MHz
11
ns
11
ns
20
ns
26
ns
3
ns
∗ CL = 35pF
5. 8-bit mode
(1) Pixel data interface
SYSCLK
tPDS
tPDH
PD0 to PD7
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Pixel data setup time to SYSCLK
Pixel data hold time to SYSCLK
Symbol
tPDS
tPDH
– 11 –
Min.
Typ.
Max.
Unit
11
ns
0
ns
CXD1915R
(2) XVRST
SYSCLK
tVS
tVH
XVRST
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Symbol
Min.
tVS
tVH
XVRST setup time to SYSCLK
XVRST hold time to SYSCLK
Typ.
Max.
Unit
10
ns
0
ns
(3) HSYNC, VSYNC, FID
SYSCLK
tSYS
tSYH
HSYNC∗1
VSYNC∗1
FID∗1
∗1 In slave mode
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Sync signal setup time to SYSCLK
Sync signal hold time to SYSCLK
Symbol
tSYS
tSYH
– 12 –
Min.
Typ.
Max.
Unit
10
ns
0
ns
CXD1915R
6. 16-bit mode
(1) Pixel data interface
PDCLK
tPDS
tPDH
PD0 to PD15
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Pixel data setup time to PDCLK
Pixel data hold time to PDCLK
Symbol
Min.
tPDS
tPDH
Typ.
Max.
Unit
23
ns
0
ns
(2) XVRST
PDCLK
tVS
tVH
XVRST
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
XVRST setup time to PDCLK
XVRST hold time to PDCLK
Symbol
tVS
tVH
– 13 –
Min.
Typ.
Max.
Unit
20
ns
0
ns
CXD1915R
(3) HSYNC, VSYNC, FID
PDCLK
tSYS
tSYH
HSYNC∗1
VSYNC∗1
FID∗1
∗1 In slave mode
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Sync signal setup time to PDCLK
Sync signal hold time to PDCLK
Symbol
tSYS
tSYH
– 14 –
Min.
Typ.
Max.
Unit
20
ns
0
ns
CXD1915R
Description of Functions
The CXD1915R converts digital parallel data (ITU-R601 Y, Cb, Cr) into analog TV signals in NTSC (RS170A)
or PAL (ITU-R624; B, G, H, I) format.
The CXD1915R first receives image data in 8-bit parallel form (multiplexed Y, Cb, and Cr data), or in 16-bit
parallel form (8-bit Y and 8-bit multiplexed Cb and Cr data). After demultiplexing, it converts the Cb and Cr
signals into the U and V signals, respectively, interpolates 4:2:2 to 4:4:4, and then modulates the signals with
the digital subcarrier inside the CXD1915R to create the chroma (C) signal.
The Y and chroma (C) signals are oversampled at double speed to reduce SIN (X)/(X) roll-off, and then added
to become the digital composite signal.
The 10-bit DAC converts the digital composite, Y/C, U, V, and RGB signals into analog signals.
1. Pixel input format
The pixel input format is selected according to the value of bit 4 (PIF MODE) of control register address 01H as
shown in Table 1-1 below.
When "PIF MODE" is "0", the image data (multiplexed Y, Cb, and Cr data) input from PD0 to PD7 are sampled
at the rising edge of SYSCLK as shown in the chart on the following page. When "PIF MODE" is "1", the image
data (PD0 to PD7: Y data, PD8 to PD15: multiplexed Cb and Cr data) input from PD0 to PD15 are sampled at
the rising edge of PDCLK.
PIF Mode
PD15 to 8
PD7 to 0
0 (8 bit mode)
NA
Y/Cb/Cr
1 (16 bit mode)
Cb/Cr
Y
Table 1-1
Also, the pixel input data timing is determined according to bits 3 and 2 (PIX TIM) of control register address
01H as shown in Table 1-2 below.
When "PIF MODE" is "0", Cb0 of the image data (Cb0, Y0, Cr0 and Y1) input from PD0 to PD7 is sampled at
the respective rising edge of SYSCLK after the fall of HSYNC.
(Default: Cb0 is sampled at the rising edge of the second SYSCLK after the fall of HSYNC.)
When "PIF MODE" is "1", Y0 and Y1 data are input to PD0 to PD7, multiplexed Cb0 and Cr0 data are input to
PD8 to PD15, and Y0 and Cb0 are sampled at the respective rising edge of PDCLK after the fall of HSYNC.
(Default: Y0 and Cb0 are sampled at the rising edge of the second PDCLK after the fall of HSYNC.)
PIX TIM
Timing phase
0
0
#0 (default)
0
1
#1
1
0
#2
1
1
#3
Table 1-2
– 15 –
CXD1915R
Pixel Data Input Timing
1
2
3
4
5
SYSCLK
1
3
2
PDCLK
HSYNC
[16-bit mode]
PD0 to PD7
Y0
Y1
Y2
Y3
Y4
Y5
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
Y0
Y1
Y2
Y3
Y4
Cb0
Cr0
Cb2
Cr2
Cb4
#0 #1
PD8 to PD15
#2 #3
[8-bit mode]
PD0 to PD7
Cb0
#0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
Cr4
Y5
Cb6
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
Cr4
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
Cr4
Y5
#1
#2
Cb0
#3
PD0
PD1
:
PD7
Pixel data 0 (LSB)
Pixel data 1
:
Pixel data 7 (MSB)
PD8
PD9
:
PD15
– 16 –
Pixel data 0 (LSB)
Pixel data 1
:
Pixel data 7 (MSB)
CXD1915R
2. Serial interface
The CXD1915R supports both the I2C bus (high-speed mode) and Sony serial interface modes. These modes
can be selected by the XIICEN input pin as shown in Table 2-1 below.
XIICEN
H
L
I2C
SONY SIO Mode
SI/SDA
Mode
SI
SDA
SCK/SCL
SCK
SCL
XCS/SA
XCS
SA
SO
High-Z
SO
Table 2-1
2-1. I2C bus interface
The CXD1915R becomes an I2C bus slave transceiver, and supports the 7-bit slave address and the highspeed mode (400K bits/s).
2-1-1 Slave address
Two kinds of slave address (88H, 8CH) can be selected by the SA signal as shown in Table 2-2 below.
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
0
1
SA
0
X
Table 2-2
2-1-2. Write cycle
S
Slave address
W
A
start address
A
A
write data
write data
A
P
"0"
from master to slave
from slave to master
D7
D6
D5
D4
start address
D3
D2
D1
D0
ADR[4:0]
After the slave address is supplied from the master, the data in the next transfer cycle is set up inside the start
address register of this IC as the start address of the control register. In subsequent cycles, the data supplied
from the master is written in the addresses indicated by the control register address. The set control register
address is automatically incremented with the transfer completion of each byte of data.
– 17 –
CXD1915R
2-1-3. Read cycle
S
Slave address
R
A
read address
A
read data
A
P
"1"
from master to slave
from slave to master
After the slave address is supplied from the master, subsequent cycles change immediately to read cycles and
only the ID code (address 0CH, 0DH) is read out. During the read cycle, the start address is automatically set
to 0CH.
Note: In Sony SIO mode, addresses from 00H to 0DH can be read out.
2-1-4. Handling of general call address (00H)
The general call address is ignored and there is no ACK response.
– 18 –
CXD1915R
2-2. Sony serial interface
The Sony serial interface uses the SCK, XCS, SI and SO signals.
The serial interface is active when the XCS signal is Low and transmits and receives signals to and from the
host.
The first byte after the XCS signal becomes Low is set up as a serial control command. Its data includes a
control register address and read/write mode information for the interface. (See 2-2-1. Serial control command
format.)
The control register address is automatically incremented with the transfer completion of each byte of data. In
write mode, the SI signal of the serial input data is sampled at the rising edge of the SCK signal. In read mode,
the register value is read out as the SO signal of the serial output data at the falling edge of the SCK signal,
and is variable. In this case, the SI signal of the serial input data is ignored.
Serial Interface Timing
SCK
XCS
SI
D0
LSB
D1
D2
D3
D4
D5
D6
Serial Control Command
D7
D0
MSB
LSB
SO
D0
D1
D2
D3
D4
D5
D6
Serial Data
D1
D2
D3
D4
D7
MSB
D5
D6
D7
Serial Interface Sequence
SCK
XCS
SI
00H
Internal address
Control register
address set
Control Register Address
00H
01H
02H
FFH
11H
CEH
00H
01H
02H
Control register address
auto-increment
Control register address
auto-increment
Control Register Data
FFH
11H
CEH
2-2-1. Serial control command format
D7
D6
D5
D4
D3
WR
D2
D1
D0
ADR[4:0]
WR:
Read/write mode
When this bit is "1":
The serial interface is write mode, and the SI signal of the serial input data is written in the
register.
When this bit is "0":
The serial interface is read mode, and the register value is read out as the SO signal of the
serial output data.
ADR[4:0]: Control register address setting (Initial value of the address)
– 19 –
CXD1915R
3. XVRST, F1
The XVRST and F1 signals are used to synchronize with the external V sync.
The XVRST and F1 signals are sampled at the rising edge of SYSCLK, and the F1 signal is sampled when
XVRST is Low. When F1 is High, the internal sync generator is reset to the 1st field, and when F1 is Low, it is
reset to the 2nd field. When XVRST is set to High, the digital sync generator starts operation, and the
sequence of the 1st or 2nd field starts.
[8-bit mode]
XVRST Timing (1st Field)
SYSCLK
XVRST
F1 “H”
VSYNC
Start of 1st field (NTSC: 4H)
(PAL: 1H)
FID
HSYNC
XVRST Timing (2nd Field)
SYSCLK
XVRST
F1 “L”
VSYNC
Start of 2nd field (NTSC: 266H)
(PAL: 313H)
FID
1/2H
HSYNC
– 20 –
CXD1915R
[16-bit mode]
XVRST Timing (1st Field)
PDCLK
XVRST
F1 “H”
VSYNC
Start of 1st field (NTSC: 4H)
(PAL: 1H)
FID
HSYNC
XVRST Timing (2nd Field)
PDCLK
XVRST
F1 “L”
VSYNC
Start of 2nd field (NTSC: 266H)
(PAL: 313H)
FID
1/2H
HSYNC
– 21 –
CXD1915R
4. External synchronization
The CXD1915R can select master or slave operation using the SYNCM input pin.
When the SYNCM signal is Low, the CXD1915R is set to slave mode, and synchronizes to an external source
using the HSYNC, VSYNC and FID I/O pin inputs.
The signal combinations used for external synchronization are set by bit 7 (SSEL) of control register 03H.
Register setting
HSYNC
VSYNC
FID
1
Used
Ignored
Used
0 (default)
Used
Used
Ignored
4-1. V synchronization
4-1-1. When SSEL = 0 (default), the CXD1915R identifies the data as the 1st field when the falling edges of
the HSYNC and VSYNC signals match, or as the 2nd field when the falling edges do not match. The
CXD1915R performs synchronization reset only during the 1st field.
VSYNC
HSYNC
CPSYNC
4-1-2. When SSEL = 1, operation is reset to the 1st field at the falling edge of the FID signal. In this case, set
bit 7 (FIDS) of control register 00H to High (default).
FID
HSYNC
CPSYNC
4-2. H synchronization
The horizontal line is reset by detecting the falling edge of the HSYNC signal.
Be sure to perform reset at the precise period.
– 22 –
CXD1915R
5. Closed caption
The CXD1915R supports closed caption encoding.
ASCII data for closed captions are encoded in line 21 and line 284 by adding a parity bit to every ASCII data
set up in control registers 04H, 05H (data #1 and #2 for line 21) and 06H, 07H (data #1 and #2 for line 284).
The control registers (04H to 07H) are double-buffered and ASCII data, which are set up by the serial
interface, are synchronized with the VSYNC signal.
Automatic reset on/off can be selected for ASCII data which has been synchronized with VSYNC by changing
the setting of bit 5 (CCRST) of control register address 03H.
When CCRST = "1", the control registers (04H, 05H or 06H, 07H) are automatically reset in sync with the rise
of the next VSYNC.
When CCRST = "0" (default), the control registers (04H, 05H or 06H, 07H) are not reset, and the data set last
is held.
Closed Caption Data Renewal Timing
When CCRST = "1"
Field
Field 1
Field 4
VSYNC
Control registers 04H and 05H set
SI/SDA
NEW DATA
Data 21H
Front-end buffer
OLD DATA
Data 21H
Rear-end buffer
Data 284H
Front-end buffer
NEW DATA
OLD DATA
DATA A
(7'h00)
NEW DATA
DATA RESET (7'h00)
Data 284H
Rear-end buffer
DATA A
(7'h00)
Field
Field 1
Field 2
VSYNC
Control registers 06H and 07H set
SI/SDA
NEW DATA
Data 284H
Front-end buffer
OLD DATA
Data 284H
Rear-end buffer
Data 21H
Front-end buffer
Data 21H
Rear-end buffer
NEW DATA
OLD DATA
DATA A
(7'h00)
NEW DATA
DATA RESET (7'h00)
DATA A
– 23 –
(7'h00)
CXD1915R
When CCRST = "0"
Field
Field 1
Field 4
VSYNC
Control registers 04H and 05H set
SI/SDA
NEW DATA
Data 21H
Front-end buffer
OLD DATA
NEW DATA
Data 21H
Rear-end buffer
OLD DATA
Data 284H
Front-end buffer
DATA A
Data 284H
Rear-end buffer
DATA A
Field
Field 1
NEW DATA
Field 2
VSYNC
Control registers 06H and 07H set
SI/SDA
NEW DATA
Data 284H
Front-end buffer
OLD DATA
NEW DATA
Data 284H
Rear-end buffer
OLD DATA
Data 21H
Front-end buffer
DATA A
Data 21H
Rear-end buffer
DATA A
NEW DATA
Double Buffer for Closed Caption
SI/SDA
VSYNC
04H
Load
ASCII data #1
Closed Caption Signal Waveform
HSYNC
Color
Burst
Clock Run-In
Start Bits
ASCII Data #1
ASCII Data #2
S1 S2 S3 b0 b1 b2 b3 b4 b5 b6 P1 b0 b1 b2 b3 b4 b5 b6 P2
50 IRE
– 24 –
CXD1915R
6. VBID (Video ID)
The CXD1915R supports encoding of Video ID (Provisional Standard EIAJ CPX-1204) to discriminate the
aspect ratio. VBID is 14-bit data as shown in Table 6-1, and becomes 20-bit data with the addition of 6-bit
CRCC. These data are superimposed on lines 20 and 283 during the vertical blanking period of NTSC video
signals and output.
The data setting in Table 6-1 below is done by writing data in control registers (08H and 09H) via the serial
interface. These control registers (08H and 09H) are double-buffered, and the VBID data are renewed in sync
with the VSYNC signal.
bit-No.
Contents
"0"
"1"
A
1
2
3
Transmission aspect ratio
Image display format
Undefined
B
4
5
6
Identification information about video and other signals (audio signals, etc.)
incidental to images which are transmitted simultaneously
Word 0
Full-mode (16:9)
Letter-box
4:3
Normal
Word 1
4-bit width
Identification signal incidental to Word 0
Word 2
4-bit width
Identification signal and information incidental to Word 0
Table 6-1
Double Buffer for VBID
SI
VSYNC
08H
Load
Word 0
VBID Data Renewal Timing
VSYNC
Control register 08H set
SI
NEW DATA
Data #1
OLD DATA
– 25 –
NEW DATA
CXD1915R
VBID Code Allocation
The VBID data are composed of Word 0 = 6 bits (Word 0-A = 3 bits and Word 0-B = 3 bits), Word 1 = 4 bits,
Word 2 = 4 bits, and CRCC = 6 bits.
bit 0 ···
··· bit 20
Data
0-A
0-B
Word 1
4 bits
Word 2
4 bits
CRCC
6 bits
Word 0
6 bits
VBID Signal Waveform
Ref.
bit 1 bit 2 bit 3
···
2.235µs ± 20ns
11.2µs ± 0.6µs
49.1µs ± 0.5µs
1H
– 26 –
bit 20
CXD1915R
7. WSS (Widescreen Signaling)
The CXD1915R supports WSS encoding to discriminate the aspect ratio. WSS is 14-bit data as shown in
Table 7-1. These data are superimposed on line 23 during the vertical blanking period of PAL video signals
and output.
The data setting in Table 7-1 below is done by writing data in control registers (0AH and 0BH) via the serial
interface. These control registers (0AH and 0BH) are double-buffered, and the WSS data are renewed in sync
with the VSYNC signal.
Group 1
Aspect ratio information (4 bits)
b0 to b3
0001
1000
0100
1101
0010
1011
0111
1110
Normal
Letter-box
Letter-box
Letter-box
Letter-box
Letter-box >
Full-mode
Full-mode
Group 2
PAL plus related information (4 bits)
b4 to b7
14:9 Center
14:9 Top
16:9 Center
16:9 Top
16:9 Center
14:9
16:9
bit 4
Camera/Film mode
bits 5 to 7 Reserved
(Color plus)
(Helper)
(BasebandHelper)
∗ b3 is odd parity.
Group 3
Subtitle information (3 bits)
b8 to b10
Bit 8
Bits 9, 10
00
10
01
11
Group 4
Undefined (3 bits)
b11 to b13
TeleText subtitle enable/disable
No subtitle
Subtitle inside screen
Subtitle in black portion
Reserved
Reserved
Table 7-1
Double Buffer for WSS
SI
VSYNC
0AH
Load
Group1, 2
WSS Data Renewal Timing
VSYNC
Control register 0AH set
SI
NEW DATA
Data #1
OLD DATA
– 27 –
NEW DATA
CXD1915R
WSS Signal Waveform
bit 0 bit 1 bit 2
···
649
bit 13
71.4 IRE
RUN Start
-IN Code
256
0 IRE
20
11.03µs
10.67µs
16.59µs
8. RGB/YUV output
The CXD1915R has an RGB/YUV output function. RGB and YUV can be switched by setting bit 2 (RGB_UV)
of control register address 03H.
Also, the UV level can be selected from BetaCam or SMPTE by setting bit 0 (BTCM) of address 03H. During
RGB output, when bit 1 (GSYNC) of control register address 03H is "1", the sync signal is added to the G
signal and output; when bit 1 (GSYNC) is "0", the sync signal is not added.
9. Support of interlace/non-interlace modes
The CXD1915R can be switched to the interlace and non-interlace modes by varying the setting of bit 1
(INTERLS) of control register address 01H. During the non-interlace mode, the 1st field is repeatedly output.
Register setting value
INTERLS
0 (non-interlace)
1 (interlace)
Number of lines/field
NTSC
PAL
262
312
262.5
312.5
– 28 –
CXD1915R
10. Support of NTSC, PAL, MPAL and 4.43NTSC
The CXD1915R can convert to NTSC, PAL, MPAL and 4.43NTSC analog TV signals by setting bits 2, 1 and 0
(ENC MODE) of control register address 00H.
Register setting value
ENC MODE
Encoding mode
Number of
lines/field
Subcarrier line
phase difference
Subcarrier
frequency [MHz]
0
0
0
PAL
625/50
±135°
4.4336 (10 ± 1cycles)
0
0
1
NTSC
525/60
±180°
3.5795 (9 ± 1cycles)
0
1
1
MPAL
525/60
±135°
3.5756 (9 ± 1cycles)
1
0
1
4.43NTSC
525/60
±180°
4.4336
11. OSD
The CXD1915R can be switched to OSD mode by setting bit 6 (OSDEN) of control register address 02H. At
this time, if OSDSW (Pin 67) = 1, the OSD input pin is enabled.
Also, the luminance level can be selected from the four levels of 25%, 50%, 75% and 100% by varying the
setting of bits 5 and 4 (Y_LEV) of control register address 02H. This allows 29-color (7 colors × 4 levels +
black) OSD output. (Up to 8 colors can be displayed at once.)
Color
ROSD (Pin 68)
GOSD (Pin 69)
BOSD (Pin 70)
White
1
1
1
Yellow
1
1
0
Cyan
0
1
1
Green
0
1
0
Magenta
1
0
1
Red
1
0
0
Blue
0
0
1
Black
0
0
0
12. Support of square pixels
The CXD1915R can be switched to support square pixels by setting bit 4 (SQPIX) of control register address
00H.
MPAL and 4.43NTSC cannot be used in square pixel mode.
Register setting value
SQPIX
Mode
0
1
Pixel clock frequency [MHz]
NTSC
PAL
Normal mode
13.5
13.5
Square pixel mode
12.272727
14.75
13. On-chip 100% color bar generator
The CXD1915R can display an ITU_R100% color bar from its internal generator by setting bit 7 (CBAR) of
control register address 02H.
– 29 –
CXD1915R
14. ITU-656EAV decoding
The CXD1915R decodes the EAV of the ITU-656 1st field and performs internal synchronization every 4 fields
for NTSC or every 8 fields for PAL by setting bit 3 (D1 MODE) of control register address 03H.
– 30 –
– 31 –
FID
VSYNC
HSYNC
FID
VSYNC
HSYNC
261
524
262
525
263
1
3
264
265
Fields 2 and 4
2
Pre-equalization
3H
Fields 1 and 3
266
4
267
5
268
Vertical sync
3H
6
Vertical blanking
7
270
8
271
9
Post-equalization
3H
269
Signal Waveform of NTSC Vertical Blanking Period (Interlace mode)
272
10
273
11
274
19
282
20
283
21
284
22
285
23
CXD1915R
– 32 –
Meander
gate
FID
VSYNC
HSYNC
FID
VSYNC
HSYNC
620
308
311
623
310
(3)
622
(4)
309
(1)
(3)
621
(2)
(4)
313
625
312
624
2.5H
1
3
315
Field 4
Field 3
Field 2
Field 1
314
316
Fields 2 and 4
2
2.5H
Fields 1 and 3
Signal Waveform of PAL Vertical Blanking Period (Interlace mode)
4
317
2.5H
5
318
320
(4)
(2)
7
(1)
(3)
319
(2)
6
(3)
8
321
333
20
334
21
335
22
336
23
24
CXD1915R
– 33 –
FID
VSYNC
HSYNC
FID
VSYNC
HSYNC
261
523
2
264
Field 2∗1
263
1
265
3
266
4
267
5
3H
268
6
269
7
270
8
3H
271
9
272
10
273
11
∗1 No differentiation is made between Fields 1 and 2 to facilitate the frame description.
262
524
3H
Field 1∗1
Signal Waveform of NTSC Vertical Blanking Period (Non-interlace mode)
291
19
282
20
283
21
284
22
285
23
CXD1915R
– 34 –
FID
VSYNC
HSYNC
FID
VSYNC
HSYNC
308
620
309
621
311
2H
623
312
624
2
313
314
2.5H
Field 2∗1
1
2.5H
315
3
316
2.5H
4
2.5H
317
5
318
6
319
7
320
8
∗1 No differentiation is made between Fields 1 and 2 to facilitate the frame description.
310
622
2H
Field 1∗1
Signal Waveform of PAL Vertical Blanking Period (Non-interlace mode)
332
20
333
21
334
22
335
23
336
24
CXD1915R
CXD1915R
Sync Signal Timing
0.148µs
2.3µs
29.5µs
0.148µs
27.1µs
4.67µs
1/2H
63.555µs
NTSC Equalizing Pulse and Sync Pulse Signal Waveform
0.296µs
2.37µs
29.63µs
0.296µs
27.3µs
4.67µs
1/2H
64µs
PAL Equalizing Pulse and Sync Pulse Signal Waveform
– 35 –
CXD1915R
Control Register Map
BIT
Function Selection #1
Address
00H
7
6
5
4
3
FIDS
MASK
EN
PIX
EN
SQPIX
SET UP
ENC MODE
Encoding mode
000: PAL encoding mode
001: NTSC encoding mode (Default)
010: Inhibit
011: MPAL encoding mode
100: Inhibit
101: 4.43NTSC encoding mode
110: Inhibit
111: Inhibit
SET UP
Setup enable
0: No setup level, black level = blanking level
1: 7.5 IRE setup level insertion (Default)
SQPIX
Square pixel
0: Disable square pixel mode (13.5MHz) (Default)
1: Enable square pixel mode
PIX EN
Pixel data enable
PIXCON input pin = High
PIXCON input pin = Low
2
0: Disable input pixel data
1: Enable input pixel data (Default)
0: Disable input pixel data (Default)
1: Enable input pixel data
MASK EN
Mask enable
0: Pixel data through during vertical blanking period
1: Pixel data reject during vertical blanking period (Default)
FIDS
FID polarity select
SYNCM input pin = High
0: 1st field High, 2nd field Low
1: 1st field Low, 2nd field High (Default)
SYNCM input pin = Low
Fixed to "1".
– 36 –
1
ENC
MODE
0
R/W
CXD1915R
BIT
Function Selection #2
7
Address
01H
6
5
DAC MODE
4
3
PIF
MODE
2
PIX TIM
1
0
INTERLS
FREE
RUN
R/W
FREERUN
Free running
0: Reset applied every 4 fields during NTSC or every 8 fields during PAL and MPAL (Default)
1: No SCH timing reset
INTERLS
Interlace mode switching
0: Non-interlace mode
1: Interlace mode (Default)
PIX TIM
Pixel input timing
00: #0 (Default)
01: #1
10: #2
11: #3
PIF MODE
Pixel input format
0: 8-bit mode, multiplexed Y, Cb, Cr (4:2:2) (Default)
1: 16-bit mode, Y and multiplexed Cb, Cr (4:2:2)
DAC MODE
DAC output activity
000: Non-active
001: CP-Out active
010: Inhibit
011: Video signal (Y, C, CP) -Out active (Default)
100: Inhibit
101: R, G, B-Out and CP-Out active
110: Inhibit
111: All outputs active
– 37 –
CXD1915R
BIT
Function Selection #3
Address
02H
7
6
CBAR
OSDEN
4
5
Y_LEV
3
2
VBID
WSS
CC MODE
Closed caption encoding mode
00: Disable closed caption encoding (Default)
01: Enable encoding in 1st field (Line 21)
10: Enable encoding in 2nd field (Line 284)
11: Enable encoding in both fields
WSS
WSS encoding enable
0: Disable WSS encoding (Default)
1: Enable WSS encoding
VBID
VBID encoding mode
0: Disable VBID encoding (Default)
1: Enable VBID encoding
Y_LEV
OSD luminance level select
00: 100% (Default)
01: 25%
10: 50%
11: 75%
OSDEN
OSD enable
0: Disable OSD (Default)
1: Enable OSD
CBAR
Color bar enable
0: Disable on-chip color bar output (Default)
1: Enable on-chip color bar output (ITU_R100% color bar)
– 38 –
1
0
CC Mode
R/W
CXD1915R
BIT
Function Selection #4
Address
03H
7
6
5
SSEL
BF
CCRST
4
3
2
1
0
D1
MODE
RGB_UV
GSYNC
BTCM
BTCM
UV output level control
0: SMPTE
1: BetaCam (Default)
GSYNC
G-on SYNC enable
0: Disable (Default)
1: Enable
RGB_UV
RGB/YUV output mode switching
0: YUV (Default)
1: RGB
D1 MODE
ITU-R656 EAV decoding
0: Disable ITU-R656 EAV decoding (Default)
1: Enable ITU-R656 EAV decoding
CCRST
Closed caption character reset enable
0: Disable (Default)
1: Enable
BF
Burst flag enable
0: Disable burst flag
1: Enable burst flag (Default)
SSEL
Sync select
Selects the sync signal used during slave mode.
HSYNC VSYNC
FID
0: Used
Used Ignored (Default)
1: Used
Ignored Used
– 39 –
R/W
CXD1915R
BIT
Closed Caption Character #1 (Line 21H)
7
6
5
Address
04H
4
3
2
ASCII Data #1
1
0
R/W
(Default: 0H)
Closed Caption Character #2 (Line 21H)
7
6
5
Address
05H
4
3
2
ASCII Data #2
1
0
R/W
(Default: 0H)
Closed Caption Character #1 (Line 284H)
7
6
5
Address
06H
4
3
2
1
ASCII Data #1
(Default: 0H)
4
2
0
R/W
Closed Caption Character #2 (Line 284H)
7
6
5
Address
07H
3
ASCII Data #2
1
0
R/W
(Default: 0H)
VBID #1
7
6
5
4
3
2
1
0
Word 0
Address
08H
Word 0-B
R/W
Word 0-A
VBID #2
7
Address
09H
6
5
4
3
Word 2
2
1
0
R/W
Word 1
WSS #1
Address
0AH
7
6
5
4
3
2
1
0
bit 7
Group 2
bit 6
bit 5
bit 4
bit 3
bit 2
Group 1
bit 1
bit 0
7
6
5
4
3
2
1
0
bit 13
Group 4
bit 12
bit 11
bit 10
Group 3
bit 9
bit 8
R/W
WSS #2
Address
0BH
– 40 –
R/W
CXD1915R
BIT
Device ID #1
7
6
5
4
Address
0CH
3
ID Code
ID code
2
1
0
RO
(Lower) 15H
Identification: 15H
Device ID #2
7
Address
0DH
6
5
4
3
ID Code
ID code
Identification: 19H
– 41 –
2
1
(Upper) 19H
0
RO
CXD1915R
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Video Signal Timing (NTSC, 7.5 IRE Setup)
806
806
WHITE LEVEL
748
655
597
100 IRE
506
448
7.5 IRE
355
297
BLACK LEVEL
BLANK LEVEL
256
40 IRE
36
SYNC LEVEL
BLACK
BLUE (±227)
RED (±320)
MAGENTA (±299)
GREEN (±299)
CYAN (±320)
YELLOW (±227)
WHITE
NTSC Y (luminance) signal output waveform
7.5 IRE setup
832
622
20 IRE
512
402
BLANK LEVEL
COLOR BURST
192
NTSC C (chroma) signal output waveform
7.5 IRE setup
– 42 –
CXD1915R
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Video Signal Timing (NTSC, No Setup)
806
806
WHITE LEVEL
744
643
580
100 IRE
482
419
318
BLANK LEVEL
256
40 IRE
36
SYNC LEVEL
BLACK
BLUE (±245)
RED (±347)
MAGENTA (±324)
GREEN (±324)
CYAN (±347)
YELLOW (±245)
WHITE
NTSC Y (luminance) signal output waveform
859
622
20 IRE
512
402
BLANK LEVEL
COLOR BURST
165
NTSC C (chroma) signal output waveform
– 43 –
CXD1915R
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
YELLOW
Video Signal Timing (PAL)
806
806
WHITE LEVEL
744
643
580
100 IRE
482
419
318
BLANK LEVEL
256
43 IRE
20
SYNC LEVEL
BLACK
BLUE (±245)
RED (±347)
MAGENTA (±324)
GREEN (±324)
CYAN (±347)
YELLOW (±245)
WHITE
PAL Y (luminance) signal output waveform
859
630
21.5 IRE
512
394
BLANK LEVEL
COLOR BURST
165
PAL C (chroma) signal output waveform
– 44 –
CXD1915R
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
806
YELLOW
R signal
WHITE
RGB Signal Output Waveform
806
806
257
257
805
805
256
256
WHITE LEVEL
100 IRE
256
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
806
WHITE
G signal
BLANK LEVEL
806
807
806
806
256
256
256
256
WHITE LEVEL
100 IRE
256
BLANK LEVEL
During G-on SYNC (NTSC)
WHITE LEVEL
806
100 IRE
256
BLANK LEVEL
40 IRE
36
SYNC LEVEL
During G-on SYNC (PAL)
WHITE LEVEL
806
100 IRE
256
BLANK LEVEL
43 IRE
20
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
806
WHITE
B signal
SYNC LEVEL
806
257
808
259
803
256
806
256
WHITE LEVEL
100 IRE
256
BLANK LEVEL
– 45 –
CXD1915R
UV Output Level
Color Difference (U) Signal
782
901
690
768
603
643
512
512
421
381
334
256
242
123
NTSC
NTSC, No setup
871
750
633
512
391
274
153
NTSC, Setup
787
787
693
693
605
605
512
512
419
419
331
331
237
237
PAL
PAL
– 46 –
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
BLACK
BLUE
RED
CYAN
GREEN
MAGENTA
Beta Cam LEVEL
YELLOW
WHITE
SMPTE LEVEL
CXD1915R
Color Difference (V) Signal
901
782
738
838
555
574
512
512
450
469
186
286
123
242
NTSC, No setup
NTSC
871
813
570
512
453
211
153
NTSC, Setup
787
787
742
742
556
556
512
512
468
468
282
282
237
237
PAL
PAL
– 47 –
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
YELLOW
Beta Cam LEVEL
SMPTE LEVEL
CXD1915R
Internal Filter Characteristics
Interpolation Filter Characteristic
0
Attenuation [dB]
–10
–20
–30
–40
–50
0
1
2
3
4
5
6
7
9
8
10 11 12 13 14
Frequency [MHz]
Chrominance Filter Characteristic
0
Attenuation [dB]
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
Frequency [MHz]
– 48 –
7
8
9
10
CXD1915R
DAC Application Circuit
CXD1915R
AVDD
VG
0.1µF
1kΩ
VREF
3.2kΩ
IREF
AVSS
CP-OUT
Y-OUT
C-OUT
Buff AMP
LPF
G/Y-OUT
B/U-OUT
R/V-OUT
0.1µF
VB
75Ω
200Ω
VSS
Application Circuit
CXD1915R
(Video encoder)
MPEG decoder
Y
C
8
8
FID
PD0 to PD7
PD8 to PD15
FID
HSYNC
HSYNC
VSYNC
VSYNC
DCLK
13.5MHz
CLK
PDCLK
SYSCLK
27MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 49 –
CXD1915R
Package Outline
Unit: mm
80PIN LQFP (PLASTIC)
14.0 ± 0.2
∗
12.0 ± 0.1
60
41
40
(13.0)
61
21
(0.22)
80
0.5
0.5 ± 0.2
A
1
+ 0.08
0.18 – 0.03
20
0.13 M
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0° to 10°
0.5 ± 0.2
0.1 ± 0.1
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LQFP080-P-1212
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.5g
JEDEC CODE
– 50 –