STV9432TA 100MHz OSD FOR MONITOR INCLUDING BEAM CURRENTS & VIDEO TIMING ANALYZER • MULTIFUNCTION OSD FOR MONITOR • INCLUDES FACILITIES FOR CUT-OFF VOLTAGES MONITORING: - THREE 8 BITS ADC INPUTS - ADC TRIGGER DURING RETRACE TIME OF A PROGRAMMED LINE • INCLUDES FACILITIES FOR SCREEN SIZE & CENTERING AUTO SETUP - HS, VS, VIDEO TIMING MEASUREMENTS • 100MHz MAX. PIXEL CLOCK, AVAILABLE FOR ANY LINE FREQUENCY BETWEEN 15 AND 140 kHz • 12 x 18 CHARACTER ROM FONT INCLUDES: - 240 MONOCOLOR CHARACTERS - 16 MULTICOLOR CHARACTERS • CHARACTER FLASHING • UP TO 1K CHARACTERS TEXT DISPLAY • ULTRA HIGH FREQUENCY PLL FOR JITTERFREE DISPLAY • FLEXIBLE DISPLAY: - ANY CHARACTER WIDTH AND HEIGHT - ANYWHERE IN THE SCREEN • SINGLE BYTE CHARACTER CODES AND COLOR LOOK-UP TABLE FOR EASY PROGRAMMING AND FAST ACCESS • CHARACTER FLIP OPERATIONS • WIDE DISPLAY WINDOW ALLOWS PATTERN GENERATION FOR FACTORY ADJUSTMENTS • I2C BUS MCU INTERFACE DESCRIPTION Connected to a host MCU via a serial I 2C Bus, the STV9432TA is a multifunction slave peripheral device integrating the following blocks: - On-screen Display. It includes a MASK PROGRAMMABLE ROM that holds the CUSTOM CHARACTER FONT, a 1Kbytes RAM that stores the code strings of the different lines of text to be displayed, and a set of registers to program character sizes and colors. A built-in digital PLL, oper- ating at very high frequency, provides an accurate display without visible jitter for a wide line frequency range from 15 to 140 kHz. - Cut-off Monitoring Circuitry includes 3 x 8 bits ADCs and a programmable ADC sampling trigger. It gives the possibility to measure the three beam currents, during the horizontal flyback, at a given line in the frame, provided that the three ADC inputs are connected to a beam current sensing circuitry. The values are stored in three BEAM CURRENT REGISTERS, and available for MCU read. - Video Timing Analyzer. Using the Horizontal Sync, Vertical Sync, Horizontal Flyback, and "Video Active" inputs, a set of counters provide the different timing measurements necessary to analyze the current Video timing characteristics to make the automatic set-up of screen size and centering. The measurements are initialized on the same programmable trigger line than in the above cut-off monitoring circuitry SDIP24 (Plastic Package) ORDER CODE: STV9432TA PIN CONNECTIONS FILTER 1 24 TEST AGND 2 23 ADCREF SDA 3 22 RCI SCL 4 21 GCI HS 5 20 BCI VS 6 19 AVDD HFLY 7 18 OVDD AV 8 17 FBLK DVDD 9 16 BOUT DVS S 10 15 GOUT XTI 11 14 ROUT XTO 12 13 OVS S Rev. 4.0 February 2000 This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice. 1/24 1 STV9432TA 1 - PIN DESCRIPTION 2/24 2 Pin Number Symbol Type 1 FILTER I/O Description 2 AGND Power 3 4 SDA SCL I/O I I2C Bus Serial Data I2C Bus Serial Clock 5 HS I Horizontal Sync Input 6 7 VS HFLY I I Vertical Sync Input Horizontal Flyback Input Active Video Input PLL Filter Analog Ground 8 AV I 9 10 DVDD DVSS Power Digital +5V Power Supply Power Digital Ground 11 XTI I 12 13 XTO OVSS O Power 14 ROUT O Red Output 15 GOUT O Green Output 16 17 BOUT FBLK O O Blue Output Fast Blanking Output 18 OVDD Power +5V Supply for the RGB Outputs 19 20 AVDD BCI Power I Analog +5V Power Supply Blue Beam Current Input 21 GCI I Green Beam Current Input 22 23 RCI ADCREF I I/O Red Beam Current Input ADC Reference Voltage Pin 24 TEST I/O Pin must be connected to ground Crystal Oscillator Input Crystal Oscillator Output Ground for the RGB Outputs STV9432TA 2 - BLOCK DIAGRAM 11 XTI OSCILLATOR 12 XTO TEST 24 18 OVDD FILTER 1 HFLY 7 VS 6 HS 5 AV 8 13 OVSS PLL 14 ROUT DISPLAY CONTROLLER 15 GOUT 16 BOUT 17 FBLK TIMINGS ANALYZER RCI 22 BEAM CURRENT MEASURE GCI 21 BCI 20 1k BYTES RAM CHARACTER FONT ROM I2C BUS INTERFACE ADCREF 23 3 SDA 4 SCL 3.3V AVDD 19 VOLTAGE REGULATOR DVDD 9 POWER-ON RESET 10 DVSS 2 AGND STV9432TA 3 - ABSOLUTE MAXIMUM RATINGS Symbol AVDD, DVDD, OVDD VIN Toper Tstg Parameter Supply Voltage Input Voltage Operating Temperature Storage Temperature Value Unit -0.3, +6.0 V VSS - 0.3, VDD + 0.3 0, +70 V o C -40, +125 o C 3/24 2 STV9432TA 4 - ELECTRICAL CHARACTERISTICS (VDD = 5V, VSS = 0V, GND = 0V, TA = 0 to 70o, unless otherwise specified) Symbol SUPPLY Parameter AVDD, DVDD, OVDD Supply Voltage AIDD + DIDD + OIDD INPUTS (SCL, SDA) Analog and Digital Supply Current VIL Input Low Voltage VIH Input High Voltage VIH Typ. Max. Unit 4.75 5 5.25 V - - 150 mA 0.8 2.4 Input Leakage Current IIL INPUTS (HS, VS, AV, HFLY) VIL Min. -1 Input Low Voltage Input High Voltage HS, VS, AV HFLY VHYST Schmidt Trigger Hysteresis IPU Pull-up Source Current (VIN = 0V) V V +1 µA 0.8 V 2.4 3.6 V 0.4 V 100 µA HSIN Horizontal Synchro Input Range OUTPUTS (SDA open drain) 15 140 kHz VOL 0 0.4 V Output Low Voltage (IOL = 3mA) OUTPUTS (R, G, B, FBLK) VOL Output Low Voltage (IOL = 3mA) Output High Voltage (IOH = 3mA) VOH OSCILLATOR (XTI, XTO) IIL XTI Input Source Current (VIN = 0V) IIH XTI Input Sink Current (VIN = VDD) VIL XTI Input Low Voltage VIH VOL XTI Input High Voltage VOH XTI Output Low Voltage (IOL = 3mA) XTI Output High Voltage (IOH = 3mA) ADCREF VREF Output Voltage Reference 0 0.4 V 0.8VDD VDD V 3 15 µA 3 15 µA 1.4 V 0 0.4 V 0.8VDD VDD V 0.7VDD V 3.3 V 3.6 V POWER-ON RESET Supply Threshold Level DVDDTH 8 BITS ADC INPUTS (RCI GCI BCI) VIN Input Voltage ZIN VOFF Input Impedance ILEAK Input Leakage Current ILE Integral Linearity Error (Note 2) DLE Differential Linearity Error (Note 2) 4/24 2 0 VADCREF Input Offset Voltage 3 0 V kΩ 100 LSB 50 µA -2 +2 LSB -0.5 +0.5 LSB STV9432TA 5 - TIMINGS Symbol Parameter Min. Typ. Max. Unit 100 MHz OSCILLATOR fOSC Clock Frequency fPXL Pixel Frequency 8 R, G, B, FBLK (CLOAD = 30pF) tR Rise Time (see Note 1) MHz 5 ns tF Fall Time (see Note 1) 5 ns tSKEW Skew between R, G, B, FBLK 5 ns I2C INTERFACE: SDA AND SCL (see Figure 1) fSCL SCL Clock Frequency 0 400 kHz tBUF Time the bus must be free between 2 access 500 ns tHDS tSUP Hold Time for Start Condition 500 ns Set up Time for Stop Condition 500 ns tLOW The Low Period of Clock 400 ns tHIGH tHDAT The High Period of Clock 400 ns 0 ns tSUDAT Set up Time Data tF Fall Time of SDA tR Rise Time of both SCL and SDA Hold Time Data 500 ns 20 ns Depend on the pull-up resistor and the load capacitance ANALYZER (HS, HFLY, AV) tHLOW Low Pulse Width (see Note 3) 2 4091 tHTIM tHHIGH High Pulse Width (see Note 3) 2 4091 tHTIM Hs max Max Hs Frequency Hfly ANALYZER (VS) tVLOW tVHIGH Low Pulse Width 2 4091 Lines High Pulse Width 2 4091 Lines Note 1: These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization Note 2 : The ADC measurements are dependant on the noise. The test is done by correlation in order to screen out marginal devices. Note 3 : tHTIM = 3tOSC : 40. Figure 1. STOP START DATA STOP tHDAT tBUF SDA tHDS tSUDAT tSUP SCL tHIGH tLOW 5/24 2 STV9432TA 6 - SERIAL INTERFACE The 2-wires serial interface is an I 2C interface. To be connected to the I2C bus, a device must own its slave address; the slave address of the STV9432TA is BA (in hexadecimal). A6 A5 A4 A3 A2 A1 A0 1 0 1 1 1 0 1 - The two bytes of the internal address where the MCU wants to write data(s), - The successive bytes of data(s). All bytes are sent MSB bit first and the write data transfer is ended with a stop. RW 6.2 - DATA TRANSFER IN READ MODE The host MCU can read data from the STV9432TA registers, RAM or ROM. 6.1 - DATA TRANSFER IN WRITE MODE The host MCU can write data into the STV9432TA registers or RAM. To read data from the STV9432TA (Figure 3), the MCU must send 2 different I2C sequences. The first one includes the I2C slave address byte with R/W bit at low level and the 2 internal address bytes. To write data into the STVA9432TA after a start, the MCU must send (Figure 2): The second one includes the I 2C slave address byte with R/W bit at high level and all the successive data bytes read at successive addresses starting from the initial address given by the first sequence. - First, the I2C address slave byte with a low level for the R/W bit, Figure 2. I2C Write Operation SCL R/W A7 SDA I2 C Start Slave Address A6 A5 ACK A4 A3 A2 A1 A0 LSB Address - - A13 ACK A12 A11 A10 A9 MSB Address A8 ACK SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 Data Byte 1 D7 D6 D5 ACK D4 D3 D2 D1 D0 Data Byte 2 D7 D6 D5 ACK D4 D3 D2 D1 D0 Data Byte n ACK Stop Figure 3. I2C Read Operation SCL R/W SDA A7 Start I2C Slave Address Start I2C Slave Address A6 A5 ACK A4 A3 A2 A1 A0 LSB Address - - ACK A13 A12 A10 A10 A9 A8 MSB Address ACK Stop ACK Stop SCL SDA 6/24 2 D7 R/W ACK * D6 D5 D4 D3 Data Byte 1 D2 D1 D0 D7 ACK D6 D5 D4 D3 Data Byte n D2 D1 D0 STV9432TA 6.3 - ADDRESSING SPACE 6.3.1 - General Mapping STV9432TA registers, RAM and ROM are mapped in a 32K address space. The mapping is: 0000 03FF 0400 07FF 1024 bytes RAM 0800 3FFF Character Generator ROM 4000 403F 4040 7FFF Internal Registers Descriptors and character codes Empty Space Empty Space Important Notice: All 16 bits datas are mapped LSB byte at lower address and MSB byte at higher address. – Example: H1 12 bits register: @4000: 8 LSB bits - @4001: 4 MSB bits. – Descriptors must also be written to RAM LSB byte first. 6.3.2 - I2C Registers Mapping 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 400A 400B 400C 400D 400E 400F 4010 4011 4012 4013 4014 4015 4016 4017-401F 4020 4021 H1 LSB H1 MSB H2 LSB H2 MSB H3 LSB H3 MSB H4 LSB H4 MSB H5 LSB H5 MSB H6 LSB H6 MSB V1 LSB V1 MSB V2 LSB V2 MSB V3 LSB V3 MSB RCI GCI BCI SBN TIMG Reserved Color 0 Color 1 4022 4023 4024 4025 4026 4027 4028 4029 402A 402B 402C 402D 402E 402F 4030 4031 4032 4033 4034 4035 4036 4037 4038-403E 403F 4040-7FFF Color 2 Color 3 Color 4 Color 5 Color 6 Color 7 Color 8 Color 9 Color 10 Color 11 Color 12 Color 13 Color 14 Color 15 Line Duration Top Margin Horizontal Delay Character Height Display Control Locking Time Constant Capture Time Constant Initial Pixel Period Reserved RST Reserved 7/24 STV9432TA 7 - TIMING ANALYZER 7.1 - Video Horizontal Timings All horizontal timing measurements use a 106.7MHz clock. This clock is made from the internal oscillator: fHTIM = 40fOSC : 3. These twelve bits read-only registers read time measurements, given in t HTIM units. They hold the value of the last measurement that was initiated by I2C command (see TIMG Register). Figure 4. AV A HS K B L HFLY E A’ K’ F L’ E’ F’ H1 Register: H sync to Active video, min of C to A 4000 4001 H1.7 - H1.6 - H1.5 - H1.4 - H1.3 H1.11 H1.2 H1.10 H1.1 H1.9 H1.0 H1.8 H2.5 - H2.4 - H2.3 H2.11 H2.2 H2.10 H2.1 H2.9 H2.0 H2.8 H2 Register: Active video to H sync, min of B to C’ 4002 4003 H2.7 - H2.6 - H3 Register: Line period, C to C’ 4004 H3.7 H3.6 H3.5 H3.4 H3.3 H3.2 H3.1 H3.0 4005 - - - - H3.11 H3.10 H3.9 H3.8 H4 Register: H Fly to H sync, E to C 4006 H4.7 H4.6 H4.5 H4.4 H4.3 H4.2 H4.1 H4.0 4007 - - - - H4.11 H4.10 H4.9 H4.8 H5 Register: H sync to H Fly, C to E’ 4008 H5.7 H5.6 H5.5 H5.4 H5.3 H5.2 H5.1 H5.0 4009 - - - - H5.11 H5.10 H5.9 H5.8 H6 Register: H fly pulse, E to F 400A H6.7 H6.6 H6.5 H6.4 H6.3 H6.2 H6.1 H6.0 400B - - - - H6.11 H6.10 H6.9 H6.8 7.2 - Video Vertical Timings These twelve bits read-only registers read time measurements, given in number of scan lines. They hold the value of the last measurement that was initiated by I2C command (see TIMG Register). Figure 5. AV VS 8/24 3 A K L B A’ K’ L’ STV9432TA V1 Register: V sync to Active video, min. of K to A 400C V1.7 V1.6 V1.5 V1.4 V1.3 V1.2 V1.1 V1.0 400D - - - - V1.11 V1.10 V1.9 V1.8 V2 Register: Active video to V sync, min. of B to K’ 400E V2.7 V2.6 V2.5 V2.4 V2.3 V2.2 V2.1 V2.0 400F - - - - V2.11 V2.10 V2.9 V2.8 V3 Register: Number of lines per frame, K to K’7 4010 V3.7 V3.6 V3.5 V3.4 V3.3 V3.2 V3.1 V3.0 4011 - - - - V3.11 V3.10 V3.9 V3.8 7.3 - Timing Analysis Trigger The Timing Analysis is performed according to the setting of SBN and TIMG registers : 7.3.1 - SBN Register This 8 bits register holds the "sampling bloc" number. The sampling bloc is a set of 4 consecutive scan lines, the first of which is used for sampling the video timings or Beam currents. The reset value of this register is zero, must be programmed at a minimum value of 1 for correct operation. 4015 SBN7 SBN6 SBN5 SBN4 SBN3 SBN2 SBN1 SBN0 NFR1 NFR0 ADCDLY3 ADCDLY2 ADCDLY1 0 SELECT 7.3.2 - TIMG Register 4016 STM This 8 bits register holds the following parameters: STM : NFR [1:0] ADCDLY[3:1] SELECT : : : Start Measurement Bit. This bit has to be forced to 1 by I2C to start the measurement sequence, depending on the measurement selection bit. When measurement is completed the IC will reset this bit to 0. NFR number of measurement frames, 1 to 4 frames Cut-off Beam current ADC sampling delay time: 0 to 15 x tOSC, by tOSC steps Selection of Beam current measurement (0) or Timing measurement (1) To initiate a Timing Analysis cycle: - program the Sampling Bloc Number in the SBN Register, - program the TIMG Register, with: "SELECT" bit =1, "NFR" bits specify the number of measurement frames (H1, H2, V1, V2), "STM" bit = 1 (Start Measurement). As soon as the measurement cycle is finished, the "STM" bit is automatically reset by the device. After a Timing Analysis cycle, reading a zero in STM bit of TIMG register means that the measurement is completed and the MCU may read the results in Hi and Vi registers. The reset value of this register is 0. 9/24 3 STV9432TA Figure 6. Video Timing Measurement sequence - “Select bit = 1” (TIMG register, bit 0) I2C SET STM BIT (TIMG register) WAIT FOR ACKNOWLEDGE BIT WAIT FOR RISING EDGE OF VS MEASURES H1 AT EVERY LINE DURING NFR+1 FRAMES. AFTER NFR+1 FRAMES, H1 HOLDS THE MIN.VALUE MEASURES V3 WAIT FOR 4*SBN RISING EDGES OF HS MEASURES V1 DURING NFR+1 AND KEEPS THE MIN. VALUE MEASURES H2 AT EVERY LINE DURING NFR+1 FRAMES. AFTER NFR+1 FRAMES, H2 HOLDS THE MIN.VALUE MEASURES V2 DURING NFR+1 AND KEEPS THE MIN. VALUE AFTER NFR+1 FRAMES, RESET STM BIT 10/24 3 ACQUISITION OF H3, H4, H5, H6 STV9432TA 8 - BEAM CURRENTS MEASUREMENT 8.1 - BEAM CURRENT MEASUREMENT REGISTERS The Beam Current Measurement circuitry uses three A to D converters, sampled at fOSC frequency. These three 8 bits registers read the values of the last Beam currents measurement, initiated by I 2C command (see TIMG register). RCI Register: Red Beam Current Input 4012 RCI7 RCI6 RCI5 RCI4 RCI3 RCI2 RCI1 RCI0 GCI4 GCI3 GCI2 GCI1 GCI0 BCI4 BCI3 BCI2 BCI1 BCI0 GCI Register: Green Beam Current Input 4013 GCI7 GCI6 GCI5 BCI Register: Blue Beam Current Input 4014 BCI7 BCI6 BCI5 8.2 - BEAM CURRENT MEASUREMENT TRIGGER The Beam Currents Measurement is performed according to the setting of SBN and TIMG registers : 8.2.1 - SBN Register This 8 bits register holds the "sampling bloc" number. The sampling bloc is a set of 4 consecutive scan lines, the first of which is used for sampling the video timings or Beam currents. The reset value of this register is 0. 4015 SBN7 SBN6 SBN5 SBN4 SBN3 SBN2 SBN1 SBN0 NFR1 NFR0 ADCDLY3 ADCDLY2 ADCDLY1 0 SELECT 8.2.2 - TIMG Register 4016 STM This 8 bits register holds the following parameters: STM : Start Measurement Bit. This bit has to be forced to 1 by I2C to start the measurement sequence, depending on the measurement selection bit. When measurement is completed the IC will reset this bit to 0. NFR [1:0] : NFR number of measurement frames, 1 to 4 frames ADCDLY [3:1] : Cut-off Beam current ADC sampling delay time: 0 to 14 x tOSC, by tOSC steps SELECT : Selection of Beam current measurement (0) or Timing measurement (1) To initiate a Beam Currents Measurement cycle: - program the Sampling Bloc Number in the SBN Register, - program the TIMG Register, with: "SELECT" bit = 0, "ADCDLY" bits specify the sampling time during HFly, "STM" bit = 1 (Start Measurement). As soon as the measurement cycle is finished, the "STM" bit is automatically reset by the device. After a Beam Currents Measurement cycle, reading a zero in STM bit of TIMG register means that the measurement is completed and the MCU may read the results in RCI, GCI, and BCI registers. The reset value of this register is 0. 11/24 4 STV9432TA Figure 7. Beam Currents Measurement Sequence - “Select bit = 0” (TIMG register, bit 0) I2C SET STM BIT (TIMG register) WAIT FOR ACKNOWLEDGE BIT WAIT FOR RISING EDGE OF VS WAIT FOR 4*SBN RISING EDGES OF HS WAIT FOR RISING EDGE OF HFLY WAIT FOR ADC DLY ACQUISITION OF RBC, GBC, BBC RESET STM BIT 12/24 4 STV9432TA 9 - SOFTWARE RESET REGISTER 403F - - - - - - - RST To perform a software I2C reset of the device, set the RST bit to ONE. This bit will be automatically reset by the device. Software Reset will put all Write registers at their default power-on value, and reset all internal logic blocks except the I2C bus interface itself. It will not change the RAM contents. SELXTAL This bit must be set to ONE in order to operate the oscillator in the external crystal mode. In its ZERO default state, this bit enables the internal RC mode oscillator. 10 - ON-SCREEN DISPLAY The STV9432TA on-screen display is able to display any line of characters (character strip) anywhere in the screen. Character strings are programmed by the MCU in RAM via I2C bus. Character shapes are coded in the internal ROM font. Character strips may be adjacent or separated by vertical spaces (Spacing strips). Consequently, one display page is made of a list of Character strips and Spacing strips. A Top Margin and a Left Margin are programmable in dedicated registers. 10.1 - RAM PROGRAMMING Each Strip is associated with a 2 bytes Strip Descriptor. There are two Strip Descriptors: - The Character Strip Descriptors containing the Text string Ram address of the Character Strip, - The Spacing Strip Descriptors which specify the vertical space height. In the example shown in Figure 8 on page 13, the OSD screen, is made of 9 strips. In RAM, there is: - one list of 9 Strip descriptors (size = 9 x 2 bytes = 18 bytes), - 6 Text strings, each of them made of the character codes from the line of text. Text strings can be programmed anywhere in 10.1.1 - Two kinds of Data: RAM. The Descriptor list can be located at 16 difStrip Descriptors and Character Codes ferent addresses in RAM. The address is defined An OSD screen is made of a number of Character in the Display Control Register. It is consequently and Spacing strips. possible to store up to 16 different pages in RAM. Two groups of Data make one OSD screen: The current Displayed page is specified in the Display Control Register. It refers to a given Page - a Strip Descriptors list, Descriptor list. - Text strings - one per Character strip. Figure 8. Display Page: List of Character and Spacing strips TOP MARGIN Text line number one Text line number two Strip 1 : Character Strip Strip 2 : Character Strip LEFT MARGIN Strip 3 : Spacing Strip Text line number three Strip 4 : Character Strip Strip 5 : Spacing Strip Text line number four Text line number five Text line number six Strip 6 : Character Strip Strip 7 : Character Strip Strip 8 : Character Strip Strip 9 : Spacing Strip (Bottom Margin) 13/24 5 STV9432TA 10.1.2 - Descriptors Spacing MSB 0 L/ C - - - - - - LSB SL7 SL6 SL5 SL4 SL3 SL2 SL1 SL0 L/ C : LINE or CHARACTER spacing: = 0, spacing descriptor defined as character height (SL[7:0] = 1 to 255 character). = 1, spacing descriptor defined as scan line height (SL[7:0] = 1 to 255 scan lines). SL[7:0] : Number of selected height (character or scan lines according L/ C ). Character MSB 1 DE CLU3 CLU2 CLU1 CLU0 C9 C8 LSB C7 C6 C5 C4 C3 C2 C1 C0 DE : Display enable: = 0, R = G = B = 0 and FBLK = FBK bit of display control register on the whole strip, = 1, display of the characters. CLU[3:0] : Active color selection at the begining of the strip. C[9:1] : Address of the first character code of the strip. C0 : Address 0 must be 0. 10.1.3 - Code Format There are basically 3 kinds of code: - the control codes from 0 to 15 (00H to 0FH), - the ROM monochrome character codes from 16 to 255 (10H to FFH), - the two bytes multicolor character codes from 08F0 to 08FF (Hex). For code definitions see Table 1. Table 1 Character and Command Codes 0 1 2 3 4 5 6 7 0 col 0 col 1 col 2 col 3 col 4 col 5 col 6 col 7 1 2 3 4 5 6 7 8 9 A B C D E 240 Monochrome Characters 8 multicol 9 nop A vflip B hflip C dflip D call E rtn F eof Single byte codes 00 to 0f are command codes. Single byte codes 10 to ff are monochrome character codes. Double byte codes 08F0 to 08FF are multicolor character codes. 14/24 5 F STV9432TA Figure 9. Character Font of the STV9432TA 15/24 5 STV9432TA Control Codes Control codes must be followed by a displayable code, except for RTN & EOL. They must not be used twice consecutively without a displayable code between them. The control code CALL is preceded by an address byte. The control codes are not displayed except if mentioned. Code 14 (0Eh): RTN: return to the CALL + 1 code location (see Note). Codes 0 to 7 (0h to 7h): COL0 to COL7 codes select 1 byte among 8 within the CLUT in RAM. The block selection is fixed by CLU3 bit of the active character descriptor (see Table 1 and Table 2). Codes 16 to 255 (10h to FFh): ROM monochrome character codes. The character shapes are 12x18 pixel matrix described in Figure 9 . Code 8 (08h): Multicolor character precode, must be followed by a multicolor character number from F0h to FFh. Code 9 (09h): NOP: no operation is performed, can be used to spare a location in RAM for an active control code. Codes 10 to 12 (0Ah to 0Ch): FLIPS: HFLIP(0Bh) Horizontal Flip code flips horizontaly the following displayable code. VFLIP(0Ah) Vertical Flip code flips verticaly the following displayable code. DFLIP(0Ch) Horizontal & Vertical Flip code flips horizontaly and verticaly the following displayable code. Code 13 (0Dh): CALL, this control code switches the display of the next character to the code address given by the next byte as follows: 0 CALL CODE (odd @) MSB ADDRESS BYTE (even @) LSB A[9:1] : 0 0 0 1 1 0 1 A8 A7 A6 A5 A4 A3 A2 A1 Address of the next code to be used (A0 = 0 only even addresses), in low half part of RAM. Notes: CALL and RTN code must be used simultaneously. CALL and RTN codes are displayed as a SPACE character. CALL and RTN codes must be placed at odd addresses. They may be preceded by a NOP to place them at the right position. 16/24 5 Code 15 (0Fh): EOL, end of line terminates the display of the current row. ROM Character Codes Codes 256 to 272 (F0h to FFh): ROM multicolor character codes. They must be preceded by the multicolor pre-code 08h. The character shapes are 12x18 pixel matrix described in Figure 9. 10.2 - OSD LOOK-UP TABLE Color look-up table [CLUT] is read/write RAM table. Mapping address is described in Chapter 6.3.2 - I2C Registers Mapping on page 7. The CLUT is splitted into 2 blocks of 8 bytes. Each byte contains foreground and background informations as described below: TRA BR TRA FL BR, BG, BB FR, FG, FB BG : : : : BB FL FR FG Transparent background Flashing foreground Background color Foreground color FB Each block may store a different set of colors. One block of colors may be used for the normal items of the menu while the second block, with brighter colors, may be used for selected items of the menu. The block selection is done by programming bit CLU3 of CLU[3:0] of the character descriptor (see Table 2). It remains selected for the whole row. Bit CLU2, CLU1 and CLU0 of CLU[3:0] of the character descriptor select the active color at the beginning of the row. The active color can be modified along the row, using 8 control codes COL0 to COL7. Each control code (COL0 to COL7) activates a dedicated color byte in the CLUT as described in Table 2. STV9432TA Table 2 CLUT Block Selection CLU3 0 1 CLU[2:0] Code Name 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Col 0 Col 1 Col 2 Col 3 Col 4 Col 5 Col 6 Col 7 Col 0 Col 1 Col 2 Col 3 Col 4 Col 5 Col 6 Col 7 Command Code (hex) 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07 Ram @(hex) Reset Value (hex) 07 16 25 34 43 52 61 70 70 61 52 43 34 25 16 07 @4020 @4021 @4022 @4023 @4024 @4025 @4026 @4027 @4028 @4029 @402A @402B @402C @402D @402E @402F 10.3 - OSD CONTROL REGISTERS Line Duration (reset value: 20H) 4030 VSP HSP LD6 VSP : V-SYNC active edge selection = 0, falling egde, = 1, rising edge. HSP : HFLY active edge selection = 0, rising egde, = 1, falling edge. LD[6:1] : LINE DURATION LD0 = 0 LD1 = 2 periods of character One character period is 12 pixels long. LD5 LD4 LD3 LD2 LD1 M6 M5 M4 M3 M2 Top Margin (reset value: 30H) 4031 M9 M8 M7 M[9:2] : TOP MARGIN height from the VSYNC reference edge. M0 = 0, M1 = 0 M2 = 4 scan lines Note : The top margin is displayed before the first strip of descriptor list. It can be black if FBK of DISPLAY CONTROL register is set or transparent if FBK is clear. 17/24 5 STV9432TA Horizontal Delay (reset value: 20H) 4032 DD[7:0] DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 : HORIZONTAL DISPLAY DELAY from the HSYNC reference edge to the 1st pixel position of the character strips. Unit = 6 pixel periods. Minimum value is 08H. First pixel position = [DD[7:0] - 6] x 6 + 54 with DD[7:0] = 0,2,4,6 delay is 54 pixel and with DD[7:0] = 1,3,5 delay is 60 pixel Characters Height (reset value: 24H) 4033 CH[5:0] - - CH5 CH4 CH3 CH2 CH1 CH0 : HEIGHT of the character strips in scan lines. For each scan line, the number of the slice which is displayed is given by: SLICE-NUMBER = ( round SCAN-LINE-NUMBER x 18 ) CH[5:0] SCAN-LINE-NUMBER = Number of the current scan line of the strip. Display Control (reset Value: 00H) 4034 OSD OSD FBK : : FL[1:0] : FBK FL1 FL0 P9 P8 P7 P6 ON/OFF (if 0, R, G, B and FBLK outputs are 0). Fast blanking control: = 1, forces FBLK pin at "1" outside and inside the OSD area. This leads to blank video RGB and to only display OSD RGB. = 0, FBLK pin is driven according character code for normal display of OSD data. Flashing mode : - 00: No flashing. The character attribute is ignored, - 01: Flashing at fF (50% duty cycle), - 10: Flashing at 2 fF - 11: Flashing at 4 fF Note: fF is 128 time vertical frequency. P[9:6] : Address of the 1st descriptor of the current displayed pages. P[13:10] and P[5:0] = 0; up to 16 different pages can be stored in the RAM. Locking Condition Time Constant (reset value: 01H) 4035 FR AS[2:0] BS[2:0] LUK 18/24 5 FR AS2 AS1 AS0 LUK BS2 BS1 : Free Running; if = 1 PLL is disabled and the pixel frequency keeps its last value. : Phase constant during locking conditions. : Frequency constant during locking conditions. : Lock unlock status bit 0 = unlocked PLL 1 = Locked PLL BS0 STV9432TA Capture Process Time Constant (reset value: 24H) 4036 LEN AF[2:0] BF[2:0] LEN AF2 AF1 AF0 - BF2 BF1 BF0 PP2 PP1 PP0 : Lock enable 0 = R,G,B, FBLK are always enabled, 1 = R,G,B,, FBLK are enabled only when PLL is locked. : Phase constant during the capture process. : Frequency constant during the capture process. Initial Pixel Period (reset value: 06H) 4037 PP[7:0] PP7 : PP6 PP5 PP4 PP3 Value to initialize the pixel period of the PLL. 10.4 - OSD TIMINGS The number of pixel periods is given by the LINE DURATION register and is equal to: [LD[6:1] x 2 + 1 ] x 12. (LD[6:1]: value of the LINE DURATION register). This value is used to define the horizontal size of the characters. The horizontal left margin is given by the HORIZONTAL DELAY register and is equal to: (DD[7:0] -6) x 6 + 54 (DD[7:0]: value of the DISPLAY DELAY register). This value is used to define the horizontal position of the characters on the screen. Due to internal logic, minimum horizontal delay is fixed at 4.5 characters (54 pixel) when DD is even and inferior or equal to 6, and it is fixed at 5 characters (60 pixel) when DD is odd and inferior or equal to 7. 10.5 - PLL The PLL function of the STV9432TA provides the internal pixel clock locked on the horizontal synchro signal and used by the display processor to generate the R, G, B and fast blanking signals. It is made of 2 PLLs. The first PLL which is analog (see Figure 10) provides a high frequency that is 40 times the internal oscillator frequency, or 320MHz. This high frequency clock is used by the Display controller. The 320MHz frequency is then divided by three. The resulting 106.7MHz clock is used by the Video timings analysis block. The second PLL, fully digital (see Figure 11), provides a pixel frequency locked on the horizontal synchro signal. The ratio between the frequencies of these 2 signals is: M = 12 x (LD[6:1] x 2 + 1) where LD[6:1] is the value of the LINE DURATION register. Figure 10. Analog PLL N • fOSC VCO 40 fOSC FILTER Figure 11. Digital PLL M • fH-SYNC %D 40 • fOSC D(n) %M ALGO fH-SYNC err(n) 10.5.1 - Programming of the PLL Registers Initial Pixel Period (@4037) This register allows to increase the speed of the PLL convergence when the horizontal frequency changes (new graphic standard). The relationship between PP[7:0], LD[6:1], fHSYNC and fOSC is: ( PP[7:] = round 40 . fOSC ) 6. (2 . LD + 1) . fHSYNC 19/24 5 STV9432TA Locking Condition Time Constant (@ 4035) This register provides the AS[2:0] and BS[2:0] constants used by the algo part of the PLL (see Figure 10). These two constants as well as the phase error (err(n)) give the new value (Dn) of the high frequency signal division. Consequently, AS[2:0] and BS[2:0] fix the pixel clock frequency. These two constants are used only in locking condition, if the phase error is inferior to a fixed value during at least 4 scan lines. If the phase error becomes superior to the fixed value, the PLL is not in locking condition but in capture process. In this case, the algo part of the PLL uses the other constants AF[2:0] and BF[2:0] from the next register. If ( α + β )2 - 4 β ≥ 0 and 2 α – β < 4, the PLL is stable and its response is as shown in Figure 15. If ( α + β )2 - 4 β ≤ 0 , the response of the PLL is as shown in Figure 13. In this case the PLL is stable if τ > 0.7 damping coefficient. Table 3 gives some good values for A and B constants for different values of the LINE DURATION. Figure 12. Time Response of the PLL/ Characteristic equation solutions (with real solutions) PLL Frequency f1 f0 Capture Process Time Constant (@ 4036) The choice between these two time constants (locking condition or capture process) allows to decrease the capture process time by changing the time response of the PLL. 10.5.2 - How to choose the time constant value The time response of the PLL is given by its characteristic equation which is: (x - 1)2 + ( α + β ) . (x - 1) + β = 0 Where: α = 3 ⋅ LD[6:1] . 2A -11 and β = 3 . LD[6:1] . 2B - 19 (LD[6:1] = value of the LINE DURATION register, A = value of the 1st time constant, AF or AS and B = value of the 2d time constant, BF or BS). As can be seen, the solution depends only on the LINE DURATION and the TIME CONSTANTS given by the I2C registers. Table 3 Valid Time Constants Examples t Input Frequency f1 f0 t Figure 13. Time Response of the PLL/ Characteristic equation solutions (with complex solutions) PLL Frequency f1 f0 t Input Frequency f1 f0 t B \ A 0 1 2 3 4 5 6 0 YYYY YYYY YYYY YYYN YNNN NNNN NNNN 1 YYYY YYYY YYYY YYYN YNNN NNNN NNNN 2 NYYY YYYY YYYY YYYN YNNN NNNN NNNN 3 NNNY YYYY YYYY YYYN YNNN NNNN NNNN 4 NNNN NYYY(1) YYYY YYYN YNNN NNNN NNNN 5 NNNN NNNY YYYY YYYN YNNN NNNN NNNN 6 NNNN NNNN NYYY YYYN YNNN NNNN NNNN 7 NNNN NNNN NNNY YYYN YNNN NNNN NNNN Case of A[2:0] = 1 (001) and B[2:0] = 4 (100) :Table meaning: N = No possible capture - No stability, Y = PLL can lock. LD[6:1] 8 16 24 32 Valid Time Constants N Y Y Y 20/24 5 Separate path for digitlal GND 1kΩ 1kΩ R2 2.2kΩ C11 1 FILTER 2 AGND I2C bus Horizontal sync Vertival sync Fly back pulse Active video L1 C7 100nF 100mH C1 C2 C3 C4 Xtal 8 Mhz TEST 24 1kΩ 47µF R4 C16 100pF C12 C14 1nF C8 R3 100pF 22µF R1 VDD +5V Beam current inputs C14 100nF 11 - APPLICATION DIAGRAM Figure 14. GND ADCREF 23 3 SDA RCI 22 4 SCL GCI 21 5 HS BCI 20 6 VS AVdd 19 7 HFLY OVdd 18 8 AV FBLK 17 9 DVdd BOUT 16 10 DVss 11 XTi GOUT 15 12 XTO OVss 13 C10 100nF 100pF C15 L3 100mH 100mH L2 ROUT 14 C9 100pF 100pF 100pF 100pF 22pF 22pF C5 100nF C6 RGB outputs Fast blanking ouput STV9432TA 21/24 5 STV9432TA 22/24 STV9432TA 12 - PACKAGE MECHANICAL DATA 24 PINS - PLASTIC DIP (SHRINK) E A2 A L A1 E1 Stand-off B B1 e e1 e2 c E D 13 .015 F 24 0,38 Gage Plane 1 12 e3 SDIP24 Dimensions Min. A A1 A2 B B1 C D E E1 e e1 e2 e3 L 0.51 3.05 0.36 0.76 0.23 22.61 7.62 6.10 2.54 Millimeters Typ. 3.30 0.46 1.02 0.25 22.86 6.40 1.778 7.62 3.30 Max. 5.08 4.57 0.56 1.14 0.38 23.11 8.64 6.86 10.92 1.52 3.81 Min. 0.020 0.120 0.0142 0.030 0.0090 0.890 0.30 0.240 0.10 e2 Inches Typ. 0.130 0.0181 0.040 0.0098 0.90 0.252 0.070 0.30 0.130 Max. 0.20 0.180 0.0220 0.045 0.0150 0.910 0.340 0270 0.430 0.060 0.150 23/24 6 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. © 2000 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. 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