STMICROELECTRONICS STV9432TAP

STV9432TAP
100MHz OSD FOR MONITOR INCLUDING
BEAM CURRENTS, VIDEO TIMING ANALYZER AND PWMs
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MULTIFUNCTION OSD FOR MONITOR
INCLUDES FACILITIES FOR CUT-OFF VOLTAGE MONITORING:
- THREE 8 BITS ADC INPUTS
- ADC TRIGGER DURING RETRACE TIME OF A
PROGRAMMED LINE
INCLUDES FACILITIES FOR SCREEN SIZE &
CENTERING AUTO SETUP
- HS, VS, VIDEO TIMING MEASUREMENTS
100MHz MAX. PIXEL CLOCK, AVAILABLE FOR
ANY LINE FREQUENCY BETWEEN 15 AND 140
kHz
12 x 18 CHARACTER ROM FONT INCLUDES:
- 240 MONOCOLOR CHARACTERS
- 16 MULTICOLOR CHARACTERS
CHARACTER FLASHING
UP TO 1K CHARACTERS TEXT DISPLAY
ULTRA HIGH FREQUENCY PLL FOR
JITTER-FREE DISPLAY
FLEXIBLE DISPLAY:
- ANY CHARACTER WIDTH AND HEIGHT
- ANYWHERE IN THE SCREEN
SINGLE BYTE CHARACTER CODES AND
COLOR LOOK-UP TABLE FOR EASY PROGRAMMING AND FAST ACCESS
CHARACTER FLIP OPERATIONS
WIDE DISPLAY WINDOW ALLOWS PATTERN
GENERATION FOR FACTORY ADJUSTMENTS
I2C BUS MCU INTERFACE
FIVE 8 BITS PWM DAC OUTPUTS
ating at very high frequency, gives an accurrate
display without visible jitter for a wide line frequency range from 15 to 140 kHz.
- Cut-off Monitoring Circuitry includes: 5 x 8 bits
PWM DACs, 3 x 8 bits ADCs and a programmable
ADC sampling trigger. It gives the possibility to
measure the three beam currents, during the horizontal flyback, at a given line in the frame, provided that the three ADC inputs are connected to a
beam current sensing circuitry. The values are
stored in three BEAM CURRENT REGISTERS,
and available for MCU read.
- Video Timing Analyzer. Using the Horizontal Sync,
Vertical Sync, Horizontal Flyback, and ”Video
Active” inputs, a set of counters give the different
timing measurements necessary to analyze the
current Video timing characteristics in order to
make the automatic set-up of screen size and centering. The measurements are initialized on the
same programmable trigger line than in the above
cut-off monitoring circuitry.
.
SO28
(Plastic Micropackage)
ORDER CODE: STV9432TAP
DESCRIPTION
Connected to a host MCU via its serial I2C Bus, the
STV9432TAP is a multifunction slave peripheral
device integrating the following blocks:
- On-screen Display. It includes a MASK PROGRAMMABLE ROM that holds the CUSTOM
CHARACTER FONT, a 1Kbytes RAM that stores
the code strings of the different lines of text to be
displayed, and a set of registers to program character sizes and colors. A built-in digital PLL, oper-
Version 4.0
February 2000
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
1/25
1
STV9432TAP
1 - PIN CONNECTIONS
2/25
2
FILTER
1
28
TEST
AGND
2
27
ADCREF
SDA
3
26
RCI
SCL
4
25
GCI
HS
5
24
BCI
VS
6
23
AVDD
HFLY
7
22
OVDD
AV
8
21
FBLK
DVDD
9
20
BOUT
DVSS/OVSS
10
19
GOUT
XTI
11
18
ROUT
XTO
12
17
PWM5
PWM1
13
16
PWM4
PWM2
14
15
PWM3
STV9432TAP
2 - PIN DESCRIPTION
Pin Number
Symbol
Type
Description
1
FILTER
I/O
2
AGND
Power
3
SDA
I/O
I2C Bus Serial Data
4
SCL
I
I2C Bus Serial Clock
5
HS
I
Horizontal Sync Input
6
VS
I
Vertical Sync Input
7
HFLY
I
Horizontal Flyback Input
8
AV
I
Active Video Input
9
DVDD
Power
Digital +5V Power Supply
10
DV SS/OVSS
Power
Digital and RGB Output Ground
PLL Filter
Analog Ground
11
XTI
I
12
XTO
O
Crystal Oscillator Input
Crystal Oscillator Output
13
PWM1
O
PWM DAC Output 1
14
PWM2
O
PWM DAC Output 2
15
PWM3
O
PWM DAC Output 3
16
PWM4
O
PWM DAC Output 4
17
PWM5
O
PWM DAC Output 5
18
ROUT
O
Red Output
19
GOUT
O
Green Output
20
BOUT
O
Blue Output
Fast Blanking Output
21
FBLK
O
22
OVDD
Power
23
AVDD
Power
24
BCI
I
Blue Beam Current Input
25
GCI
I
Green Beam Current Input
26
RCI
I
Red Beam Current Input
27
ADCREF
I/O
ADC Reference Voltage Pin
28
TEST
I/O
Pin to be connected to ground
+5V Supply for the RGB Outputs
Analog +5V Power Supply
3/25
STV9432TAP
3 - BLOCK DIAGRAM
XTI
11
XTO
12
1
HS
5
TIMINGS
AV
8
ANALYZER
25
BCI 24
PWM2
15
PWM3
16
PWM4
17
PWM5
22
OV DD
18
ROUT
19
GOUT
20
BOUT
21
FBLK
10
DV SS/OVSS
CONTROLLER
6
GCI
14
DISPLAY
VS
RCI 26
PWMs
PLL
7
HFLY
PWM1
8 BITS
OSCILLATOR
FILTER
13
BEAM
CURRENT
MEASUREMENT
1k BYTES RAM
CHARACTER
FONT ROM
I2C BUS
INTERFACE
ADCREF 27
AVDD 23
DV DD
9
3.3V
2
AGND
3
SDA
4
SCL
28
VOLTAGE REGULATOR
TEST
POWER-ON RESET
STV9432TAP
4 - ABSOLUTE MAXIMUM RATINGS
Symbol
AVDD, DV DD, OVDD
VIN
4/25
Parameter
Supply Voltage
Input Voltage
Toper
Operating Temperature
Tstg
Storage Temperature
Value
Unit
-0.3, +6.0
V
VSS-0.3, VDD+0.3
V
0, +70
o
C
-40, +125
o
C
STV9432TAP
5 - ELECTRICAL CHARACTERISTICS
(VDD = 5V, VSS = 0V, GND = 0V, T A = 0 to 70o, unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
4.75
5
5.25
V
-
-
150
mA
SUPPLY
AVDD, DV DD, OVDD
Supply Voltage
AIDD+ DI DD + OIDD
Analog and Digital Supply Current
INPUTS (SCL, SDA)
VIL
Input Low Voltage
VIH
Input High Voltage
2.4
IIL
Input Leakage Current
-1
0.8
V
V
+1
µA
0.8
V
INPUTS (HS, VS, AV, HFLY)
VIL
VIH
Input Low Voltage
Input High Voltage
HS, VS, AV
HFLY
2.4
3.6
V
Schmidt Trigger Hysteresis
0.4
V
IPU
Pull-up Source Current (VIN = 0V)
100
µA
HSIN
Horinzontal Synchro Input Range
VHYST
15
-
140
kHz
0.4
V
OUTPUTS (SDA open drain)
V OL
Output Low Voltage (IOL = 3mA)
0
OUTPUTS (R, G, B, FBLK)
V OL
Output Low Voltage (IOL = 3mA)
0
0.4
V
VOH
Output High Voltage (IOH = 3mA)
0.8V DD
VDD
V
OSCILLATOR (XTI, XTO)
IIL
XTI Input Source Current (VIN = 0V)
3
15
µA
I IH
XTI Input Sink Current (VIN = VDD)
3
15
µA
VIL
XTI Input Low Voltage
VIH
XTI Input High Voltage
V OL
XTI Output Low Voltage (IOL = 3mA)
0
0.4
V
VOH
XTI Output High Voltage (IOH = 3mA)
0.8V DD
VDD
V
1.4
0.7V DD
V
V
ADCREF
VREF
3.3
Output Voltage Reference
V
8 BITS PWM DACs 1,2,3,4,5
0
0.4
V
V OL
Output Low Voltage (IOL = 1.6mA)
VOH
Output High Voltage (IOH = -0.8mA)
t PWM
PWM Period
256
tOSC
Supply Threshold Level
3.6
V
VCC - 0.5
V
POWER-ON RESET
DV DDTH
8 BITS ADC INPUTS (RCI, GCI, BCI)
VIN
Input Voltage
Z IN
Input Impedance
VOFF
Input Offset Voltage
ILEAK
Input Leakage Current
0
VADCREF
V
kΩ
100
3
LSB
50
µA
ILE
Integral Linearity Error (Note 2)
-2
+2
LSB
DLE
Differential Linearity Error (Note 2)
-0.5
+0.5
LSB
0
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STV9432TAP
6 - TIMINGS
Symbol
Parameter
Min.
Typ.
Max.
Unit
OSCILLATOR
fOSC
Clock Frequency
fPXL
Maximum Pixel Frequency
8
MHz
100
MHz
R, G, B, FBLK (CLOAD = 30pF)
tR
Rise Time (see Note 1)
5
ns
tF
Fall Time (see Note 1)
5
ns
Skew between R, G, B, FBLK
5
ns
tSKEW
I2C INTERFACE: SDA AND SCL (see Figure 1)
fSCL
SCL Clock Frequency
tBUF
Time the bus must be free between 2 access
500
ns
tHDS
Hold Time for Start Condition
500
ns
tSUP
Set up Time for Stop Condition
500
ns
tLOW
The Low Period of Clock
400
ns
400
ns
tHIGH
The High Period of Clock
tHDAT
Hold Time Data
tSUDAT
Set up Time Data
tF
Fall Time of SDA
tR
0
400
kHz
0
ns
500
ns
20
ns
Depend on the pull-up resistor and the
load capacitance
Rise Time of both SCL and SDA
ANALYZER (HS, HFLY, AV)
tHLOW
Low Pulse Width (see Note 3)
2
4091
tHTIM
tHHIGH
High Pulse Width
2
4091
tHTIM
Hs
Hfly
Hs Frequency
ANALYZER (VS)
tVLOW
Low Pulse Width
2
4091
Lines
tVHIGH
High Pulse Width
2
4091
Lines
Notes:
- These parameters are not tested on each unit. They are measured during our internal qualification procedure which
includes characterization on batches coming from corners of our processes and also temperature characterization.
- The ADC measurements are dependant on the noise. The test is done by correlation in order to screen out marginal
devices.
- tHTIM = 3tOSC : 40.
Figure 1.
STOP START
tBUF
STOP
DATA
tHDAT
SDA
tHDS
tSUDAT
tSUP
SCL
tHIGH
6/25
tLOW
STV9432TAP
7 - SERIAL INTERFACE
The 2-wires serial interface is an I2C interface. To be
connected to the I2C bus, a device must own its slave
address; the slave address of the STV9432TAP is BA
(in hexadecimal).
A6
A5
A4
A3
A2
A1
A0
1
0
1
1
1
0
1
- The successive bytes of data.
All bytes are sent MSB bit first and the write data
transfer is closed by a stop.
RW
7.2 - Data Transfer in Read Mode
The host MCU can read data from the STV9432TAP
register, RAM or ROM.
7.1 - Data Transfer in Write Mode
To read data from the STV9432TAP (Figure 3), the
MCU must send 2 different I2C sequences. The first
one is made of I2C slave address byte with R/W bit at
low level and the 2 internal address bytes.
The host MCU can write data into the STV9432TAP
registers or RAM.
To write data into the STV9432TAP, after a start, the
MCU must send (Figure 2):
The second one is made of I2C slave address byte
with R/W bit at high level and all the successive data
bytes read at successive addresses starting from the
initial address given by the first sequence.
the I2C address
slave byte with a low level for
- First,
the R/W bit,
- The two bytes of the internal address where the
MCU wants to write data,
Figure 2. I2C Write Operation
SCL
R/W
A7
SDA
I2 C Slave Address
Start
A6
A5
ACK
A4
A3
A2
A1
A0
LSB Address
-
-
A13
ACK
A12
A11
A10
A9
MSB Address
A8
ACK
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte 1
D7
D6
D5
ACK
D4
D3
D2
D1
D0
Data Byte 2
D7
D6
D5
ACK
D4
D3
D2
D1
D0
Data Byte n
ACK
Stop
Figure 3. I2C Read Operation
SCL
R/W
A7
SDA
2
Start
I C Slave Address
Start
I2C Slave Address
A6
A5
ACK
A4
A3
A2
A1
A0
LSB Address
-
-
ACK
A13 A12 A10 A10
A9
A8
MSB Address
ACK
Stop
ACK
Stop
SCL
D7
R/W
SDA
ACK*
D6
D5
D4
D3
Data Byte 1
D2
D1
D0
D7
ACK
D6
D5
D4
D3
Data Byte n
D2
D1
D0
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STV9432TAP
7.3 - ADDRESSING SPACE
7.3.1 - General Mapping
STV9432TAP registers, RAM and ROM are mapped in a 32Kbytes addressing space.
The mapping is the following:
0000
03FF
1024 bytes RAM
0400
07FF
Empty Space
0800
3FFF
Character Generator ROM
4000
403F
Internal Registers
4040
7FFF
Empty Space
Descriptors and character codes
Important Notice: All 16 bits datas are mapped LSB byte at lower address and MSB byte at higher address.
- Example: H1 12 bits register: @4000: 8 LSB bits - @4001: 4 MSB bits.
- Descriptors must also be written to RAM LSB byte first.
7.3.2 - I2C Registers Mapping
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
400A
400B
400C
400D
400E
400F
4010
4011
4012
4013
4014
4015
4016
4017-401F
4020
4021
H1 LSB
H1 MSB
H2 LSB
H2 MSB
H3 LSB
H3 MSB
H4 LSB
H4 MSB
H5 LSB
H5 MSB
H6 LSB
H6 MSB
V1 LSB
V1 MSB
V2 LSB
V2 MSB
V3 LSB
V3 MSB
RCI
GCI
BCI
SBN
TIMG
Reserved
Color 0
Color 1
4024
4025
4026
4027
4028
4029
402A
402B
402C
402D
402E
402F
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
403A
403B
403C
403D-403E
Color 4
Color 5
Color 6
Color 7
Color 8
Color 9
Color 10
Color 11
Color 12
Color 13
Color 14
Color 15
Line Duration
Top Margin
Horizontal Delay
Character Height
Display Control
Locking Time Constant
Capture Time Constant
Initial Pixel Period
PWM1
PWM2
PWM3
PWM4
PWM5
Reserved
4022
4023
Color 2
Color 3
403F
4040-7FFF
RST
Reserved
8/25
STV9432TAP
8 - TIMING ANALYZER
8.1 - VIDEO HORIZONTAL TIMINGS
All horizontal timing measurements use a 106.7MHz clock. This clock is made from the internal oscillator:
fHTIM = 40fOSC : 3. These twelve bits read-only registers read time measurements, given in t HTIM units.
They hold the value of the last measurement that was initiated by I2C command (see TIMG Register).
Figure 4.
AV
HS
HFLY E
A
D
C
B
A’
C’
F
D’
E’
F’
H1 Register: H sync to Active video, min of C to A
4000
H1.7
H1.6
H1.5
H1.4
H1.3
H1.2
H1.1
H1.0
4001
-
-
-
-
H1.11
H1.10
H1.9
H1.8
H2 Register: Active video to H sync, min of B to C’
4002
H2.7
H2.6
H2.5
H2.4
H2.3
H2.2
H2.1
H2.0
4003
-
-
-
-
H2.11
H2.10
H2.9
H2.8
H3 Register: Line period, C to C’
4004
H3.7
H3.6
H3.5
H3.4
H3.3
H3.2
H3.1
H3.0
4005
-
-
-
-
H3.11
H3.10
H3.9
H3.8
H4 Register: H Fly to H sync, E to C
4006
H4.7
H4.6
H4.5
H4.4
H4.3
H4.2
H4.1
H4.0
4007
-
-
-
-
H4.11
H4.10
H4.9
H4.8
H5 Register: H sync to H Fly, C to E’
4008
H5.7
H5.6
H5.5
H5.4
H5.3
H5.2
H5.1
H5.0
4009
-
-
-
-
H5.11
H5.10
H5.9
H5.8
H6 Register: H fly pulse, E to F
400A
H6.7
H6.6
H6.5
H6.4
H6.3
H6.2
H6.1
H6.0
400B
-
-
-
-
H6.11
H6.10
H6.9
H6.8
8.2 - VIDEO VERTICAL TIMINGS
These twelve bits read-only registers read time measurements, given in number of scan lines. They hold the
value of the last measurement that was initiated by I2C command (see TIMG Register).
Figure 5.
AV
VS
A
K
L
B
A’
K’
L’
9/25
3
STV9432TAP
V1 Register: V sync to Active video, min. of K to A
400C
V1.7
V1.6
V1.5
V1.4
V1.3
V1.2
V1.1
V1.0
400D
-
-
-
-
V1.11
V1.10
V1.9
V1.8
V2.3
V2.2
V2.1
V2.0
V2.11
V2.10
V2.9
V2.8
V2 Register: Active video to V sync, min. of B to K’
400E
V2.7
V2.6
V2.5
V2.4
400F
-
-
-
-
V3 Register: Number of lines per frame, K to K’
’
4010
V3.7
V3.6
V3.5
V3.4
V3.3
V3.2
V3.1
V3.0
4011
-
-
-
-
V3.11
V3.10
V3.9
V3.8
8.3 - TIMING ANALYSIS TRIGGER
The Timing Analysis is performed according to the setting of SBN and TIMG registers:
8.3.1 - SBN Register
This 8 bits register holds the ”sampling bloc” number.
The sampling bloc is a set of 4 consecutive scan lines, the first of which is used for sampling the video timings or
Beam currents.
The reset value of this register is 0.
4015
SBN7
SBN6
SBN5
SBN4
SBN3
SBN2
SBN1
SBN0
NFR1
NFR0
ADCDLY3
ADCDLY2
ADCDLY1
ADCDLY0
SELECT
8.3.2 - TIMG Register
4016
STM
This 8 bits register holds the following parameters:
STM
:
NFR [1:0]
ADCDLY[3:0]
SELECT
:
:
:
Start Measurement Bit. This bit has to be forced to 1 by I2C to start the measurement sequence, depending on the measurement selection bit. When measurement is completed the IC will reset this bit to 0.
NFR number of measurement frames, 1 to 4 frames
Cut-off Beam current ADC sampling delay time: 0 to 15 x tOSC , by tOSC steps
Selection of Beam current measurement (0) or Timing measurement (1)
To initiate a Timing Analysis cycle:
- program the Sampling Bloc Number in the SBN Register,
- program the TIMG Register, with: ”SELECT” bit =1, ”NFR” bits specify the number of measurement frames
(H1, H2, V1, V2), ”STM” bit = 1 (Start Measurement).
As soon as the measurement cycle is finished, the ”STM” bit is automatically reset by the device.
After a Timing Analysis cycle, reading a zero in STM bit of TIMG register means that the measurement is completed and the mcu may read the results in Hi and Vi registers.
10/25
STV9432TAP
Figure 6. Video Timing Measurement sequence - “Select bit = 1” (TIMG register, bit 0)
I2C SET STM BIT (TIMG register)
WAIT FOR ACKNOWLEDGE BIT
WAIT FOR RISING EDGE OF VS
MEASURES H1 AT EVERY LINE
DURING NFR+1 FRAMES.
AFTER NFR+1 FRAMES,
H1 HOLDS THE MIN.VALUE
MEASURES V3
WAIT FOR 4*SBN RISING EDGES OF HS
MEASURES V1 DURING NFR+1
AND KEEPS THE MIN. VALUE
MEASURES H2 AT EVERY LINE
DURING NFR+1 FRAMES.
AFTER NFR+1 FRAMES,
H2 HOLDS THE MIN.VALUE
ACQUISITION OF H3, H4, H5, H6
MEASURES V2 DURING NFR+1
AND KEEPS THE MIN. VALUE
AFTER NFR+1 FRAMES, RESET STM BIT
11/25
STV9432TAP
9 - BEAM CURRENTS MEASUREMENT
9.1 - BEAM CURRENT MEASUREMENT REGISTERS
The Beam Current Measurement circuitry uses three A to D converters, sampled at fOSC frequency.
These three 8 bits registers read the values of the last Beam currents measurement, initiated by I2C command (see TIMG register).
RCI Register: Red Beam Current Input
4012
RCI7
RCI6
RCI5
RCII4
RCI3
RCI2
RCI1
RCI0
GCI4
GCI3
GCI2
GCI1
GCI0
BCI4
BCI3
BCI2
BCI1
BCI0
GCI Register: Green Beam Current Input
4013
GCI7
GCI6
GCI5
BCI Register: Blue Beam Current Input
4014
BCI7
BCI6
BCI5
9.2 - BEAM CURRENT MEASUREMENT TRIGGER
The Beam Currents Measurement is performed according to the setting of SBN and TIMG registers :
9.2.1 - SBN Register
This 8 bits register holds the ”sampling bloc” number. The sampling bloc is a set of 4 consecutive scan
lines, the first of which is used for sampling the video timings or Beam currents. The reset value of this
register is 0.
4015
SBN7
SBN6
SBN5
SBN4
SBN3
SBN2
SBN1
SBN0
NFR1
NFR0
ADCDLY3
ADCDLY2
ADCDLY1
0
SELECT
9.2.2 - TIMG Register
4016
STM
This 8 bits register holds the following parameters:
STM
: Start Measurement Bit. This bit has
to be forced to 1 by I2C to start the
measurement sequence, depending
on the measurement selection bit.
When measurement is completed
the IC will reset this bit to 0.
NFR
[1:0]
: NFR number of measurement
frames, 1 to 4 frames
ADCDLY : Cut-off Beam current ADC sampling
[3:0]
delay time: 0 to 15 x tOSC, by tOSC
steps
SELECT : Selection of Beam current measurement (0) or Timing measurement (1)
When measurement is completed the IC will reset
this bit to 0. The reset value of this register is 0.
To initiate a Beam Currents Measurement cycle:
- program the Sampling Bloc Number in the SBN
Register,
- program the TIMG Register, with: ”SELECT”
bit = 0, ”ADCDLY” bits specify the sampling
time during HFly, ”STM” bit = 1 (Start Measurement).
As soon as the measurement cycle is finished, the
”STM” bit is automatically reset by the device.
After a Beam Currents Measurement cycle, reading a zero in STM bit of TIMG register means that
the measurement is completed and the MCU may
read the results in RCI, GCI, and BCI registers.
15/29
4
STV9432TAP
Figure 7. Beam Currents Measurement Sequence - “Select bit = 0” (TIMG register, bit 0)
I2C SET STM BIT (TIMG register)
WAIT FOR ACKNOWLEDGE BIT
WAIT FOR RISING EDGE OF VS
WAIT FOR 4*SBN RISING EDGES OF HS
WAIT FOR RISING EDGE OF HFLY
WAIT FOR ADC DLY
ACQUISITION OF RBC, GBC, BBC
RESET STM BIT
16/29
STV9432TAP
10 - DIGITAL TO ANALOG PWM OUTPUTS
The five to A outputs PWM1 toc5 of the STV9432TAP are pulse width modulator type converter outputs.
The frequency of the output signal is fOSC: 256 and the duty cycle is: Value [7:0]: 256. After an external
low pass filter, the voltage value of the output is: Value [7:0] x VDD : 256.
Figure 8.
PWM1 Signal
256 x tOSC
V1[7:0]
0
tOSC
1
128
255
10.1 - PWM REGISTERS
Pulse Width Modulator 1
4038
V17
V16
V15
V14
V13
V12
V11
V10
V22
V21
V20
V32
V31
V30
V42
V41
V40
V52
V51
V50
V1[7:0] : Digital value of the 1st PWM D to A converter (Pin 13)
Pulse Width Modulator 2
4039
V27
V26
V25
V24
V23
V2[7:0] : Digital value of the 2nd PWM D to A converter (Pin 14)
Pulse Width Modulator 3
403A
V37
V36
V35
V34
V33
V3[7:0] : Digital value of the 3rd PWM D to A converter (Pin 15)
Pulse Width Modulator 4
403B
V47
V46
V45
V44
V43
V4[7:0] : Digital value of the 4th PWM D to A converter (Pin 16)
Pulse Width Modulator 5
403C
V57
V56
V55
V54
V53
V5[7:0] : Digital value of the 5th PWM D to A converter (Pin 17)
Note: Power-on reset default value of PWM register is
14/25
5
OOH.
STV9432TAP
11 - SOFTWARE RESET REGISTER
403F
-
-
-
-
-
-
-
RST
To perform a software I2C reset of the device, set the RST bit to ONE.
This bit will be automatically reset by the device.
Software Reset will put all Write registers at their default power-on value, and reset all internal logic
blocks except the I2C bus interface itself. It will not change the RAM contents.
12 - ON-SCREEN DISPLAY
The STV9432TAP on-screen display is able to display any line of characters (character strip) anywhere in the screen.
Character strings are programmed by the MCU in
RAM via I 2C bus. Character shapes are coded in
the internal ROM font. Character strips may be
adjacent or separated by vertical spaces (Spacing
strips)
Consequently, one display page is made of a list
of Character strips and Spacing strips.
A Top Margin and a Left Margin are programmable
in dedicated registers.
12.1 - RAM PROGRAMMING
12.1.1 - Two kinds of Data
Strip Descriptors and Character Codes
An OSD screen is made of a number of Character
and Spacing strips.
There are two groups of Data that make one OSD
screen:
- a Strip Descriptors list,
- Text strings - one per Character strip.
Each Strip is associated with a 2 bytes Strip
Descriptor.
There are two kinds of Strip Descriptors:
- Character Strip Descriptors: they contain the
Text string Ram address of the Character Strip,
- Spacing Strip Descriptors: they specify the vertical space height.
In the example shown in Figure 9, the OSD
screen, is made of 9 strips.
In RAM, there is:
- one list of 9 Strip descriptors
(size = 9 x 2 bytes = 18 bytes),
- 6 Text strings, each of them is made of the
character codes of the line of text.
Text strings can be programmed anywhere in
RAM. The Descriptor list can be located at 16 different addresses in RAM, this address is defined
in the Display Control Register.
It is consequently possible to store up to 16 different pages in RAM.
The current Displayed page is specified in the Display Control Register. It refers to a given Page
Descriptor list.
Figure 9. Display Page: list of Character and Spacing strips
TOP MARGIN
Text line number one
Text line number two
Strip 1 : Character Strip
Strip 2 : Character Strip
LEFT MARGIN
Strip 3 : Spacing Strip
Text line number three
Strip 4 : Character Strip
Strip 5 : Spacing Strip
Text line number four
Text line number five
Text line number six
Strip 6 : Character Strip
Strip 7 : Character Strip
Strip 8 : Character Strip
Strip 9 : Spacing Strip (Bottom Margin)
15/25
STV9432TAP
12.1.2 - Descriptors
Spacing
MSB
0
L/ C
-
-
-
-
-
-
LSB
SL7
SL6
SL5
SL4
SL3
SL2
SL1
SL0
L/ C
: LINE or CHARACTER spacing:
= 0, spacing descriptor defined as character height (SL[7:0] = 1 to 255 character).
= 1, spacing descriptor defined as scan line height (SL[7:0] = 1 to 255 scan lines).
SL[7:0]
: Number of selected height (character or scan lines according L/ C ).
Character
MSB
1
DE
CLU3
CLU2
CLU1
CLU0
C9
C8
LSB
C7
C6
C5
C4
C3
C2
C1
C0
DE
: Display enable:
= 0, R = G = B = 0 and FBLK = FBK bit of display control register on the whole strip,
= 1, display of the characters.
CLU[3:0]
: Active color selection at the begining of the strip.
C[9:1]
: Address of the first character code of the strip.
C0
: Address 0 must be 0.
12.1.3 - Code Format
There are basically 3 kinds of code:
- the control codes from 0 to 15 (00H to 0FH),
- the ROM monochrome character codes from 16 to 255 (10H to FFH),
- the two bytes multicolor character codes from 08F0 to 08FF (Hex).
For code definitions see Table 1.
Table 1
Character and Command Codes
0
1
2
3
4
5
6
7
0
col 0
col 1
col 2
col 3
col 4
col 5
col 6
col 7
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
240 Monochrome Characters
8
multicol
9
nop
A
vflip
B
hflip
C
dflip
D
call
E
rtn
F
eof
Single byte codes 00 to 0f are command codes. Single byte codes 10 to ff are monochrome character codes. Double
byte codes 08F0 to 08FF are multicolor character codes.
16/25
STV9432TAP
Figure 10. Character Font for the STV9432TAP
17/25
STV9432TAP
Control Codes
Control codes must be followed by a displayable
code, except for RTN & EOL. They must not be
used twice consecutively without a displayable
code between them.
The control code CALL is preceded by an address
byte. The control codes are not displayed except if
mentioned.
Codes 0 to 7 (0h to 7h):
COL0 to COL7 codes select 1 byte among 8
within the CLUT in RAM. The block selection is
fixed by CLU3 bit of the active character descriptor
(see Table 1 and Table 2).
Code 8 (08h):
Multicolor character precode, must be followed by
a multicolor character number from F0h to FFh.
Code 9 (09h):
NOP: no operation is performed, can be used to
spare a location in RAM for an active control code.
Codes 10 to 12 (0Ah to 0Ch):
FLIPS:
HFLIP(0Bh) Horizontal Flip code flips horizontaly
the following displayable code.
VFLIP(0Ah) Vertical Flip code flips verticaly the
following displayable code.
DFLIP(0Ch) Horizontal & Vertical Flip code flips
horizontaly and verticaly the following displayable
code.
Code 13 (0Dh):
CALL, this control code switch the display of the
next character to the code address given by the
next byte as following:
CALL CODE
(odd @) MSB
ADDRESS BYTE
(even @) LSB
A[9:1]
0
0
0
0
1
1
0
1
A8 A7 A6 A5 A4 A3 A2 A1
: Address of the next code to be
used (A0 = 0 only even
addresses), in low half part of
RAM.
Notes:
CALL and RTN code must be used simultaneously.
CALL and RTN codes are displayed as a SPACE
character.
CALL and RTN codes must be placed at odd addresses. They may be preceed by a NOP in order to
place them at the right position.
18/25
Code 14 (0Eh):
RTN: return to the CALL + 1 code location (see
Note).
Code 15 (0Fh):
EOL, end of line terminates the display of the current row.
ROM Character Codes
Codes 16 to 255 (10h to FFh):
ROM monochrome character codes. The characters shapes are 12x18 pixel matrix described in
Figure 11.
Codes 256 to 272 (F0h to FFh):
ROM multicolor character codes. They must be
preceded by the multicolor pre-code 08h. The
characters shapes are 12x18 pixel matrix
described in Figure 11.
12.1.4 - OSD Look-up Table
Color look-up table [CLUT] is read/write RAM
table. Mapping address is described above in the
section ROM Character Codes.
The CLUT is splitted in 2 blocks of 8 bytes. Each
byte contains foreground and background informations as described below:
TRA
BR
TRA
FL
BR, BG, BB
FR, FG, FB
BG
:
:
:
:
BB
FL
FR
FG
FB
Transparent background
Flashing foreground
Background color
Foreground color
Each block may store a different set of colors. One
block of colors may be used for the normal items
of the menu while the second block, with brighter
colors, may be used for selected items of the
menu.
The block selection is done by programming bit
CLU3 of CLU[3:0] of the character descriptor (see
Table 2). It remains selected all the row long.
Bit CLU2, CLU1 and CLU0 of CLU[3:0] of the
character descriptor select the active color at the
beginning of the row.
The active color can be changed along the row,
using 8 control codes COL0 to COL7.
Each control code (COL0 to COL7) activate a dedicated color byte in the CLUT as described in
Table 2.
STV9432TAP
Table 2
CLUT Block Selection
CLU3
CLU[2:0]
Code Name
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
Col
Command Code
(hex)
00
01
02
03
04
05
06
07
00
01
02
03
04
05
06
07
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Ram @(hex)
Reset Value (hex)
@4020
@4021
@4022
@4023
@4024
@4025
@4026
@4027
@4028
@4029
@402A
@402B
@402C
@402D
@402E
@402F
07
16
25
34
43
52
61
70
70
61
52
43
34
25
16
07
12.2 - OSD CONTROL REGISTERS
Line Duration (reset value: 20H)
4030
VSP
HSP
LD6
VSP
:
V-SYNC active edge selection
= 0, falling egde,
= 1, rising edge.
HSP
:
HFLY active edge selection
= 0, rising egde,
= 1, falling edge.
LD[6:1]
:
LINE DURATION
LD0 = 0
LD1 = 2 periods of character
One character period is 12 pixels long.
LD5
LD4
LD3
LD2
LD1
M6
M5
M4
M3
M2
Top Margin (reset value: 30H)
4031
M[9:2]
M9
M8
M7
: TOP MARGIN height from the VSYNC reference edge.
M0 = 0, M1 = 0
M2 = 4 scan lines
Note: The top margin is displayed before the first strip of descriptor list. It can be black if FBK of DISPLAY CONTROL
register is set or transparent if FBK is clear.
Horizontal Delay (reset value: 20H)
4032
DD[7:0]
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
: HORIZONTAL DISPLAY DELAY from the HSYNC reference edge to the 1st pixel position of the character strips.
Unit = 6 pixel periods. Minimum value is 08H. First pixel position = [DD[7:0] - 6] x 6 + 54 with
DD[7:0] = 0,2,4,6 delay is 54 pixel and with DD[7:0] = 1,3,5 delay is 60 pixel
19/25
STV9432TAP
Character Height (reset value: 24H)
4033
CH[5:0]
:
-
CH5
CH4
CH3
CH2
CH1
CH0
HEIGHT of the character strips in scan lines. For each scan line, the number of the slice which is displayed is
given by:
SLICE-NUMBER =
(
SCAN-LINE-NUMBER x 18 )
round
CH[5:0]
SCAN-LINE-NUMBER = Number of the current scan line of the strip.
Display Control (reset Value: 00H)
4034
OSD
OSD
FBK
:
:
FL[1:0]
:
FBK
FL1
FL0
P9
P8
P7
P6
BS1
BS0
ON/OFF (if 0, R, G, B and FBLK outputs are 0).
Fast blanking control:
= 1, forces FBLK pin at ”1” outside and inside the OSD area.
This leads to blank video RGB and to only display OSD RGB.
= 0, FBLK pin is driven according character code for normal display of OSD data.
Flashing mode :
- 00: No flashing. The character attribute is ignored,
- 01: Flashing at fF (50% duty cycle),
- 10: Flashing at 2 fF
- 11: Flashing at 4 fF
Note: fF is 128 time vertical frequency.
P[9:6]
:
Address of the 1st descriptor of the current displayed pages.
P[13:10] and P[5:0] = 0; up to 16 different pages can be stored in the RAM.
Locking Condition Time Constant (reset value: 01H)
4035
FR
AS[2:0]
BS[2:0]
LUK
FR
:
:
:
:
AS2
AS1
AS0
LUK
BS2
Free Running; if = 1 PLL is disabled and the pixel frequency keeps its last value.
Phase constant during locking conditions.
Frequency constant during locking conditions.
Lock unlock status bit
0 = unlocked PLL
1 = Locked PLL
Capture Process Time Constant (reset value: 24H)
4036
LEN
AF[2:0]
BF[2:0]
LEN
AF2
AF1
AF0
-
BF2
BF1
BF0
PP3
PP2
PP1
PP0
: Lock enable
0 = R,G,B, FBLK are always enabled,
1 = R,G,B,, FBLK are enabled only when PLL is locked.
: Phase constant during the capture process.
: Frequency constant during the capture process.
Initial Pixel Period (reset value: 06H)
4037
PP[7:0]
20/25
PP7
PP6
PP5
PP4
: Value to initialize the pixel period of the PLL.
STV9432TAP
12.3 - OSD TIMINGS
The number of pixel periods is given by the LINE
DURATION register and is equal to:
[LD[6:1] x 2 + 1 ] x 12.
(LD[6:1]: value of the LINE DURATION register).
This value allows to define the horizontal size of
the characters.
The horizontal left margin is given by the HORIZONTAL DELAY register and is equal to:
(DD[7:0] -6) x 6 + 54
(DD[7:0]: value of the DISPLAY DELAY register).
This value allows to define the horizontal position
of the characters on the screen. Due to internal
logic, minimum horizontal delay is fixed at 4.5
characters (54 pixel) when DD is even and lower
or equal to 6, and it is fixed at 5 characters (60
pixel) when DD is odd and lower or equal to 7.
12.4 - PLL
The PLL function of the STV9432TAP provides
the internal pixel clock locked on the horizontal
synchro signal and used by the display processor
to generate the R, G, B and fast blanking signals.
It is made of 2 PLLs. The first one analog (see Figure 11) provides a high frequency that is 40 times
the internal oscillator frequency, or 320MHz. This
high frequency clock is used by the Display controller.
The 320MHz frequency is then divided by three.
The resulting 106.7MHz clock is used by the
Video timings analysis block.
The second PLL, full digital (see Figure 12), provides a pixel frequency locked on the horizontal
synchro signal. The ratio between the frequencies
of these 2 signals is:
M = 12 x (LD[6:1] x 2 + 1) where LD[6:1] is the
value of the LINE DURATION register.
Figure 11. Analog PLL
N • fOSC
VCO
40
fOSC
FILTER
Figure 12. Digital PLL
M • fH-SYNC
40 •f OSC
%D
D(n)
%M
ALGO
fH-SYNC
err(n)
12.4.1 - Programming of the PLL Registers
Initial Pixel Period (@4037)
This register allows to increase the speed of the
convergence of the PLL when the horizontal frequency changes (new graphic standard). The
relationship between PP[7:0], LD[6:1], fHSYNC and
fOSC is:
(
PP[7:0] = round
40 . f OSC
.
)
.
6 . (2 LD + 1) fHSYNC
Locking Condition Time Constant (@ 4035)
This register provides the AS[2:0] and BS[2:0]
constants used by the algo part of the PLL (see
Figure 11). These two constants as well as the
phase error err(n) give the new value D(n) of the
high frequency signal division. AS[2:0] and
BS[2:0] fix the pixel clock frequency. These two
constants are used only in locking condition, if the
phase error is inferior to a fixed value during at
least 4 scan lines. If the phase error becomes
greater than this fixed value, the PLL is not in locking condition but in capture process. In this case,
the algo part of the PLL used the other constants,
AF[2:0] and BF[2:0], given by the next register.
Capture Process Time Constant (@ 4036)
The choice between these two time constants
(locking condition or capture process) allows to
decrease the capture process time by changing
the time response of the PLL.
12.4.2 - How to choose the time constant value
The time response of the PLL is given by its characteristic equation which is:
(x - 1)2 + ( α + β ) . (x - 1) + β = 0
Where:
α = 3 ⋅ LD [6:1] . 2A -11 and β = 3 . LD[6:1] . 2B - 19
(LD[6:1] = value of the LINE DURATION register,
A = value of the 1st time constant, AF or AS and
B = value of the 2d time constant, BF or BS).
As you can see, the solution depends only on the
LINE DURATION and the TIME CONSTANTS
given by the I2C registers.
If ( α + β )2 - 4 β ≥ 0 and 2 α – β < 4, the PLL is stable and its response is like that presented in Figure 14.
If ( α + β )2 - 4 β ≤ 0 , the response of the PLL is
like that presented in Figure 15. In this case the
PLL is stable if τ > 0.7 damping coefficient). Table
3 gives some good values for A and B constants
for different values of the LINE DURATION.
21/25
STV9432TAP
Figure 13. Time Response of the PLL/
Characteristic equation solutions (with real
solutions)
Figure 14. Time Response of the PLL/
Characteristic equation solutions (with
complex solutions)
PLL Frequency
PLL Frequency
f1
f1
f0
f0
t
t
Input Frequency
Input Frequency
f1
f1
f0
f0
Table 3
t
t
Valid Time Constants Examples
B \ A
0
1
2
3
4
5
6
0
YYYY
YYYY
YYYY
YYYN
YNNN
NNNN
NNNN
1
YYYY
YYYY
YYYY
YYYN
YNNN
NNNN
NNNN
2
NYYY
YYYY
YYYY
YYYN
YNNN
NNNN
NNNN
3
NNNY
YYYY
YYYY
YYYN
YNNN
NNNN
NNNN
4
NNNN
NYYY(1)
YYYY
YYYN
YNNN
NNNN
NNNN
5
NNNN
NNNY
YYYY
YYYN
YNNN
NNNN
NNNN
6
NNNN
NNNN
NYYY
YYYN
YNNN
NNNN
NNNN
7
NNNN
NNNN
NNNY
YYYN
YNNN
NNNN
NNNN
8
16
24
32
N
Y
Y
Y
Note : Case of A[2:0] = 1 (001) and B[2:0] = 4 (100):
LD[6:1]
Valid Time Constants
Table meaning: N = No possible capture - No stability, Y = PLL can lock.
22/25
Horizontal sync
Vertival sync
Fly back pulse
Active video
I2C bus
C1
C2
C3
C4
100pF 100pF 100pF 100pF
C5
22pF
R5
C6
22pF
R8
PWM outputs
4.7 µF
R8
4.7 µF
10kΩ
4.7 µF
C9
100nF
R6
10kΩ
PWM315
PWM416
13 PWM1
14 PWM2
ROUT18
PWM517
12 XTO
GOUT19
10 DVss/OVss
11 XTi
FBLK21
BOUT20
OVdd22
7 HFLY
8 AV
AVdd23
6 VS
9 DVdd
BCI24
5 HS
RCI26
GCI25
4 SCL
C10
100nF
C11
22µF
10kΩ
100nF
TEST28
ADCREF27
3 SDA
2 AGND
1 FILTER
R1
PWM outputs
4.7µF
10kΩ
100µH
Xtal
8 Mhz
L1
C8
1nF
2.2kΩ
Separate path for digitlal GND
GND
100pF
C14
R3
RGB outputs
L2
100µH
C12
100pF
R2
1k Ω
L3
C15
100nF
100pF
100µH
C16
VDD +5V
Fast blanking ouput
C14
1kΩ
R4
1kΩ
Beam current inputs
47µF
STV9432TAP
13 - APPLICATION DIAGRAM
Figure 15.
23/25
STV9432TAP
PACKAGE MECHANICAL DATA
28 PINS - PLASTIC MICROPACKAGE (SO)
Dimensions
A
a1
b
b1
C
c1
D
E
e
e3
F
L
S
24/25
6
Min.
Millimeters
Typ.
0.1
0.35
0.23
Max.
2.65
0.3
0.49
0.32
Min.
Inches
Typ.
0.004
0.014
0.009
0.5
Max.
0.104
0.012
0.019
0.013
0.020
45
17.7
10
18.1
10.65
0.697
0.394
1.27
16.51
7.4
0.4
0.713
0.419
0.050
0.65
7.6
1.27
8° (Max.)
0.291
0.016
0.299
0.050
STV9432TAP
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no
responsibility for the consequences of use of such information nor for any infringement of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change
witho ut notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics.
 2000 STMicroelectronics - All Rights Reserved
Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent.
Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C
Standard Specifications as defined by Philip s.
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25/25
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