PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODECS FEATURES • • • • • • • • • Monolithic 20-Bit ∆Σ ADC and DAC 16/20-Bit Input/Output Data Software Control: PCM3002 Hardware Control: PCM3003 Stereo ADC: – Single-Ended Voltage Input – Antialiasing Filter – 64× Oversampling – High Performance • THD+N: –86 dB • SNR: 90 dB • Dynamic Range: 90 dB Stereo DAC: – Single-Ended Voltage Output – Analog Low-Pass Filter – 64× Oversampling – High Performance • THD+N: –86 dB • SNR: 94 dB • Dynamic Range: 94 dB Special Features (PCM3002, PCM3003) – Digital De-Emphasis: 32 kHz, 44.1 kHz, 48 kHz – Power Down: ADC/DAC Independent Special Features (PCM3002) – Digital Attenuation (256 Steps) – Soft Mute – Digital Loopback – Four Alternative Audio Data Formats Sampling Rate: 4 kHz to 48 kHz Lch In Analog Front-End Rch In Delta-Sigma Modulator • • Single 3-V Power Supply Small Package: SSOP-24 APPLICATIONS • • • DVC Applications DSC Applications Portable/Mobile Audio Applications DESCRIPTION The PCM3002 and PCM3003 are low-cost, single-chip stereo audio codecs (analog-to-digital and digital-to-analog converters) with single-ended analog voltage input and output. The ADCs and DACs employ delta-sigma modulation with 64-times oversampling. The ADCs include a digital decimation filter, and the DACs include an 8-times oversampling digital interpolation filter. The DACs also include digital attenuation, de-emphasis, infinite zero detection, and soft mute to form a complete subsystem. The PCM3002 and PCM3003 operate with left-justified (ADC) and right-justified (DAC) formats, while the PCM3002 also supports other formats, including the I2S data format. The PCM3002 and PCM3003 provide a power-down mode that operates on the ADCs and DACs independently. The PCM3002 and PCM3003 are fabricated using a highly advanced CMOS process, and are available in a 24-pin SSOP package. The PCM3002 and PCM3003 are suitable for a wide variety of cost-sensitive consumer applications where good performance is required. The PCM3002 programmable functions are controlled by software. The PCM3003 functions, which are controlled by hardware, include de-emphasis, power-down, and audio data format selections. Digital Decimation Filter Digital Out * Lch Out Rch Out Low-Pass Filter and Output Buffer * PCM3002 Only Multilevel Delta-Sigma Modulator Digital Interpolation Filter Serial Interface and Mode Control Digital In Mode Control System Clock B0006-01 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2004, Texas Instruments Incorporated PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted PARAMETER CONDITIONS PCM3002E/3003E MIN TYP MAX UNITS DIGITAL INPUT/OUTPUT Input Logic VIH (1) (2) (3) VIL (1) (2) (3) IIN (2) IIN (1) (3) 0.7 VDD Input logic level 0.3 VDD ±1 Input logic current 100 VDC µA Output Logic VOH (4) VOL (4) IOUT = –1 mA Output logic level VOL (5) VDD – 0.3 IOUT = 1 mA 0.3 IOUT = 1 mA 0.3 VDC CLOCK FREQUENCY fs 4 (6) 44.1 48 256 fS 1.024 11.2896 12.288 384 fS 1.536 16.9344 18.432 512 fS 2.048 22.5792 24.576 Sampling frequency System clock frequency kHz MHz ADC CHARACTERISTICS Resolution 20 Bits DC Accuracy Gain mismatch, channelto-channel ±1 ±3 % of FSR Gain error ±2 ±5 % of FSR ±20 Gain drift ppm of FSR/°C Bipolar zero error High-pass filter bypassed (7) ±1.7 % of FSR Bipolar zero drift High-pass filter bypassed (7) ±20 ppm of FSR/°C VIN = –0.5 dB –86 VIN = –60 dB –28 Dynamic Performance (8) THD+N (2) (3) (4) (5) (6) (7) (8) 2 dB Dynamic range A-weighted 86 90 dB Signal-to-noise ratio A-weighted 86 90 dB 84 88 dB Channel separation (1) –80 Pins 7, 8, 17 and 18: RST, ML, MD, and MC for the PCM3002; PDAD, PDDA, DEM1, and DEM0 for PCM3003 (Schmitt-trigger input with 100-kΩ typical internal pulldown resistor) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt-trigger input) Pin 16: 20BIT for PCM3003 (Schmitt-trigger input, 100-kΩ typical internal pulldown resistor) Pin 12: DOUT Pin 16: ZFLG for PCM3002 (open-drain output) See Application Bulletin SBAA033 for information relating to operation at lower sampling frequencies. High-pass filter for offset cancel fIN = 1 kHz, using the System Two™ audio measurement system by Audio Precision™ in rms mode with 20-kHz LPF, 400-Hz HPF used for performance calculation. PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted PARAMETER CONDITIONS PCM3002E/3003E MIN TYP MAX UNITS 0.454 fS Hz Digital Filter Performance Pass band Stop band 0.583 fS Hz ±0.05 Pass-band ripple Stop-band attenuation –65 Delay time dB dB 17.4/fS s 0.019 fS mHz Voltage range 0.6 VCC Vp-p Center voltage 0.5 VCC VDC HPF frequency response –3 dB Analog Input Input impedance Antialiasing filter frequency response –3 dB 30 kΩ 150 kHz 20 Bits DAC CHARACTERISTICS Resolution DC Accuracy ±1 ±3 Gain error ±1 ±5 Gain drift ±20 Bipolar zero error ±2.5 % of FSR Bipolar zero drift ±20 ppm of FSR/°C Gain mismatch, channelto-channel % of FSR % of FSR ppm of FSR/°C Dynamic Performance (9) THD+N VOUT = 0 dB (full scale) –86 VOUT = –60 dB –32 –80 dB Dynamic range EIAJ, A-weighted 88 94 dB Signal-to-noise ratio EIAJ, A-weighted 88 94 dB 86 91 dB Channel separation Digital Filter Performance Pass band 0.445 fS Stop band 0.555 fS Hz ±0.17 Pass-band ripple Stop-band attenuation –35 Delay time Hz dB dB 11.1/fS s Voltage range 0.6 VCC Vp-p Center voltage 0.5 VCC VDC Analog Output Load impedance LPF frequency response (9) AC coupling f = 20 kHz 10 kΩ –0.16 dB fOUT = 1 kHz, using the System Two audio measurement system by Audio Precision in rms mode with 20-kHz LPF, 400-Hz HPF used for performance calculation. 3 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted PARAMETER CONDITIONS PCM3002E/3003E MIN TYP MAX UNITS –25°C to 85°C 2.7 3 3.6 VDC 0° C to 70°C (10) 2.4 3 3.6 VDC 24 mA 72 mW POWER SUPPLY REQUIREMENTS VCC, VDD Supply voltage Supply current Power dissipation Operation, VCC = VDD = 3 V 18 Power down, VCC = VDD = 3 V 50 Operation, VCC = VDD = 3 V 54 Power down (11), VCC = VDD = 3V 150 µA µW TEMPERATURE RANGE TA Operation –25 Tstg Storage –55 θJA Thermal resistance 85 125 °C °C °C/W 100 (10) Applies for voltages between 2.4 V and 2.7 V for 0°C to 70°C and 256 fS/512 fS operation (384 fS not available) (11) SYSCLK, BCKIN, and LRCIN are stopped. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE TYPE PACKAGE CODE PACKAGE MARKING PCM3002E 24-pin SSOP DB PCM3002E PCM3003E 24-pin SSOP DB PCM3003E ORDERING NUMBER TRANSPORT MEDIA QUANTITY PCM3002E Rails 58 PCM3002E/2K Tape and reel 2000 PCM3003E Rails 58 PCM3003E/2K Tape and reel 2000 ABSOLUTE MAXIMUM RATINGS Supply voltage VDD, VCC1, VCC2 Supply voltage differences GND voltage differences Digital input voltage Analog input voltage Power dissipation Input current (any pins except supplies) Operating temperature Storage temperature Lead temperature, soldering Package temperature (IR reflow, peak) 4 –0.3 V to 6.5 V ±0.1 V ±0.1 V –0.3 V to VDD + 0.3 V, < 6.5 V –0.3 V to VCC1, VCC2 + 0.3 V, < 6.5 V 300 mW ±10 mA –25°C to 85°C –55°C to 125°C 260°C, 5 s 235°C PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range MIN NOM MAX Analog supply voltage, VCC1, VCC2 2.7 3 3.6 Digital supply voltage, VDD 2.7 3 3.6 Analog input voltage, full scale (–0 dB) VCC = 3 V 1.8 Digital input logic family V V Vp-p CMOS System clock Digital input clock frequency 8.192 24.576 MHz 32 48 kHz Sampling clock Analog output load resistance 10 kΩ Analog output load capacitance 30 Digital output load capacitance 10 Operating free-air temperature, TA 1 2 3 4 5 6 7 8 9 10 11 12 pF pF –25 PCM3002 (TOP VIEW) VCC1 VCC1 VINR VREF1 VREF2 VINL RST ML SYSCLK LRCIN BCKIN DOUT UNIT 85 °C PCM3003 (TOP VIEW) 24 23 22 21 20 19 18 17 16 15 14 13 VCC2 AGND1 AGND2 VCOM VOUTR VOUTL MC MD ZFLG DIN VDD DGND VCC1 VCC1 VINR VREF1 VREF2 VINL PDAD PDDA SYSCLK LRCIN BCKIN DOUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC2 AGND1 AGND2 VCOM VOUTR VOUTL DEM0 DEM1 20BIT DIN VDD DGND P0004-02 PIN ASSIGNMENTS—PCM3002 (1) (2) NAME PIN I/O AGND1 23 – ADC analog ground DESCRIPTION AGND2 22 – DAC analog ground BCKIN 11 I Bit clock input (1) DGND 13 – Digital ground DIN 15 I Data input (1) DOUT 12 O Data output LRCIN 10 I Sample rate clock input (fs) (1) MC 18 I Bit clock for mode control (1) (2) MD 17 I Serial data for mode control (1) (2) ML 8 I Strobe pulse for mode control (1) (2) RST 7 I Reset, active LOW (1) (2) SYSCLK 9 I System clock input (1) VCC1 1, 2 – ADC analog power supply VCC2 24 – DAC analog power supply VCOM 21 – ADC/DAC common VDD 14 – Digital power supply Schmitt-trigger input With 100-kΩ typical internal pulldown resistor 5 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 PIN ASSIGNMENTS—PCM3002 (continued) (3) NAME PIN I/O VINL 6 I ADC analog input, Lch DESCRIPTION VINR 3 I ADC analog input, Rch VOUTL 19 O DAC analog output, Lch VOUTR 20 O DAC analog output, Rch VREF1 4 – ADC reference 1 VREF2 5 – ADC reference 2 ZFLG 16 O Zero flag output, active LOW (3) Open-drain output PIN ASSIGNMENTS—PCM3003 (1) (2) 6 NAME PIN I/O AGND1 23 – ADC analog ground DESCRIPTION AGND2 22 – DAC analog ground BCKIN 11 I Bit clock input (1) DEM0 18 I De-emphasis control 0 (1) (2) DEM1 17 I De-emphasis control 1 (1) (2) DGND 13 – Digital ground DIN 15 I Data input (1) DOUT 12 O Data output LRCIN 10 I Sample rate clock input (fs) (1) PDAD 7 I ADC power down, active LOW (1) (2) PDDA 8 I DAC power down, active LOW (1) (2) SYSCLK 9 I System clock input (1) VCC1 1, 2 – ADC analog power supply VCC2 24 – DAC analog power supply VCOM 21 – ADC/DAC common VDD 14 – Digital power supply VINL 6 I ADC analog input, Lch VINR 3 I ADC analog input, Rch VOUTL 19 O DAC analog output, Lch VOUTR 20 O DAC analog output, Rch VREF1 4 – ADC reference 1 VREF2 5 – ADC reference 2 20BIT 16 I 20-bit format select(1)(2) Schmitt-trigger input With 100-kΩ typical internal pulldown resistor PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted ADC SECTION 4 0.006 3 −0.5 dB 0.004 0 25 50 75 THD+N − Total Harm. Dist. + Noise at −0.5 dB − % 90 SNR 86 −25 88 0 25 50 75 TA − Free-Air Temperature − °C G002 Figure 1. Figure 2. THD+N vs SUPPLY VOLTAGE DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE 5 −60 dB 0.008 4 0.006 3 0.004 2 −0.5 dB 2.7 3.0 3.3 VCC − Supply Voltage − V Figure 3. 86 100 G001 0.010 2.4 90 92 88 1 100 TA − Free-Air Temperature − °C 0.002 2.1 Dynamic Range 92 3.6 1 3.9 94 94 92 Dynamic Range − dB 0.002 −25 2 94 92 Dynamic Range 90 90 SNR 88 86 2.1 SNR − Signal-to-Noise Ratio − dB −60 dB 0.008 94 88 2.4 2.7 3.0 3.3 3.6 VCC − Supply Voltage − V G003 SNR − Signal-to-Noise Ratio − dB 5 Dynamic Range − dB 0.010 THD+N − Total Harm. Dist. + Noise at −60 dB − % DYNAMIC RANGE and SNR vs TEMPERATURE THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N − Total Harm. Dist. + Noise at −0.5 dB − % THD+N vs TEMPERATURE 86 3.9 G004 Figure 4. NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 fS. 7 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted −60 dB 4 0.008 0.006 3 0.004 2 −0.5 dB 0.002 44.1 94 92 92 Dynamic Range 90 90 SNR 88 88 86 1 32 94 86 32 48 44.1 48 fS − Sampling Frequency − kHz fS − Sampling Frequency − kHz SNR − Signal-to-Noise Ratio − dB 5 Dynamic Range − dB 0.010 DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N − Total Harm. Dist. + Noise at −0.5 dB − % THD+N vs SAMPLING FREQUENCY G006 G005 Figure 5. Figure 6. THD+N vs TEMPERATURE DYNAMIC RANGE and SNR vs TEMPERATURE −60 dB 0.008 3 0.006 2 FS 0.004 0.002 −25 1 0 25 50 75 TA − Free-Air Temperature − °C Figure 7. 8 0 100 98 98 96 96 Dynamic Range 94 94 SNR 92 90 −25 92 0 25 50 75 TA − Free-Air Temperature − °C G007 Figure 8. SNR − Signal-to-Noise Ratio − dB 4 Dynamic Range − dB THD+N − Total Harm. Dist. + Noise at FS − % 0.010 THD+N − Total Harm. Dist. + Noise at −60 dB − % DAC SECTION 90 100 G008 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted 4 −60 dB 0.008 3 0.006 2 FS 0.004 1 0.002 2.1 2.4 2.7 3.0 3.3 3.6 98 98 96 96 Dynamic Range 94 94 SNR 92 92 90 2.1 0 3.9 2.4 2.7 3.0 3.3 3.6 90 3.9 VCC − Supply Voltage − V VCC − Supply Voltage − V G010 G009 Figure 9. SNR − Signal-to-Noise Ratio − dB THD+N − Total Harm. Dist. + Noise at FS − % 0.010 Dynamic Range − dB DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N vs SUPPLY VOLTAGE Figure 10. NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 fS. 3 −60 dB 384 fS 256 fS, 512 fS 0.006 2 384 fS FS 256 fS, 512 fS 0.004 1 0.002 0 32 44.1 Figure 11. 98 256 fS, 512 fS 96 96 SNR 94 94 Dynamic Range 384 fS 92 92 90 90 32 48 fS − Sampling Frequency − kHz 98 SNR − Signal-to-Noise Ratio − dB 0.008 4 Dynamic Range − dB THD+N − Total Harm. Dist. + Noise at FS − % 0.010 DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY and SYSTEM CLOCK THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N vs SAMPLING FREQUENCY and SYSTEM CLOCK 44.1 48 fS − Sampling Frequency − kHz G011 G012 Figure 12. 9 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted OUTPUT SPECTRUM ADCs OUTPUT SPECTRUM (–60 dB, N = 8192) 0 −20 −20 −40 −40 Amplitude − dB Amplitude − dB OUTPUT SPECTRUM (–0.5 dB, N = 8192) 0 −60 −80 −60 −80 −100 −100 −120 −120 −140 −140 0 5 10 15 20 25 0 5 f − Frequency − kHz 10 15 G013 Figure 14. THD+N vs SIGNAL LEVEL THD+N − Total Harmonic Distortion + Noise − % 100 10 1 0.1 0.01 −84 −72 −60 −48 −36 −24 −12 0 Signal Level − dB G017 Figure 15. 10 25 G015 Figure 13. 0.001 −96 20 f − Frequency − kHz PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted DACs OUTPUT SPECTRUM (–60 dB, N = 8192) −20 −20 −40 −40 Amplitude − dB 0 −60 −80 −60 −80 −100 −100 −120 −120 −140 −140 0 5 10 15 20 25 0 5 f − Frequency − kHz 10 15 20 25 f − Frequency − kHz G014 G016 Figure 16. Figure 17. THD+N vs SIGNAL LEVEL 100 THD+N − Total Harmonic Distortion + Noise − % Amplitude − dB OUTPUT SPECTRUM (0 dB, N = 8192) 0 10 1 0.1 0.01 0.001 −96 −84 −72 −60 −48 −36 −24 −12 0 Signal Level − dB G018 Figure 18. 11 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, DIN = BPZ, and VIN = BPZ, unless otherwise noted SUPPLY CURRENT ICC + IDD vs SUPPLY VOLTAGE ICC + IDD vs TEMPERATURE 25 2.0 ICC + IDD − mA ADC and DAC 15 1.5 ADC 10 1.0 DAC 5 0.5 2.5 20 ICC + IDD − mA 20 ICC + IDD: Power Down and Off − mA 2.5 15 1.5 ADC 10 1.0 DAC 5 0.5 Power Down and Off 0 2.1 2.4 2.7 3.0 3.3 Power Down and Off 3.6 0 −50 0 3.9 VCC − Supply Voltage − V −25 0 25 Figure 20. All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 fS. ICC + IDD vs SAMPLING FREQUENCY 20 ADC and DAC 19 512 fS ICC + IDD − mA 50 TA − Free-Air Temperature − °C G020 Figure 19. 18 256 fS 17 16 15 32 44.1 48 fS − Sampling Frequency − kHz Figure 21. 12 2.0 ADC and DAC ICC + IDD: Power Down and Off − mA 25 G021 75 0 100 G019 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted DECIMATION FILTER OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS 0 0 −20 Amplitude − dB Amplitude − dB −50 −100 −40 −60 −150 −80 −200 0 8 16 24 Normalized Frequency [× fS Hz] −100 0.0 32 0.2 0.4 0.6 0.8 Normalized Frequency [× fS Hz] G022 Figure 22. 1.0 G023 Figure 23. PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS 0.2 0 −1 −2 −3 −0.2 Amplitude − dB Amplitude − dB 0.0 −0.4 −0.6 −4 −5 −6 −7 −8 −0.8 −9 −1.0 0.0 0.1 0.2 0.3 0.4 Normalized Frequency [× fS Hz] Figure 24. 0.5 G024 −4.13 dB at 0.5 fS −10 0.45 0.47 0.49 0.51 0.53 Normalized Frequency [× fS Hz] 0.55 G025 Figure 25. 13 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted HIGH-PASS FILTER HIGH-PASS FILTER RESPONSE HIGH-PASS FILTER RESPONSE 0 0.2 −10 0.0 −20 Amplitude − dB Amplitude − dB −30 −40 −50 −60 −70 −80 −0.2 −0.4 −0.6 −0.8 −90 −100 0.0 −1.0 0.1 0.2 0.3 0.4 Normalized Frequency [× fS/1000 Hz] 0.5 0 1 2 3 4 Normalized Frequency [× fS/1000 Hz] G026 Figure 26. G027 Figure 27. ANTIALIASING FILTER ANTIALIASING FILTER OVERALL FREQUENCY RESPONSE ANTIALIASING FILTER PASS-BAND FREQUENCY RESPONSE 0.2 0 0.0 Amplitude − dB Amplitude − dB −10 −20 −30 −40 −0.2 −0.4 −0.6 −0.8 −50 −1.0 1 10 100 1k 10k 100k 1M 10M f − Frequency − Hz 1 10 100 1k G028 Figure 28. 14 10k 100k f − Frequency − Hz G029 Figure 29. PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted DIGITAL FILTER PASS-BAND RIPPLE CHARACTERISTICS (fS = 44.1 kHz) 0 0.00 −20 −0.20 −40 −0.40 Level − dB Level − dB OVERALL FREQUENCY CHARACTERISTICS (fS = 44.1 kHz) −60 −80 −0.60 −0.80 −100 −1.00 0 25k 50k 75k 100k 125k 150k 175k 0 5k f − Frequency − Hz 10k 15k 20k f − Frequency − Hz G030 G031 Figure 30. Figure 31. DE-EMPHASIS FILTER DE-EMPHASIS ERROR (32 kHz) 0.6 −2 0.4 −4 0.2 Error − dB Level − dB DE-EMPHASIS FREQUENCY RESPONSE (32 kHz) 0 −6 0.0 −8 −0.2 −10 −0.4 −12 −0.6 0 5k 10k 15k 20k 25k f − Frequency − Hz 0 3628 7256 G032 Figure 32. 10884 14512 f − Frequency − Hz G033 Figure 33. 15 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted DE-EMPHASIS ERROR (44.1 kHz) 0.6 −2 0.4 −4 0.2 Error − dB Level − dB DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz) 0 −6 0.0 −8 −0.2 −10 −0.4 −12 −0.6 0 5k 10k 15k 20k 25k 0 4999.8375 f − Frequency − Hz 9999.675 14999.5125 G034 G035 Figure 34. Figure 35. DE-EMPHASIS ERROR (48 kHz) 0 0.6 −2 0.4 −4 0.2 Error − dB Level − dB DE-EMPHASIS FREQUENCY RESPONSE (48 kHz) −6 0.0 −8 −0.2 −10 −0.4 −12 −0.6 0 5k 10k 15k 20k 25k f − Frequency − Hz 0 5442 10884 Figure 36. 16326 21768 f − Frequency − Hz G036 16 19999.35 f − Frequency − Hz G037 Figure 37. PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted ANALOG LOW-PASS FILTER INTERNAL ANALOG FILTER FREQUENCY RESPONSE (1 Hz–100 kHz) 20 0.15 0 0.10 −20 0.05 Level − dB Level − dB INTERNAL ANALOG FILTER FREQUENCY RESPONSE (1 Hz–10 MHz) −40 0.00 −60 −0.05 −80 −0.10 −100 −0.15 1 10 100 1k 10k 100k 1M 10M f − Frequency − Hz 1 10 100 1k G038 Figure 38. 10k 100k f − Frequency − Hz G039 Figure 39. 17 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 BLOCK DIAGRAM (+) VINL VREF1 VCOM VREF2 Analog Front-End Circuit (−) Decimation and High-Pass Filter Delta-Sigma Modulator LRCIN BCKIN Serial Data Interface ADC Reference DIN (−) VINR Analog Front-End Circuit VOUTL Analog Low-Pass Filter (+) Delta-Sigma Modulator Decimation and High-Pass Filter Multilevel Delta-Sigma Modulator Interpolation Filter 8× Oversampling DOUT MC(1)/DEM0(2) Mode Control Interface DAC VOUTR Analog Low-Pass Filter Multilevel Delta-Sigma Modulator MD(1)/DEM1(2) ML(1) 20BIT(2) Interpolation Filter 8× Oversampling Reset and Power Down PDDA(2) RST(1)/PDAD(2) Power Supply AGND2 VCC2 AGND1 VCC1 DGND VDD Clock Zero Detect(1) SYSCLK ZFLG(1) B0004-03 18 (1) MC, MD, ML, RST, and ZFLG are for PCM3002 only. (2) DEM0, DEM1, 20BIT, PDAD, and PDDA are for PCM3003 only. PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 1.0 µF + 3 VINR 30 kΩ − − (+) + + (−) 21 4.7 µF VCOM Delta-Sigma Modulator + 4 4.7 µF VREF1 + 5 4.7 µF VREF2 + VREF S0011-03 Figure 40. Analog Front-End (Single-Channel) PCM AUDIO INTERFACE The four-wire digital audio interface for the PCM3002/3003 comprises LRCIN (pin 10), BCKIN (pin 11), DIN (pin 15), and DOUT (pin 12). The PCM3002 can be used with any of the four input/output data formats (formats 0–3), while the PCM3003 can only be used with selected input/output formats (formats 0–1). For the PCM3002, these formats are selected through program register 3 in the software mode. For the PCM3003, data formats are selected by the 20BIT input (pin 16). Figure 41, Figure 42, and Figure 43 illustrate audio data input/output formats and timing. The PCM3002/3003 can accept 32, 48, or 64 bit clocks (BCKIN) in one clock of LRCIN. Only the 16-bit data format can be selected when 32-bit clocks/LRCIN are applied. 19 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 FORMAT 0: PCM3002/3003 DAC: 16-Bit, MSB-First, Right-Justified LRCIN Left-Channel Right-Channel BCKIN DIN 16 1 2 3 14 15 16 MSB 1 2 3 14 15 16 MSB LSB LSB ADC: 16-Bit, MSB-First, Left-Justified Left-Channel LRCIN Right-Channel BCKIN DOUT 1 2 3 14 15 16 MSB 1 LSB 2 3 1 14 15 16 MSB LSB FORMAT 1: PCM3002/3003 DAC: 20-Bit, MSB-First, Right-Justified LRCIN Left-Channel Right-Channel BCKIN DIN 20 1 2 3 18 19 20 MSB 1 2 3 18 19 20 MSB LSB LSB ADC: 20-Bit, MSB-First, Left-Justified Left-Channel LRCIN Right-Channel BCKIN DOUT 1 2 MSB 3 18 19 20 LSB 1 2 3 MSB 18 19 20 1 LSB T0016-04 Figure 41. Audio Data Input/Output Format 20 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 FORMAT 2: PCM3002 Only DAC: 20-Bit, MSB-First, Left-Justified Left-Channel LRCIN Right-Channel BCKIN DIN 1 2 3 18 19 20 MSB 1 LSB 2 3 1 18 19 20 MSB LSB ADC: 20-Bit, MSB-First, Left-Justified Left-Channel LRCIN Right-Channel BCKIN DOUT 1 2 3 18 19 20 MSB 1 LSB 2 3 1 18 19 20 MSB LSB FORMAT 3: PCM3002 Only DAC: 20-Bit, MSB-First, I2S Left-Channel LRCIN Right-Channel BCKIN DIN 1 2 3 18 19 20 MSB LSB 1 2 3 18 19 20 MSB LSB ADC: 20-Bit, MSB-First, I2S Left-Channel LRCIN Right-Channel BCKIN DOUT 1 2 MSB 3 18 19 20 LSB 1 2 3 MSB 18 19 20 LSB T0016-05 Figure 42. Audio Data Input/Output Format (PCM3002) 21 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 t(LRP) 0.5 VDD LRCIN t(BCL) t(BCH) t(LB) t(BL) 0.5 VDD BCKIN t(BCY) t(DIH) t(DIS) 0.5 VDD DIN t(BDO) t(LDO) 0.5 VDD DOUT T0021−01 BCKIN pulse cycle time t(BCY) 300 ns (min) BCKIN pulse duration, HIGH t(BCH) 120 ns (min) BCKIN pulse duration, LOW t(BCL) 120 ns (min) BCKIN rising edge to LRCIN edge t(BL) 40 ns (min) LRCIN edge to BCKIN rising edge t(LB) 40 ns (min) LRCIN pulse duration t(LRP) t(BCY) (min) DIN setup time t(DIS) 40 ns (min) DIN hold time t(DIH) 40 ns (min) DOUT delay time to BCKIN falling edge t(BDO) 40 ns (max) DOUT delay time to LRCIN edge t(LDO) 40 ns (max) Rising time of all signals t(RISE) 20 ns (max) Falling time of all signals t(FALL) 20 ns (max) Figure 43. Audio Data Input/Output Timing SYSTEM CLOCK The system clock for the PCM3002/3003 must be either 256 fS, 384 fS, or 512 fS, where fS is the audio sampling frequency. The system clock should be provided at the SYSCLK input (pin 9). The PCM3002/3003 also has a system-clock detection circuit that automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS. When a 384-fS or 512-fS system clock is used, the clock is divided to 256 fS automatically. The 256-fS clock is used to operate the digital filters and the delta-sigma modulators. Table 1 lists the relationship of typical sampling frequencies and system clock frequencies; Figure 44 illustrates the system clock timing. Table 1. System Clock Frequencies SAMPLING RATE FREQUENCY (kHz) 22 SYSTEM CLOCK FREQUENCY (MHz) 256 fs 384 fs 512 fs 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 t(SCKH) H 0.7 VDD SYSCLK 0.3 VDD L 1/256 fS, 1/384 fS, or 1/512 fS t(SCKL) T0005-05 Figure 44. System Clock Timing System clock pulse duration, HIGH t(SCKH) 12 ns (min) System clock pulse duration, LOW t(SCKL) 12 ns (min) POWER-ON RESET Both the PCM3002 and PCM3003 have internal power-on reset circuitry. Power-on reset occurs when the system clock (SYSCLK) is active and VDD > 2.2 V. For the PCM3003, the SYSCLK must complete a minimum of three complete cycles prior to VDD > 2.2 V to ensure proper reset operation. The initialization sequence requires 1024 SYSCLK cycles for completion, as shown in Figure 45. Figure 46 shows the state of the DAC and ADC outputs during and after the reset sequence. VDD 2.4 V 2.2 V 2.0 V Reset Reset Removal Internal Reset 3 Clocks Minimum 1024 System Clock Periods System Clock T0014-03 Figure 45. Internal Power-On Reset Timing 23 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 Reset Removal or Power Down Off Internal Reset or Power Down Reset Ready/Operation Power Down t(DACDLY1) (16384/fS) DAC VOUT GND VCOM (0.5 VCC) t(ADCDLY1) (18432/fS) ADC DOUT Zero Data Zero Data Normal Data(1) T0019-02 (1) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant) appears initially. Figure 46. DAC Output and ADC Output for Reset and Power Down EXTERNAL RESET The PCM3002 includes a reset input, RST (pin 7), while the PCM3003 uses both PDAD (pin 7) and PDDA (pin 8) for external reset control. As shown in Figure 47, the external reset signal must drive RST or PDAD and PDDA low for a minimum of 40 nanoseconds while SYSCLK is active in order to initiate the reset sequence. Initialization starts on the rising edge of RST or PDAD and PDDA, and requires 1024 SYSCLK cycles for completion. Figure 46 shows the state of the DAC and ADC outputs during and after the reset sequence. RST or PDAD and PDDA RST Pulse Duration t(RST) = 40 ns (min) t(RST) Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock T0015-02 Figure 47. External Forced-Reset Timing SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM The PCM3002/3003 operates with LRCIN synchronized to the system clock. The PCM3002/3003 does not require any specific phase relationship between LRCIN and the system clock, but there must be synchronization of LRCIN and the system clock. If the synchronization between the system clock and LRCIN changes more than 6 bit clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the DAC stops within 1/fS, and the analog output is forced to bipolar zero (0.5 VCC) until the system clock is resynchronized to LRCIN followed by t(DACDLY2) delay time. Internal operation of the ADC also stops within 1/fS, and the digital output codes are set to bipolar zero until resynchronization occurs followed by t(ADCDLY2) delay time. If LRCIN is synchronized within 5 or fewer bit clocks to the system clock, operation is normal. Figure 48 illustrates the effects on the output when synchronization is lost. Before the outputs are forced to bipolar zero (<1/fS seconds), the outputs are not defined and some noise may occur. During the transitions between normal data and undefined states, the output has discontinuities, which cause output noise. 24 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 Synchronization Lost State of Synchronization Synchronous Resynchronization Asynchronous Synchronous t(DACDLY2) (32/fS) Within 1/fS DAC VOUT Undefined Data Normal Data VCOM Normal Data (0.5 VCC) t(ADCDLY2) (32/fS) ADC DOUT Undefined Data Normal Data Normal Data(1) Zero Data T0020-03 (1) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant) appears initially. Figure 48. DAC Output and ADC Output for Loss of Synchronization ZERO FLAG OUTPUT: PCM3002 ONLY Pin 16 is an open-drain output, used as the infinite zero detection flag on the PCM3002 only. When input data is continuously zero for 65,536 BCKIN cycles, ZFLG is LOW; otherwise, ZFLG is in a high-impedance state. OPERATIONAL CONTROL The PCM3002 can be controlled in a software mode with a three-wire serial interface on MC (pin 18), MD (pin 17), and ML (pin 8). Table 2 indicates selectable functions, and Figure 49 and Figure 50 illustrate the control data input format and timing. The PCM3003 only allows for control of 16/20-bit data format, digital de-emphasis, and power-down control by hardware pins. Table 2. Selectable Functions (O = User Selectable; X = Not Available) ADC/DAC PCM3002 PCM3003 Audio data format FUNCTION ADC/DAC Four selectable formats Two selectable formats LRCIN polarity ADC/DAC O X Loopback control ADC/DAC O X Left-channel attenuation DAC O X Right-channel attenuation DAC O X Attenuation control DAC O X Infinite zero detection and mute DAC O X DAC output control DAC O X Soft mute control DAC O X De-emphasis (OFF, 32 kHz, 44.1 kHz, 48 kHz) DAC O O ADC power-down control ADC O O DAC power-down control DAC O O High-pass filter operation ADC O X 25 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 ML MC MD B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 T0023-01 Figure 49. Control Data Input Format t(MHH) t(MLH) t(MLS) 0.5 VDD ML t(MCL) t(MLL) t(MCH) MC 0.5 VDD t(MCY) LSB MD 0.5 VDD t(MDS) t(MDH) T0024-02 MC pulse cycle time t(MCY) 100 ns (min) MC pulse duration, LOW t(MCL) 40 ns (min) MC pulse duration, HIGH t(MCH) 40 ns (min) MD setup time t(MDS) 40 ns (min) MD hold time t(MDH) 40 ns (min) ML low-level time t(MLL) 40 ns + 1 SYSCLK(1) (min) ML high-level time t(MHH) 40 ns + 1 SYSCLK(1) (min) ML setup time(3) t(MLS) 40 ns (min) ML hold time(2) t(MLH) 40 ns (min) SYSCLK: 1/256 fS or 1/384 fS or 1/512 fS (1) SYSCLK: System clock cycle (2) MC rising edge of LSB to ML rising edge (3) ML rising edge to the next MC rising edge Figure 50. Control Data Input Timing 26 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 MAPPING OF PROGRAM REGISTERS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 REGISTER 1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 REGISTER 2 res res res res res A1 A0 PDAD ATC IZD OUT DEM1 DEM0 REGISTER 3 res res res res res A1 A0 res LOP res FMT1 FMT0 BYPS PDDA res res LRP MUT res NOTE: res indicates a reserved bit that should be set to 0. SOFTWARE CONTROL (PCM3002) The PCM3002 special functions are controlled using four program registers which are each 16 bits long. There are four distinct registers, with bits 9 and 10 determining which register is in use. Table 3 describes the functions of the four registers. Table 3. Functions of the Registers REGISTER NAME REGISTER BIT(S) BIT NAME Register 0 15–11 res 10–9 A[1:0] 8 LDL Register 1 Register 2 Register 3 DESCRIPTION Reserved, should be set to 0 Register address 00 DAC attenuation data load control for Lch 7–0 AL[7:0] DAC attenuation data for Lch 15–11 res Reserved, should be set to 0 10–9 A[1:0] 8 LDR 7–0 AR[7:0] DAC attenuation data for Rch 15–11 res Reserved, should be set to 0 Register address 01 DAC attenuation data load control for Rch 10–9 A[1:0] Register address 10 8 PDAD ADC power-down control 7 BYPS ADC high-pass filter bypass control 6 PDDA DAC power-down control 5 ATC DAC attenuation data mode control 4 IZD DAC infinite zero detection and mute control 3 OUT DAC output enable control 2–1 DEM[1:0] DAC de-emphasis control 0 MUT DAC Lch and Rch soft mute control 15–11 res 10–9 A[1:0] Reserved, should be set to 0 8–6 res Reserved, should be set to 0 5 LOP ADC/DAC digital loopback control Reserved, should be set to 0 Register address 11 4 res 3–2 FMT[1:0] 1 LRP ADC/DAC polarity of LR-clock selection 0 res Reserved, should be set to 0 ADC/DAC audio data format selection PROGRAM REGISTER 0 res: Bits 15–11: Reserved These bits are reserved and should be set to 0. 27 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 A[1:0] www.ti.com Bits 10, 9: Register address These bits define the address for register 0: A1 A0 0 0 REGISTER Register 0 LDL Bit 8: DAC attenuation data load control for left channel This bit is used to set analog outputs of the left and right channels simultaneously. The output level is controlled by AL[7:0] attenuation data when this bit is set to 1. When set to 0, the new attenuation data is ignored, and the output level remains at the previous attenuation level. The LDR bit in register 1 has the equivalent function as LDL. When either LDL or LDR is set to 1, the output levels of the left and right channels are controlled simultaneously. AL (7:0) Bits 7–0: DAC attenuation data for left channel AL7 and AL0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by: ATT = 20 × log10 (AL[7:0]/256) [dB], except AL[7:0] = FFh AL[7:0] ATTENUATION LEVEL 00h – ∞dB (mute) 01h –48.16 dB : : FEh –0.07 dB FFh 0 dB (default) PROGRAM REGISTER 1 res: Bits 15–11: Reserved These bits are reserved and should be set to 0. A[1:0] Bits 10, 9: Register address These bits define the address for register 1: A1 A0 0 1 REGISTER Register 1 LDR Bit 8: DAC attenuation data load control for right channel This bit is used to set analog outputs of the left and right channels simultaneously. The output level is controlled by AR[7:0] attenuation data when this bit is set to 1. When set to 0, the new attenuation data is ignored, and the output level remains at the previous attenuation level. The LDL bit in register 0 has the equivalent function as LDR. When either LDL or LDR is set to 1, the output levels of the left and right channels are controlled simultaneously. AR[7:0] Bits 7–0: DAC attenuation data for right channel AR7 and AR0 are the MSB and LSB, respectively. ATT = 20 × log10 (AR[7:0]/256) [dB], except AR[7:0] = FFh AR[7:0] ATTENUATION LEVEL 00h – ∞dB (mute) 01h –48.16 dB : : FEh –0.07 dB FFh 0 dB (default) PROGRAM REGISTER 2 res: 28 Bits 15–11: Reserved These bits are reserved and should be set to 0. PCM3002 PCM3003 www.ti.com A[1:0] SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 Bits 10, 9: Register address These bits define the address for register 2: A1 A0 1 0 PDAD: PDAD REGISTER Register 2 Bit 8: ADC power-down control This bit places the ADC section in the lowest power-consumption mode. The ADC operation is stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC power-down mode enable. Figure 46 illustrates the ADC DOUT response for ADC power-down ON/OFF. This does not affect the DAC operation. DAC POWER-DOWN STATUS 0 Power-down mode disabled (default) 1 Power-down mode enabled BYPS: BYPS Bit 7: ADC high-pass filter bypass control This bit enables or disables the high-pass filter for the ADC. FILTER BYPASS STATUS 0 High-pass filter enabled (default) 1 High-pass filter disabled (bypassed) PDDA: PDDA Bit 6: DAC power-down control This bit places the DAC section in the lowest power-consumption mode. The DAC operation is stopped by cutting the supply current to the DAC section, and VOUT is fixed to GND during DAC power-down mode enable. Figure 46 illustrates the DAC VOUT response for DAC power-down ON/OFF. This does not affect the ADC operation. ADC POWER-DOWN STATUS 0 Power-down mode disabled (default) 1 Power-down mode enabled ATC: Bit 5: DAC attenuation data mode control When set to 1, the register 0 attenuation data can be used for both DAC channels. In this case, the register 1 attenuation data is ignored. ATC ATTENUATION CONTROL 0 Individual channel attenuation data control (default) 1 Common channel attenuation data control IZD: Bit 4: DAC infinite zero detection and mute control This bit enables the infinite zero detection circuit in the PCM3002. When enabled, this circuit disconnects the analog output amplifier from the delta-sigma DAC when the input is continuously zero for 65,536 consecutive cycles of BCKIN. IZD INFINITE ZERO DETECT STATUS 0 Infinite zero detection and mute control disabled (default) 1 Infinite zero detection and mute control enabled OUT: Bit 3: DAC output enable control When set to 1, the outputs are forced to VCC/2 (bipolar zero). In this case, all registers in the PCM3002 hold the present data. Therefore, when set to 0, the outputs return to the previous programmed state. OUT DAC OUTPUT STATUS 0 DAC outputs enabled (default normal operation) 1 DAC outputs disabled (forced to BPZ) 29 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 DEM[1:0]: Bits 2, 1: DAC de-emphasis control These bits select the de-emphasis mode as shown below: DEM1 DEM0 0 0 De-emphasis 44. 1 kHz ON 0 1 De-emphasis OFF (default) 1 0 De-emphasis 48 kHz ON 1 1 De-emphasis 32 kHz ON MUT: DE-EMPHASIS STATUS Bit 0: DAC soft mute control When set to 1, both left- and right-channel DAC outputs are muted at the same time. This muting is done by attenuating the data in the digital filter, so there is no audible click noise when soft mute is turned on. MUT MUTE STATUS 0 Mute disabled (default) 1 Mute enabled PROGRAM REGISTER 3 res: Bits 15–11: Reserved These bits are reserved and should be set to 0. A[1:0] Bits 10, 9: Register address These bits define the address for register 3: A1 A0 1 1 REGISTER Register 3 res: Bits 8–6: Reserved These bits are reserved and should be set to 0. LOP: Bit 5: ADC to DAC loopback control When this bit is set to 1, the ADC audio data is sent directly to the DAC. The data format defaults to I2S; DOUT is still available in loopback mode. LOP LOOPBACK STATUS 0 Loopback disabled (default) 1 Loopback enabled res: Bit 4: Reserved This bit is reserved and should be set to 0. FMT[1:0] Bits 3–2: Audio data format select These bits determine the input and output audio data formats. FMT1 FMT0 0 0 16-bit, MSB-first, right-justified 16-bit, MSB-first, left-justified Format 0 (default) 0 1 20-bit, MSB-first, right-justified 20-bit, MSB-first, left-justified Format 1 1 0 20-bit, MSB-first, left-justified 20-bit, MSB-first, left-justified Format 2 1 1 20-bit, MSB-first, I2S 20-bit, MSB-first, I2S Format 3 LRP: ADC DATA FORMAT Bit 1: ADC to DAC LRCIN polarity select Polarity of LRCIN applies only to formats 0 through 2. LRP 30 DAC DATA FORMAT LEFT/RIGHT POLARITY 0 Left channel is H, right channel is L (default). 1 Left channel is L, right channel is H. NAME PCM3002 PCM3003 www.ti.com res: SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 Bit 0: Reserved This bit is reserved and should be set to 0. PCM3003 DATA FORMAT CONTROL The PCM3003 has hardware functional control using PDAD (pin 7) and PDDA (pin 8) for power-down control; DEM0 (pin 18) and DEM1 (pin 17) for de-emphasis; and 20BIT (pin 16) for 16/20-bit format selection. Power-Down Control (Pin 7 and Pin 8) Both the ADC and DAC power-down control pins place the ADC or DAC section in the lowest power-consumption mode. The ADC/DAC operation is stopped by cutting the supply current to the ADC/DAC section. DOUT is fixed to zero during ADC power-down mode enable and VOUT is fixed to GND during DAC power-down mode enable. Figure 46 illustrates the ADC and DAC output response for power-down ON/OFF. PDAD PDDA Low Low Reset (ADC/DAC power down enabled) POWER DOWN Low High ADC power-down/DAC operates High Low ADC operates/DAC power down High High ADC and DAC normal operation De-Emphasis Control (Pin 17 and Pin 18) DEM0 (pin 18) and DEM1 (pin 17) are used as de-emphasis control pins. DEM1 DEMO Low Low De-emphasis enabled for 44.1 kHz DE-EMPHASIS Low High De-emphasis disabled High Low De-emphasis enabled for 48 kHz High High De-emphasis enabled for 32 kHz 20BIT Audio Data Selection (Pin 16) 20BIT Low FORMAT ADC: 16-bit MSB-first, left-justified DAC: 16-bit MSB-first, right-justified High ADC: 20-bit MSB-first, left-justified DAC: 20-bit MSB-first, right-justified 31 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com APPLICATION AND LAYOUT CONSIDERATIONS POWER-SUPPLY BYPASSING The digital and analog power supply lines to PCM3002/3003 should be bypassed to the corresponding ground pins with both 0.1-µF ceramic and 10-µF tantalum capacitors as close to the device pins as possible. Although the PCM3002/3003 has three power-supply lines to optimize dynamic performance, the use of one common power supply is generally recommended to avoid unexpected latch-up or pop noise due to power-supply sequencing problems. If separate power supplies are used, back-to-back diodes are recommended to avoid latch-up problems. GROUNDING In order to optimize the dynamic performance of the PCM3002/3003, the analog and digital grounds are not connected internally. The PCM3002/3003 performance is optimized with a single ground plane for all returns. It is recommended to tie all PCM3002/3003 ground pins to the analog ground plane using low-impedance connections. The PCM3002/3003 should reside entirely over this plane to avoid coupling high-frequency digital switching noise into the analog ground plane. VOLTAGE INPUT A tantalum or aluminum electrolytic capacitor, between 1 µF and 10 µF, is recommended as an ac-coupling capacitor at the inputs. Combined with the 30-kΩ characteristic input impedance, a 1-µF coupling capacitor establishes a 5.3-Hz cutoff frequency for blocking dc. The input voltage range can be increased by adding a series resistor on the analog input line. This series resistor, when combined with the 30-kΩ input impedance, creates a voltage divider and enables larger input ranges. VREF INPUTS A 4.7-µF to 10-µF tantalum capacitor is recommended between VREF1, VREF2, and AGND1 to ensure low source impedance for the ADC references. These capacitors should be located as close as possible to the reference pins to reduce dynamic errors on the ADC reference. VCOM INPUT A 4.7-µF to 10-µF tantalum capacitor is recommended between VCOM and AGND1 to ensure low source impedance of the ADC and DAC common voltage. This capacitor should be located as close as possible to the VCOM pin to reduce dynamic errors on the dc common-mode voltage. SYSTEM CLOCK The quality of the system clock can influence dynamic performance of both the ADC and DAC in the PCM3002/3003. The duty cycle and jitter at the system-clock input pin should be carefully managed. When power is supplied to the part, the system clock, bit clock (BCKIN), and word clock (LCRIN) also must be supplied simultaneously. Failure to supply the audio clocks results in a power-dissipation increase of up to three times normal dissipation and can degrade long-term reliability if the maximum power-dissipation limit is exceeded. RESET CONTROL If capacitors larger than 22 µF are used on VREF and VCOM, external reset control (RST = low for the PCM3002, PDAD = low and PDDA = low for the PCM3003) is required after the VREF, VCOM transient response is settled. EXTERNAL MUTE CONTROL For power-down ON/OFF control without click noise, which is generated by a DC level change on the DAC output, use of the external mute control is recommended. The control sequence, which is external mute ON, codec power-down ON, SYSCLK stop and resume if necessary, codec power-down OFF, and external mute OFF is recommended. TYPICAL CONNECTION DIAGRAM A typical connection diagram for the PCM3002/3003 is shown in Figure 51. 32 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 +3 V Analog VCC 0.1 µF and 10 µF(1) + Rch In PCM3002/3003 1 µF(3) + 1 4.7 µF(2) + 4.7 µF(2) + µF(3) + Lch In VCC2 24 2 VCC1 AGND1 23 3 VINR AGND2 22 4 VREF1 VCOM 21 5 VREF2 VOUTR 20 6 VINL SYSCLK Audio Interface 1 VCC1 VOUTL 19 4.7 µF(2) + 4.7 µF(4) + 4.7 µF(4) Rch Out(5) + Lch Out(5) 7 RST/PDAD MC/DEM0 18 MC(6)/DEM0(7) 8 ML/PDDA MD/DEM1 17 MD(6)/DEM1(7) 9 SYSCLK ZFLG/20BIT 16 L/R CLK 10 LRCIN DIN 15 BIT CLK 11 BCKIN VDD 14 DGND 13 DATA OUT 0.1 µF and 10 µF(1) + 12 DOUT ZFLG(6)/20BIT(7) 10 kΩ Control Interface 0.1 µF and 10 µF(1) DATA IN ML(6)/PDDA(7) RST(6)/PDAD(7) S0014-01 (1) 0.1-µF ceramic and 10-µF tantalum, typical, depending on power supply quality and pattern layout (2) 4.7-µF, typical, gives settling time with 30-ms (4.7 µF × 6.4 kΩ) time constant in the power ON and power-down OFF periods. (3) 1-µF, typical, gives 5.3-Hz cutoff frequency for the input HPF in normal operation and gives settling time with 30-ms (1 µF × 30 kΩ) time constant in the power ON and power-down OFF periods. (4) 4.7-µF, typical, gives 3.4-Hz cutoff frequency for the output HPF in normal operation and gives settling time with 47-ms (4.7 µF × 10 kΩ) time constant in the power ON and power-down OFF periods. (5) Post low-pass filter with RIN > 10 kΩ, depending on system performance requirements (6) MC, MD, ML, ZFLG, RST, and 10-kΩ pullup resistor are for the PCM3002. (7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003. Figure 51. Typical Connection Diagram for PCM3002/3003 33 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 THEORY OF OPERATION ADC SECTION The PCM3002/3003 ADC consists of two reference circuits, a stereo single-to-differential converter, a fully differential fifth-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The block diagram in this data sheet illustrates the architecture of the ADC section, Figure 40 shows the single-to-differential converter, and Figure 52 illustrates the architecture of the fifth-order delta-sigma modulator and transfer functions. An internal reference circuit with three external capacitors provides all reference voltages required by the ADC, which defines the full-scale range for the converter. The internal single-to-differential voltage converter saves the space and extra parts needed for the external circuitry required by many delta-sigma converters. The internal full-differential signal processing architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at a 64× oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying antialias filtering requirements. The fifth-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels. The 64-fS, one-bit data stream from the modulator is converted to 1-fS, 16/20-bit data words by the decimation filter, which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed by a high-pass filter function contained within the decimation filter. DAC SECTION The delta-sigma DAC section of the PCM3002/3003 is based on a 5-level amplitude quantizer and a third-order noise shaper. This section converts the oversampled input data to a 5-level delta-sigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure 53. This 5-level delta-sigma modulator has the advantage of improved stability and reduced clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8× interpolation filter is 64 fS for a 256-fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 54. Analog In X(z) + − 1st SW-CAP Integrator + − 2nd SW-CAP Integrator + 3rd SW-CAP Integrator + + + + − 4th SW-CAP Integrator + 5th SW-CAP Integrator + H(z) + Qn(z) Digital Out Y(z) + Comparator 1-Bit DAC Y(z) = STF(z) * X(z) + NTF(z) * Qn(z) Signal Transfer Function STF(z) = H(z) / [1 + H(z)] Noise Transfer Function NTF(z) = 1 / [1 + H(z)] B0005-01 Figure 52. Simplified Fifth-Order Delta-Sigma Modulator 34 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 THEORY OF OPERATION (continued) In 8 fS 21-Bit + + + Z−1 − + − + + Z−1 + + Z−1 + 5-Level Quantizer 4 3 Out 64 fS 2 1 0 B0008-01 Figure 53. Five-Level Delta-Sigma Modulator Block Diagram 0 −10 −20 −30 −40 Gain − dB −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 0 5 10 15 20 25 30 f − Frequency − kHz G040 Figure 54. Quantization Noise Spectrum 35 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCM3002E ACTIVE SSOP DB 24 PCM3002E/2K ACTIVE SSOP DB PCM3002E/2KG4 ACTIVE SSOP PCM3002EG ACTIVE PCM3002EG/2K 58 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SSOP DB 24 58 Pb-Free (RoHS) CU SNBI Level-2-260C-1 YEAR ACTIVE SSOP DB 24 2000 Pb-Free (RoHS) CU SNBI Level-2-260C-1 YEAR PCM3002EG/2KE6 ACTIVE SSOP DB 24 2000 Pb-Free (RoHS) CU SNBI Level-2-260C-1 YEAR PCM3002EG4 ACTIVE SSOP DB 24 58 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM3002EGE6 ACTIVE SSOP DB 24 58 Pb-Free (RoHS) CU SNBI Level-2-260C-1 YEAR PCM3003E ACTIVE SSOP DB 24 58 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM3003E/2K ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM3003E/2KG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM3003EG4 ACTIVE SSOP DB 24 CU NIPDAU Level-1-260C-UNLIM 58 Green (RoHS & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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