www.fairchildsemi.com FAN5234 Mobile-Friendly PWM/PFM Controller Features General Description • Wide input voltage range (2 to 24V) for Mobile systems • Excellent dynamic response with Voltage Feed-Forward and Average Current Mode control • Lossless current sensing on low-side MOSFET or precision over-current using sense resistor • VCC Under-voltage Lockout • Power-Good Signal • Light load Hysteretic mode maximizes efficiency • QSOP16, TSSOP16 • 300Khz or 600Khz operation The FAN5234 PWM controller provides high efficiency and regulation with an adjustable output from 0.9V to 5.5V that are required to power I/O, chip-sets, memory banks or peripherals in high-performance notebook computers, PDAs and Internet appliances. Synchronous rectification and hysteretic operation at light loads contribute to a high efficiency over a wide range of loads. The hysteretic mode of operation can be disabled if PWM mode is desired for all load levels. Efficiency is even further enhanced by using MOSFET’s RDS(ON) as a current sense component. Applications Feed-forward ramp modulation, average current mode control, and internal feedback compensation provide fast response to load transients. The FAN5234 monitors these outputs and generates a PGOOD (power good) signal when the soft-start is completed and the output is within ±10% of its set point. A built-in over-voltage protection prevents the output voltage from going above 120% of the set point. Normal operation is automatically restored when the overvoltage conditions go away. Under-voltage protection latches the chip off when the output drops below 75% of its set value after the soft-start sequence is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the lower MOSFET. • Mobile PC regulator • Hand-Held PC power Typical Application VIN (BATTERY) = 2 to 24V VIN C1 1 VCC +5 11 15 BOOT C4 Q1A FAN5234 R5 14 ILIM EN SS1 C3 +5 FPWM R4 AGND PGOOD 4 13 16 +5 C5 HDRV L1 SW 10 9 12 8 6 2 5 LDRV [email protected] C6 Q1B 3 7 C2 D1 R3 R1 PGND ISNS R2 VSEN VOUT Figure 1. 1.8V Output Regulator (see Table 2, page 12 for BOM) REV. 1.0.10 5/3/04 FAN5234 PRODUCT SPECIFICATION Pin Configurations VIN PGOOD EN ILIM VOUT VSEN SS AGND 1 2 16 15 FPWM 3 4 14 13 HDRV 12 11 ISNS 10 9 LDRV 5 6 7 8 FAN5234 BOOT SW VCC PGND QSOP-16 or TSSOP-16 θJA = 112°C/W Pin Definitions Pin Number Pin Name Pin Function Description 1 VIN Input Voltage. Connect to main input power source (battery). Also used to program operating frequency for low input voltage operation. See Table 1. 2 PGOOD Power Good Flag. An open-drain output that will pull LOW when VSEN is outside of a ±10% range of the 0.9V reference. 3 EN ENABLE. Enables operation when pulled to logic high. Toggling EN will also reset the regulator after a latched fault condition. This is a CMOS inputs whose state is indeterminate if left open. Current Limit. A resistor from this pin to GND sets the current limit. 4 ILIM 5 VOUT Output Voltage. Connect to output voltage. Used for regulation to ensure a smooth transitions during mode changes. When VOUT is expected to exceed VCC, tie this pin to VCC. 6 VSEN Output Voltage Sense. The feedback from the output. Used for regulation as well as PGOOD, under-voltage, and over-voltage protection and monitoring. 7 SS Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization. During initialization, this pin is charged with a 5µA current source. 8 AGND Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. 9 PGND Power Ground. The return for the low-side MOSFET driver. Connect to source of lowside MOSFET. 10 LDRV Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET. 11 VCC VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling). 12 ISNS Current Sense input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. 13 SW 14 HDRV High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET. 15 BOOT BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 2. 16 FPWM Forced PWM mode. When logic HIGH, inhibits the regulator from entering hysteretic mode. REV. 1.0.10 5/3/04 Switching node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain. 2 FAN5234 PRODUCT SPECIFICATION Absolute Maximum Ratings Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Parameter Min. Typ. Max. Units VCC Supply Voltage: 6.5 V VIN 27 V BOOT, SW, ISNS, HDRV 33 V BOOT to SW 6.5 V All Other Pins –0.3 VCC+0.3 V Junction Temperature (TJ) –10 150 °C Storage Temperature –65 150 °C 300 °C Units Lead Soldering Temperature, 10 seconds Recommended Operating Conditions Parameter Min. Typ. Max. Supply Voltage VCC 4.75 5 5.25 V Supply Voltage VIN 5 24 V –10 85 °C Ambient Temperature (TA ) REV. 1.0.10 5/3/04 Conditions 3 PRODUCT SPECIFICATION FAN5234 Electrical Specifications Recommended operating conditions, unless otherwise noted. Parameter Power Supplies VCC Current VIN Current - Sinking VIN Current - Sourcing VIN Current - Shut-down UVLO Threshold Oscillator Frequency Ramp Amplitude, pk–pk Ramp Amplitude, pk–pk Ramp Offset Ramp / VIN Gain Ramp / VIN Gain Reference and Soft Start Internal Reference Voltage Soft Start current (ISS) Soft Start Complete Threshold PWM Converter Load Regulation VSEN Bias Current VOUT pin input impedance Under-voltage Shutdown ISNS Over-Current threshold Over-voltage threshold Output Driver HDRV Output Resistance Conditions 4 Typ. Max. Units 850 1300 µA 5 20 15 15 30 20 1 4.75 4.5 0.5 µA µA µA µA V V V 345 690 KHz KHz V V V LDRV, HDRV Open, VSEN forced above regulation point Shut-down (EN=0) VIN pin = input voltage source VIN pin = GND 10 7 Rising VCC Falling Hysteresis 4.3 4.1 0.1 4.55 4.27 VIN > 5V VIN = 0V VIN = 16V VIN < 5V 255 510 300 600 2 1.25 0.5 VIN > 3V 1V < VIN < 3V 125 250 0.891 at start-up IOUT from 0 to 3A, VIN from 2 to 24V as % of set point. 2µS noise filter RILIM = 68.5KΩ. See Figure 4 as % of set point. 2µS noise filter Sourcing Sinking LDRV Output Resistance Sourcing Sinking PGOOD (Power Good Output) and Control pins Lower Threshold as % of set point, 2µS noise filter Upper Threshold PGOOD Output Low Leakage Current Soft Start Voltage when PGOOD Enabled EN, FPWM Inputs Input High Input Low Min. as % of set point, 2µS noise filter IPGOOD = 4mA VPULLUP = 5V 0.9 mV/V mV/V 0.909 µA V 5 1.5 -1 50 40 70 115 113 V 80 55 75 144 +1 120 65 80 172 120 % nA KΩ % µA % 8 3.2 8 1.5 15 4 15 2.4 Ω Ω Ω Ω 86 92 % 110 115 0.5 1 % V µA V 1.5 2 0.8 V V REV. 1.0.10 5/3/04 FAN5234 PRODUCT SPECIFICATION 5V VDD CBOOT BOOT EN VIN POR/UVLO Q1 FPWM FPWM HDRV SS HYST HYST OVP ADAPTIVE GATE CONTROL LOGIC VIN OU T COUT PGND S PWM R S/H PWM/HYST PWM RAMP ILIM det. VSEN L LDRV CLK Q ISNS RSENSE CURRENT PROCESSING DUTY CYCLE CLAMP EA MODE Σ IOU T ILIM SS RILIM VREF PGOOD Q2 VDD RAMP OSC VOUT SW Reference and Soft Start PWM/HYST REF2 Figure 2. IC Block Diagram Circuit Description Overview The FAN5234 is a PWM controller intended for low voltage power applications in modern notebook, desktop, and sub-notebook PCs. The output voltage of the controller can be set in the range of 0.9V to 5.5V by an external resistor divider. The synchronous buck converter can operate from either an unregulated DC source (such as a notebook battery) with voltage ranging from 2V to 24V, or from a regulated system rail. In either mode of operation the IC is biased from a +5V source. The PWM modulator uses an average current mode control with input voltage feed-forward for simplified feedback loop compensation and improved line regulation. The controller includes integrated feedback loop compensation that dramatically reduces the number of external components. Depending on the load level, the converter can operate either in fixed frequency PWM mode or in a hysteretic mode. Switch-over from PWM to hysteretic mode improves the converters' efficiency at light loads and prolongs battery run time. In hysteretic mode, a comparator is synchronized to the main clock that allows seamless transition between the operational modes and reduced channel-to-channel interaction. REV. 1.0.10 5/3/04 The hysteretic mode of operation can be inhibited independently using the FPWM pin if variable frequency operation is not desired. Oscillator Table 1. Converter Operating modes Mode FSW (Khz) Converter Power VIN Pin Battery 300 2 to 24V Battery (>5V) Fixed 300 300 < 5.5V Fixed 100KΩ to GND Fixed 600 600 < 5.5V Fixed GND When VIN is from the battery, the oscillator's ramp amplitude is proportional to VIN, providing voltage feed-forward control for improved loop response. When in either of the Fixed modes, oscillator's ramp amplitude is fixed. The operating frequency is then determined according to the connection on the VIN pin (Table 1). Initialization and Soft Start Assuming EN is high, FAN5234 is initialized when VCC exceeds the rising UVLO threshold. Should VCC drop below the UVLO threshold, an internal Power-On Reset function disables the chip. 5 PRODUCT SPECIFICATION FAN5234 The voltage at the positive input of the error amplifier is limited by the voltage at the SS pin which is charged with a 5mA current source. Once CSS has charged to VREF (0.9V) the output voltage will be in regulation. The time it takes SS to reach 0.9V is: 0.9 × C SS T 0.9 = ---------------------5 lower MOSFETs are turned off. The SW node will ‘ring’ based on the output inductor and the parasitic capacitance on the SW node and settle out at the value of the output voltage. The boundary value of inductor current, where current becomes discontinuous, can be estimated by the following expression. (1) ( V IN – V OUT )V OUT I LOAD ( DIS ) = -------------------------------------------------2F SW L OUT V IN where T0.9 is in seconds if CSS is in µF. When SS reaches 1.5V, the Power Good outputs are enabled and hysteretic mode is allowed. The converter is forced into PWM mode during soft start. (2) Hysteretic Mode Conversely, the transition from Hysteretic mode to PWM mode occurs when the SW node is negative for 8 consecutive cycles. Operation Mode Control The mode-control circuit changes the converter’s mode of operation from PWM to Hysteretic and visa versa, based on the voltage polarity of the SW node when the lower MOSFET is conducting and just before the upper MOSFET turns on. For continuous inductor current, the SW node is negative when the lower MOSFET is conducting and the converters operate in fixed-frequency PWM mode as shown in Figure 3. This mode of operation achieves high efficiency at nominal load. When the load current decreases to the point where the inductor current flows through the lower MOSFET in the ‘reverse’ direction, the SW node becomes positive, and the mode is changed to hysteretic, which achieves higher efficiency at low currents by decreasing the effective switching frequency. A sudden increase in the output current will also cause a change from hysteretic to PWM mode. This load increase causes an instantaneous decrease in the output voltage due to the voltage drop on the output capacitor ESR. If the load causes the output voltage (as presented at VSEN) to drop below the hysteretic regulation level (20mV below VREF), the mode is changed to PWM on the next clock cycle. In hysteretic mode, the PWM comparator and the error amplifier that provide control in PWM mode are inhibited and the hysteretic comparator is activated. In hysteretic mode the low side MOSFET is operated as a synchronous rectifier, where the voltage across (VDS(ON)) it is monitored, and it is switched off when VDS(ON) goes positive (current flowing back from the load) allowing the diode to block reverse conduction. To prevent accidental mode change or "mode chatter" the transition from PWM to Hysteretic mode occurs when the SW node is positive for eight consecutive clock cycles (see Figure 3). The polarity of the SW node is sampled at the end of the lower MOSFET's conduction time. At the transition between PWM and hysteretic mode both the upper and VCORE PWM Mode IL Hysteretic Mode 0 1 2 3 4 5 6 7 8 VCORE IL Hysteretic Mode 0 1 2 3 PWM Mode 4 5 6 7 8 Figure 3. Transitioning between PWM and Hysteretic Mode 6 REV. 1.0.10 5/3/04 FAN5234 PRODUCT SPECIFICATION feedback loop. For stable operation, the voltage induced by the current feedback at the PWM comparator input should be set to 30% of the ramp amplitude at maximum load currrent and line voltage. The following expression estimates the recommended value of RSENSE as a function of the maximum load current (ILOAD(MAX)) and the value of the MOSFET’s RDS(ON): The hysteretic comparator causes HDRV turn-on when the output voltage (at VSEN) falls below the lower threshold (10mV below VREF) and terminates the PFM signal when VSEN rises over the higher threshold (5mV above VREF). The switching frequency is primarily a function of: 1. Spread between the two hysteretic thresholds 2. ILOAD 3. Output Inductor and Capacitor ESR I LOAD ( MAX ) × R DS ( ON ) × 4.1K - – 100 R SENSE = ----------------------------------------------------------------------------30% × 0.125 × V IN ( MAX ) A transition back to PWM (Continuous Conduction Mode or CCM) mode occurs when the inductor current rises sufficiently to stay positive for 8 consecutive cycles. This occurs when: (4a) RSENSE must, however, be kept higher than: I LOAD ( MAX ) × R DS ( ON ) - – 100 R SENSE = ----------------------------------------------------------150µA (4b) Setting the Current Limit ∆V HYSTERESIS I LOAD ( CCM ) = -------------------------------------2 ESR (3) A ratio of ISNS is also compared to the current established when a 0.9 V internal reference drives the ILIM pin: where ∆VHYSTERESIS = 15mV and ESR is the equivalent series resistance of COUT. ( 100 + R SENSE ) 11.2 R ILIM = ---------------- × ---------------------------------------R DS ( ON ) I LIMIT Because of the different control mechanisms, the value of the load current where transition into PWM operation takes place is typically higher compared to the load level at which transition into hysteretic mode occurs. Hysteretic mode can be disabled by setting the FPWM pin HIGH. Current Processing Section The following discussion refers to Figure 4. The current through RSENSE resistor (ISNS) is sampled shortly after Q2 is turned on. That current is held, and summed with the output of the error amplifier. This effectively creates a current mode control loop. The resistor connected to ISNS pin (RSENSE) sets the gain in the current (5) Since the tolerance on the current limit is largely dependent on the ratio of the external resistors it is fairly accurate if the voltage drop on the Switching Node side of RSENSE is an accurate representation of the load current. When using the MOSFET as the sensing element, the variation of RDS(ON) causes proportional variation in the ISNS. This value not only varies from device to device, but also has a typical junction temperature coefficient of about 0.4%/°C (consult the MOSFET datasheet for actual values), so the actual current limit set point will decrease propotional to increasing MOSFET die temperature. A factor of 1.6 in the current limit setpoint should compensate for all MOSFET RDS(ON) variations, assuming the MOSFET’s heat sinking will keep its operating die temperature below 125°C. 0.17pf 1.5M S/H 17pf 300K 4.14K VSEN V to I in + ISNS RSENSE ISNS ISNS LDRV TO PWM COMP in – PGND CSS SS Reference and Soft Start I2 = ILIM*11.2 0.9V ILIM R ILIM ILIM ILIM det. 2.5V Figure 4. Current Limit / Summing Circuits REV. 1.0.10 5/3/04 7 PRODUCT SPECIFICATION FAN5234 gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1 volt. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1 Volt. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. Q2 LDRV ISNS RSENSE R1 PGND There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adaptive dead-time circuit to work properly. Any delay along that path will subtract from the delay generated by the adaptive dead-time circit and shoot-through may occur. Figure 5. Improving current sensing accuracy More accurate sensing can be achieved by using a resistor (R1) instead of the RDS(ON) of the FET as shown in Figure 5. This approach causes higher losses, but yields greater accuracy in both VDROOP and ILIMIT. R1 is a low value (e.g. 10mΩ) resistor. Current limit (ILIMIT) should be set sufficiently high as to allow inductor current to rise in response to an output load transient. Typically, a factor of 1.2 is sufficient. In addition, since ILIMIT is a peak current cut-off value, we will need to multiply ILOAD(MAX) by the inductor ripple current (we’ll use 25%). For example, in Figure 1 the target for ILIMIT would be: ILIMIT > 1.2 × 1.25 × 1.6 × 6A ≈ 14A (6) Duty Cycle Clamp During severe load increase, the error amplifier output can go to its upper limit pushing a duty cycle to almost 100% for significant amount of time. This could cause a large increase of the inductor current and lead to a long recovery from a transient, over-current condition, or even to a failure especially at high input voltages. To prevent this, the output of the error amplifier is clamped to a fixed value after two clock cycles if severe output voltage excursion is detected, limiting the maximum duty cycle to Frequency Loop Compensation Due to the implemented current mode control, the modulator has a single pole response with -1 slope at frequency determined by load 1 F PO = ---------------------2πR O C O where RO is load resistance, CO is load capacitance. For this type of modulator, Type 2 compensation circuit is usually sufficient. To reduce the number of external components and simplify the design task, the PWM controller has an internally compensated error amplifier. Figure 6 shows a Type 2 amplifier and its response along with the responses of a current mode modulator and of the converter. The Type 2 amplifier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. C2 R2 C1 R1 VIN EA Out REF C V OUT 2.4 DC MAX = -------------+ --------V IN V IN on err or a mp rte r 18 ve This circuit is designed to not interfere with normal PWM operation. When FPWM is grounded, the duty cycle clamp is disabled and the maximum duty cycle is 87%. (7) modulator 14 Gate Driver section The Adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the 8 0 F P0 FZ FP Figure 6. Compensation 1 F Z = -------------------- = 6kHz 2πR 2 C 1 (8a) 1 F P = -------------------- = 600kHz 2πR 2 C 2 (8b) REV. 1.0.10 5/3/04 FAN5234 This region is also associated with phase ‘bump’ or reduced phase shift. The amount of phase shift reduction depends the width of the region of flat gain and has a maximum value of 90 degrees. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feed-forward of VIN to the oscillator ramp. PRODUCT SPECIFICATION PGOOD 1 8 CLK IL 2 VOUT The zero frequency, the amplifier high frequency gain and the modulator gain are chosen to satisfy most typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase ‘boost’. Over-Voltage / Under-Voltage Protection Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 10kHz...50kHz range gives some additional phase ‘boost’. Fortunately, there is an opposite trend in mobile applications to keep the output capacitor as small as possible. Should the VSEN voltage exceed 120% of VREF (0.9V) due to an upper MOSFET failure, or for other reasons, the overvoltage protection comparator will force LDRV high. This action actively pulls down the output voltage and, in the event of the upper MOSFET failure, will eventually blow the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. Protection This OVP scheme provides a ‘soft’ crowbar function which helps to tackle severe load transients and does not invert the output voltage when activated — a common problem for latched OVP schemes. The converter output is monitored and protected against extreme overload, short circuit, over-voltage and undervoltage conditions. 3 CH1 5.0V CH3 2.0AΩ CH2 100mV M 10.0µs Figure 7. Over-Current protection waveforms A sustained overload on an output sets the PGOOD pin low and latches-off the whole chip. Operation can be restored by cycling the VCC voltage or by toggling the EN pin. Similarly, if an output short-circuit or severe load transient causes the output to droop to less than 75% of its regulation set point. Should this condition occur, the regulator will shut down. If VOUT drops below the under-voltage threshold, the chip shuts down immediately. Over-Temperature Protection Over-Current sensing If the circuit's current limit signal (“ILIM det” as shown in Figure 4) is high at the beginning of a clock cycle, a pulse-skipping circuit is activated and HDRV is inhibited. The circuit continues to pulse skip in this manner for the next 8 clock cycles. If at any time from the 9th to the 16th clock cycle, the "ILIM det" is again reached, the over-current protection latch is set, disabling the chip. If "ILIM det" does not occur between cycle 9 and 16, normal operation is restored and the over-current circuit resets itself. The chip incorporates an over temperature protection circuit that shuts the chip down when a die temperature of about 150˚C is reached. Normal operation is restored at die temperature below 125˚C with internal Power On Reset asserted, resulting in a full soft-start cycle. Design and Component Selection Guidelines As an initial step, define operating input voltage range, output voltage, minimum and maximum load currents for the controller. For the examples in the following discussion, we will be selecting components for: VIN from 5V to 20V VOUT = 1.8V @ ILOAD(MAX) = 3.5A REV. 1.0.10 5/3/04 9 PRODUCT SPECIFICATION FAN5234 Setting the Output Voltage The internal reference is 0.9V. The output is divided down by a voltage divider to the VSEN pin (for example, R1 and R2 in Figure 1). The output voltage therefore is: V OUT – 0.9V 0.9V ------------ = -------------------------------R1 R2 (9a) To minimize noise pickup on this node, keep the resistor to GND (R2) below 2K. We selected R2 at 1.82K. Then choose R5: ( 1.82K ) • ( 1.8V – 0.9 ) R5 = -------------------------------------------------------- = 1.82K 0.9 (9b) Output Inductor Selection The minimum practical output inductor value is the one that keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the ripple current to be somewhere from 15% to 35% of the nominal current. At light load, the ripple current also determines the point where the converter will automatically switch to hysteretic mode of operation (IMIN) to sustain high efficiency. The following equations help to choose the proper value of the output filter inductor. ∆V OUT ∆I = 2 – I MIN = -----------------ESR (10) where ∆I is the inductor ripple current, which we will choose for 20% of the full load current and ∆VOUT is the maximum output ripple voltage allowed. V IN – V OUT V OUT L = ------------------------------ × -------------F SW × ∆I V IN 0.7A In addition, the capacitor's ESR must be low enough to allow the converter to stay in regulation during a load step. The ripple voltage due to ESR for the converter in Figure 1 is 100mV P-P. Some additional ripple will appear due to the capacitance value itself: ∆I ∆V = ----------------------------------------C OUT × 8 × F SW (13) which is only about 1.5mV for the converter in Figure 1 and can be ignored. The capacitor must also be rated to withstand the RMS current which is approximately 0.3 X (∆I), or about 210mA for our example. High frequency decoupling capacitors should be placed as close to the loads as physically possible. Input Capacitor Selection The input capacitor should be selected by its ripple current rating. The input RMS current at maximum load current (IL) is: I RMS = I L D – D 2 (14) V V IN OUT where the converter duty cycle; D = -------------, which for the circuit in Figure 1, with VIN=6 calculates to: I RMS = 1.6A Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND ) losses. In typical applications, the FAN5234 converter's output voltage is low with respect to its input voltage, therefore the Lower MOSFET (Q2) is conducting the full load current for most of the cycle. Q2 should be therefore be selected to minimize conduction losses, thereby selecting a MOSFET with low RDS(ON). VIN = 20V, VOUT = 1.8V ∆I = 20% * 3.5A = 0.7A FSW = 300KHz. therefore L ≈ 8µH In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle, and it's conduction loss will therefore have less of an impact. Q1, however, sees most of the switching losses, so Q1's primary selection criteria should be gate charge. Output Capacitor Selection The output capacitor serves two major functions in a switching power supply. Along with the inductor it filters the sequence of pulses produced by the switcher, and it supplies the load transient currents. The output capacitor requirements are usually dictated by ESR, Inductor ripple current (∆I) and the allowable ripple voltage (∆V). 10 ∆I Power MOSFET Selection (11) for this example we'll use: ∆V ESR < -------∆I 0.1V For our example, ESR ( MAX ) = ∆V -------- = ------------ = 142mΩ (12) High-Side Losses: Figure 8 shows a MOSFET's switching interval, with the upper graph being the voltage and current on the Drain to Source and the lower graph detailing VGS vs. time with a constant current charging the gate. The x-axis therefore is also representative of gate charge (QG) . CISS = CGD + CGS, and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from MOSFET datasheets. REV. 1.0.10 5/3/04 FAN5234 PRODUCT SPECIFICATION Assuming switching losses are about the same for both the rising edge and falling edge, Q1's switching losses, occur during the shaded time when the MOSFET has voltage across it and current through it. Q G ( SW ) Q G ( SW ) t S = --------------------- ≈ ----------------------------------------------------I DRIVER VCC – V SP ----------------------------------------------- R DRIVER + R GATE (16) These losses are given by: PUPPER = PSW + PCOND where: V DS × I L P SW = ---------------------- × 2 × t S F SW 2 (15a) V OUT 2 P COND = -------------- × I OUT × R DS ( ON ) V IN (15b) PUPPER is the upper MOSFET's total losses, and PSW and PCOND are the switching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ). tS is the switching period (rise or fall time) and is t2+t3 (Figure 8). The driver’s impedance and CISS determine t2 while t3’s period is controlled by the driver's impedance and QGD. Since most of tS occurs when VGS = VSP we can use a constant current assumption for the driver to simplify the calculation of tS: C ISS CRSS CISS Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: QG(SW) = QGD + QGS – QTH where QTH is the gate charge required to get the MOSFET to it's threshold (VTH). For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Care should also be taken to include the delivery of the MOSFET's gate power (PGATE ) in calculating the power dissipation required for the FAN5234: PGATE = QG × VCC × FSW (17) where QG is the total gate charge to reach VCC. Low-Side Losses Q2, however, switches on or off with its parallel shottky diode conducting, therefore VDS ≈ 0.5V. Since PSW is proportional to VDS , Q2's switching losses are negligible and we can select Q2 based on RDS(ON) only. Conduction losses for Q2 are given by:: 2 P COND = ( 1 – D ) × I OUT × R DS ( ON ) VDS (18) where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and V OUT D = -------------V IN is the minimum duty cycle for the converter. ID VGS QGS QGD 4.5V VSP VTH QG(SW) t1 t2 t3 t4 t5 CISS = CGS || CGD The maximum power dissipation (PD(MAX)) is a function of the maximum allowable die temperature of the low-side MOSFET, the θJ-A, and the maximum allowable ambient temperature rise: T J ( MAX ) – T A ( MAX ) P D ( MAX ) = ------------------------------------------------θJ – A Figure 8. Switching losses and QG VIN 5V Since DMIN < 20% for portable computers, (1-D) ≈ 1 produces a conservative result, further simplifying the calculation. (19) θJ-A, depends primarily on the amount of PCB area that can be devoted to heat sinking (see FSC app note AN-1029 for SO-8 MOSFET thermal information). C GD RD HDRV RGATE G CGS SW Figure 9. Drive Equivalent Circuitt REV. 1.0.10 5/3/04 11 PRODUCT SPECIFICATION FAN5234 Table 2. BOM For 1.8V, 3.5A regulator (Figure 1) Description Qty Ref. Vendor Capacitor 68µF, Tantalum, 25V, ESR 95mΩ 1 C1 AVX Capacitor 10nF, Ceramic 2 C2, C3 Any Capacitor 68µF, Tantalum, 6V, ESR 1.8Ω 1 C4 AVX Part Number TPSV686*025#095 TAJB686*006 Capacitor 0.1µF, Ceramic 2 C5 Any Capacitor 330µF, Tantalum, 6V, ESR 100mΩ 2 C6 AVX 1.82KΩ, 1% Resistor 2 R1, R2 Any 1.3KΩ, 1% Resistor 1 R3 100KΩ, 5% Resistor 1 R4 56.2KΩ, 1% Resistor 1 R5 Any Schottky Diode; 0.5A, 20V 2 D1 Fairchild MBR0520L Inductor 8.4µH, 6A 1 L1 Dual MOSFET with Schottky 1 Q1 Fairchild FDS6986S PWM Controller 1 U1 Fairchild FAN5234 Layout Considerations Switching converters, even during normal operation, produce short pulses of current which could cause substantial ringing and be a source of EMI if layout constrains are not observed. There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rate and are noise generators. The low power components responsible for bias and feedback functions are sensitive to noise. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Notice all the nodes that are subjected to high dV/dt voltage swing such as SW, HDRV and LDRV, for example. All surrounding circuitry will tend to couple the signals from these nodes through stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. It is not recommended to use High Density Interconnect Systems, or micro-vias on these signals. The use of blind or buried vias should be limited to the low current signals only. The use of normal thermal vias is left to the discretion of the designer. 12 TPSE337*006#0100 Any Keep the wiring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak currents of 2A. Minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ringing at the gate. Locate small critical components like the soft-start capacitor and current sense resistors as close as possible to the respective pins of the IC. The FAN5234 utilizes advanced packaging technologies with lead pitches of 0.6mm. High performance analog semiconductors utilizing narrow lead spacing may require special considerations in PWB design and manufacturing. It is critical to maintain proper cleanliness of the area surrounding these devices. It is not recommended to use any type of rosin or acid core solder, or the use of flux in either the manufacturing or touch up process as these may contribute to corrosion or enable electromigration and/or eddy currents near the sensitive low current signals. When chemicals such as these are used on or near the PWB, it is suggested that the entire PWB be cleaned and dried completely before applying power. REV. 1.0.10 5/3/04 FAN5234 PRODUCT SPECIFICATION Mechanical Dimensions 16-Pin QSOP Inches Symbol Min. A A1 B C D E e H K L φ Max. Millimeters Min. .053 .069 .004 .010 .008 .012 .007 .010 .189 .197 .150 .157 .025 BSC 1.35 1.75 0.10 0.25 0.20 0.30 0.18 0.25 4.80 5.00 3.81 3.99 0.63 BSC .228 – .016 0° 5.79 – 0.41 0° .244 – .050 8° 16 Notes Max. 6.19 – 1.27 8° 9 C E H L 1 8 φ D K A B REV. 1.0.10 5/3/04 e A1 13 PRODUCT SPECIFICATION FAN5234 Mechanical Dimensions 16-Pin TSSOP 7.72 TYP 4.16 TYP. DIMENSIONS METRIC ONLY 16 5.0 ± 0.1 -A- (1.78 TYP) 0.42 TYP 0.65 TYP LAND PATTERN RECOMMENDATION 8 6.4 GAGE PLANE 4.4 ± 0.1 -B- 0.25 3.2 0°–8° 1 8 PIN #1 IDENT. 0.2 C B A ALL LEAD TIPS SEATING PLANE 0.6 ± 0.1 DETAIL A TYPICAL, SCALE: 40X SEE DETAIL A (0.90) 0.1 C ALL LEAD TIPS -C- 1.1 MAX TYP 0.65 TYP 0.10±0.05 TYP (0.19–0.30 TYP) (0.09–0.20 TYP) 0.13 M A B S C S 14 REV. 1.0.10 5/3/04 PRODUCT SPECIFICATION FAN5234 Ordering Information Part Number Temperature Range Package Packing FAN5234QSC -10°C to 85°C QSOP-16 Rails FAN5234QSCX -10°C to 85°C QSOP-16 Tape and Reel FAN5234MTC -10°C to 85°C TSSOP-16 Rails FAN5234MTCX -10°C to 85°C TSSOP-16 Tape and Reel DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 5/3/04 0.0m 004 Stock#DS30005234 2004 Fairchild Semiconductor Corporation