Order this document by MRFIC0914/D SEMICONDUCTOR TECHNICAL DATA The MRFIC Line ! This integrated circuit is intended for two–way paging applications and for other Industrial, Scientific and Medical (ISM) at 900 MHz band applications. The three stage design is implemented in Motorola’s low cost, high performance LDMOS process and housed in a low–cost surface mount SOIC package. Input and output matching is implemented off–chip for maximum flexibility while interstage matching is on–chip. A power control pin is included allowing 60 dB dynamic range. • 30.5 dBm Output Power for 3 dBm Input Power at 900 MHz • 32 dB Typ Small Signal Gain • 40% Efficiency Min at 30.5 dBm Output Power • 4.0 to 5.5 Volt Operation • Low–Cost, Low Profile Plastic SOIC Package • Order MRFIC0914R2 for Tape and Reel. R2 Suffix = 2,500 Units per 16 mm, 13 inch Reel. • Device Marking = M0914 900 MHz PAGING POWER AMPLIFIER Si MONOLITHIC INTEGRATED CIRCUIT CASE 751B–05 (SOIC–16) ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Symbol Value Unit Supply Voltage VD1, VD2, VD3 9 Vdc Supply Current IDtotal 2 Adc Rating Power Control Voltage VCNTRL 4.8 Vdc Input Power Pin 6 dBm Ambient Operating Temperature TA – 30 to + 80 °C Storage Temperature Tstg – 65 to +150 °C Thermal Resistance, Junction to Case θJC 26 °C/W VCNTRL 1 16 GND GND 2 15 GND VD2 3 14 RF IN GND 4 13 GND GND 5 12 GND RF OUT/VD3 6 11 VD1 GND 7 10 GND GND 8 9 CONTROL GND Pin Connections and Functional Block Diagram REV 2 MOTOROLA RF DEVICE DATA Motorola, Inc. 1997 MRFIC0914 1 RECOMMENDED OPERATING RANGES Parameter Symbol Value Unit VD1, VD2, VD3 3.6 to 5.8 Vdc Power Control Voltage VCNTRL 0 to 4.8 Vdc RF Frequency Range fRF 890 to 928 MHz Supply Voltage ELECTRICAL CHARACTERISTICS (VD1, VD2, VD3 = 4.8 V, f = 900 MHz, Pin = 3 dBm, 1 ms, 10% duty cycle, VCNTRL Adjusted for IDtotal = 583 mA, TA = 25°C unless otherwise noted. Measured in Circuit Configuration Shown in Figure 1.) Characteristic Min Typ Max Unit 1.12 — — W Efficiency 40 — — % Output Power at 1 dB Gain Compression — 29 — dBm Saturated Output Power — 31 — dBm Output Third Order Intercept Point — 36 — dBm Dynamic Range (VCNTRL = 0 to 4.8 V) — 60 — dB Input Return Loss 7 12 — dB 0.56 — — W Spurious Output (Load VSWR = 20:1, All Phase Angles) — –60 –50 dBc Harmonic Output (With External Matching Circuit) — — –45 dBc Output Power Output Power, Low Voltage (VD1, VD2, VD3 = 3.84 V) VCNTRL 1 C8 VD2 C4 VD3 C1 C2 C10 RF OUT C9 L 3 C1, C7 — 0.01 µf C2, C6, C8 — 33 pF C3 — 12 pF C4 — 1.0 µF 16 2 15 3 14 4 13 5 12 6 11 L2 RF INPUT C5 L 1 T2 CONTROL C3 T1 C6 7 10 8 9 C5, C10 — 100 pF C9 — 2.1 pF L1 — 33 nH L2 — 5.6 nH C7 VD3 L3 — 3.3 nH T1 — 50 Ω MICROSTRIP, 7.5° @ 900 MHz T2 — 50 Ω MICROSTRIP, 31.6° @ 900 MHz BOARD MATERIAL — 18 MIL FR4 Figure 1. Application Circuit Configuration MRFIC0914 2 MOTOROLA RF DEVICE DATA 5.8 V Pout , OUTPUT POWER (dBm) Pout , OUTPUT POWER (dBm) 3 4 3 2 3 0 2 8 2 6 2 4 2 2 2 0–10 4.8 V VD1, VD2, VD3 = 3.6 V TA = 25°C f = 900 MHz VCNTRL = 4 V –7.5 –5 –2.5 0 2.5 5 25°C TA = 85°C f = 900 MHz VCNTRL = 4 V VD1, VD2, VD3 = 4.8 V –7.5 –5 –2.5 0 2.5 Pin, INPUT POWER (dBm) Figure 2. Output Power versus Input Power Figure 3. Output Power versus Input Power 5 700 650 TOTAL SUPPLY CURRENT (mA) 5.8 V TA = 25°C f = 900 MHz VCNTRL = 4 V 4.8 V 600 550 VD1, VD2, VD3 = 3.6 V 500 450 –10 –7.5 –5 –2.5 0 2.5 –35°C 650 600 25° C 550 500 TA = 85°C f = 900 MHz VCNTRL = 4 V VD1, VD2, VD3 = 4.8 V 450 400 –10 5 –7.5 –5 –2.5 0 2.5 Pin, INPUT POWER (dBm) Pin, INPUT POWER (dBm) Figure 4. Supply Current versus Input Power Figure 5. Supply Current versus Input Power 5 900 4 0 3 0 2 0 1 0 0 5.8 V TOTAL QUIESCENT CURRENT (mA) TOTAL SUPPLY CURRENT (mA) –35°C Pin, INPUT POWER (dBm) 700 Pout , OUTPUT POWER (dBm) 3 2 3 0 2 8 2 6 2 4 2 2 2 0 1 8–10 4.8 V VD1, VD2, VD3 = 3.6 V –10 TA = 25°C f = 900 MHz Pin = 3 dBm –20 –30 5.8 V 800 VD1, VD2, VD3 = 3.6 to 5.8 V 25°C 700 600 –35°C 500 400 TA = 85°C 300 200 100 0 –40 0 1 2 3 4 5 0 1 2 3 4 VCNTRL, CONTROL VOLTAGE (VOLTS) VCNTRL, CONTROL VOLTAGE (VOLTS) Figure 6. Output Power versus VCNTRL Figure 7. Quiescent Current versus VCNTRL MOTOROLA RF DEVICE DATA 5 MRFIC0914 3 620 30.50 600 IDtotal Pout TA = 25°C f = 900 MHz VCNTRL = 4 V, 5 ms PULSE VD1, VD2, VD3 = 4.8 V Pin = 3 dBm 30.25 580 30.00 0 20 40 60 TOTAL SUPPLY CURRENT (mA) Pout , OUTPUT POWER (dBm) 30.75 560 100 80 DUTY CYCLE (%) Figure 8. Output Power versus Duty Cycle f ZOL* (Ω) Zin (Ω) MHz R jX R jX 800 48.8 –16.3 2.56 14.3 850 49.0 –17.9 3.30 14.4 900 49.0 –19.6 2.80 13.1 950 49.4 –21.2 3.94 14.0 1000 49.8 –23.1 3.95 12.6 Table 1. Device Impedances Derived from Circuit Characterization APPLICATIONS INFORMATION DESIGN PHILOSOPHY The MRFIC0914 three stage LDMOS integrated power amplifier was designed for low cost and flexibility. While the target application was two–way paging, the device can be used in a variety of 800 to 1000 MHz applications and it is particularly suited to burst mode digital transmissions with constant envelope modulation schemes. Only one supply is required. The VCNTRL pin allows the setting of the gate bias of the three stages simultaneoulsy for optimum gain and efficiency and serves as a transmit control with more than 60 dB dynamic range. RF performance is sensitive to the output matching network. C9 and L3 form a second harmonic trap which enhances efficiency. Placement of C3 along the 50Ω line at the device output is critical to gain and efficiency. L2, the input matching inductor, is optional. Without this inductor, the input match is still typically better than 2:1 VSWR. It should be note that Figure 1 does not portray the parasitics of the chip components nor their solder mounting pads. The board material is 18 mil dielectric thickness FR4. The impedances shown in Table 1 were derived from circuit characterization and are given as an aid to original designs. CIRCUIT DETAILS In Figure 1, the 900 MHz applications circuit, note that each stage has a separate supply pin, including the RF Output for the third stage. Care should be taken in bypassing these supply connections to avoid low frequency oscillation. Chip capacitors should be mounted as close to the leads and ground vias as possible. Ground vias should be provided close to the indicated ground leads as well. L1 is a bias choke supplying the third stage and could be replaced with a quarter wave line or air–wound inductor. MRFIC0914 4 EVALUATION BOARDS Evaluation boards are available for RF Monolithic Integrated Circuits by adding a “TF” to the device type. For a complete list of currently available boards and ones in development for newly introduced products, please consult your local Motorola Distributor or Sales Office. MOTOROLA RF DEVICE DATA PACKAGE DIMENSIONS -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B1 P 8 PL 0.25 (0.010) 8 M B M G K F R X 45° C -TSEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7° 0° 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7° 0° 0.229 0.244 0.010 0.019 CASE 751B-05 ISSUE J MOTOROLA RF DEVICE DATA MRFIC0914 5 Motorola reserves the right to make changes without further notice to any products herein. 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