MOTOROLA MPC9446

MOTOROLA
Freescale
SEMICONDUCTOR TECHNICAL
DATA Semiconductor, Inc.
Freescale Semiconductor, Inc...
2.5V and 3.3V LVCMOS Clock
Fanout Buffer
The MPC9446 is a 2.5V and 3.3V compatible 1:10 clock distribution
buffer designed for low-voltage mid-range to high-performance telecom,
networking and computing applications. Both 3.3V, 2.5V and dual supply
voltages are supported for mixed-voltage applications. The MPC9446
offers 10 low-skew outputs and 2 selectable inputs for clock redundancy.
The outputs are configurable and support 1:1 and 1:2 output to input
frequency ratios. The MPC9446 is specified for the extended temperature
range of --40°C to 85°C.
Features
• Configurable 10 outputs LVCMOS clock distribution buffer
Order Number: MPC9446/D
Rev 1, 03/2002
MPC9446
LOW VOLTAGE SINGLE OR
DUAL SUPPLY 2.5V AND 3.3V
LVCMOS CLOCK
DISTRIBUTION BUFFER
• Compatible to single, dual and mixed 3.3V/2.5V voltage supply
• Wide range output clock frequency up to 250 MHz
• Designed for mid-range to high-performance telecom, networking and
computer applications
•
•
•
•
•
•
Supports applications requiring clock redundancy
Max. output skew of 200 ps (150 ps within one bank)
Selectable output configurations per output bank
Tristable outputs
32 ld LQFP package
Ambient operating temperature range of --40 to 85°C
Functional Description
The MPC9446 is a full static fanout buffer design supporting clock
frequencies up to 250 MHz. The signals are generated and retimed
on-chip to ensure minimal skew between the three output banks. Two
independent LVCMOS compatible clock inputs are available. This feature
supports redundant clock sources or the addition of a test clock into the
system design. Each of the three output banks can be individually
supplied by 2.5V or 3.3V supporting mixed voltage applications. The
FSELx pins choose between division of the input reference frequency by
one or two. The frequency divider can be set individually for each of the
three output banks. The MPC9446 can be reset and the outputs are
disabled by deasserting the MR/OE pin (logic high state). Asserting
MR/OE will enable the outputs.
FA SUFFIX
LQFP PACKAGE
CASE 873A
All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated
50 Ω transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible
inputs. For series terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an
effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package.
© Motorola, Inc. 2002
1
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MPC9446
VCC
25k
CCLK0
Bank A
VCC
25k
CCLK1
CCLK_SEL
0
CLK
0
1
CLK ÷ 2
1
QA0
QA1
QA2
25k
Bank B
0
QB0
QB1
1
QB2
FSELA
FSELB
Freescale Semiconductor, Inc...
0
25k
QC1
QC2
1
25k
FSELC
QC0
Bank C
QC3
25k
MR/OE
25k
VCCC
VCCB
QB2
GND
QB1
VCCB
QB0
GND
Figure 1. MPC9446 Logic Diagram
VCCB is internally connected to VCC
24
23
22
21
20
19
18
17
VCCA
25
16
QC3
QA2
26
15
GND
GND
27
14
QC2
QA1
28
13
VCCC
VCCA
29
12
QC1
QA0
30
11
GND
GND
31
10
QC0
MR/OE
32
MPC9446
CCLK0
CCLK1
6
7
8
GND
VCC
5
FSELC
4
FSELB
3
FSELA
2
CCLK_SEL
9
1
VCCC
Figure 2. Pinout: 32--Lead Package Pinout (Top View)
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9446
Table 1: Pin Configuration
Pin
I/O
Type
Function
CCLK0,1
Input
LVCMOS
LVCMOS clock inputs
FSELA, FSELB, FSELC
Input
LVCMOS
Output bank divide select input
MR/OE
Input
LVCMOS
Internal reset and output (high impedance) control
GND
Supply
Negative voltage supply (GND)
VCCA, VCCB*, VCCC
Supply
Positive voltage supply for output banks
VCC
Supply
Positive voltage supply for core (VCC)
QA0 - QA2
Output
LVCMOS
Bank A outputs
QB0 - QB2
Output
LVCMOS
Bank B outputs
QC0 - QC3
Output
LVCMOS
Bank C outputs
* VCCB is internally connected to VCC.
Freescale Semiconductor, Inc...
Table 2: Supported Single and Dual Supply Configurations
VCCa
VCCAb
VCCBc
VCCCd
GND
3.3V
3.3V
3.3V
3.3V
3.3V
0V
Mixed voltage supply
3.3V
3.3V or 2.5V
3.3V
3.3V or 2.5V
0V
2.5V
2.5V
2.5V
2.5V
2.5V
0V
Supply voltage configuration
a.
b.
c.
d.
VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels
VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels
VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC.
VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels
Table 3: Function Table (Controls)
Control
Default
0
1
CCLK_SEL
0
CCLK0
CCLK1
FSELA
0
fQA0:2 = fREF
fQA0:2 = fREF ÷ 2
FSELB
0
fQB0:2 = fREF
fQB0:2 = fREF ÷ 2
FSELC
0
fQC0:3 = fREF
fQC0:3 = fREF ÷ 2
MR/OE
0
Outputs enabled
Internal reset Outputs disabled (tristate)
Table 4: Absolute Maximum Ratingsa
Symbol
Min
Max
Unit
VCC
Supply Voltage
-0.3
3.6
V
VIN
DC Input Voltage
-0.3
VCC+0.3
V
DC Output Voltage
-0.3
VOUT
IIN
IOUT
TS
Characteristics
VCC+0.3
V
DC Input Current
±20
mA
DC Output Current
±50
mA
125
°C
Storage temperature
-65
Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not
implied.
Table 5: General Specifications
Symbol
Characteristics
Min
Typ
Unit
VTT
Output Termination Voltage
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
2000
V
LU
Latch--Up Immunity
200
mA
CPD
Power Dissipation Capacitance
10
pF
CIN
Input Capacitance
4.0
pF
TIMING SOLUTIONS
VCC ÷ 2
Max
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Condition
V
Per output
MOTOROLA
Freescale Semiconductor, Inc.
MPC9446
Table 6: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 3.3V ±5%, TA = --40°C to +85°C)
Symbol
Characteristics
Min
VIH
Input High Voltage
2.0
VIL
Input Low Voltage
-0.3
IIN
Input Currenta
VOH
Output High Voltage
VOL
Output Low Voltage
ZOUT
Output Impedance
ICCQc
Maximum Quiescent Supply Current
Typ
Max
Unit
VCC + 0.3
V
LVCMOS
0.8
V
LVCMOS
200
µA
VIN=GND or VIN=VCC
V
IOH=-24 mAb
0.55
0.30
V
V
IOL= 24mAb
IOL= 12mA
2.0
mA
2.4
14 - 17
Condition
Ω
All VCC Pins
Freescale Semiconductor, Inc...
a. Input pull-up / pull-down resistors influence input current.
b. The MPC9446 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 7: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 3.3V ±5%, TA = --40°C to +85°C)a
Symbol
fref
Characteristics
Min
Input Frequency
fMAX
Maximum Output Frequency
tP, REF
Reference Input Pulse Width
tr, tf
CCLK Input Rise/Fall Time
tPLH
tPHL
Propagation delay
÷1 output
÷2 output
Max
Unit
0
Typ
250b
MHz
0
0
250b
125
MHz
MHz
1.4
CCLK0,1 to any Q
CCLK0,1 to any Q
2.2
2.2
Condition
FSELx=0
FSELx=1
ns
2.8
2.8
1.0c
ns
4.45
4.2
ns
ns
0.8 to 2.0V
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
tsk(O)
Output-to-output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
150
200
350
ps
ps
ps
tsk(PP)
Device-to-device Skew
2.25
ns
200
ps
53
55
%
%
DCREF = 50%
DCREF = 25%-75%
1.0
ns
0.55 to 2.4V
skewd
tSK(P)
Output pulse
DCQ
Output Duty Cycle
tr, tf
Output Rise/Fall Time
÷1 output
÷2 output
47
45
0.1
50
50
a. AC characteristics apply for parallal output termination of 50Ω to VTT.
b. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
c. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
d. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9446
Table 8: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = --40°C to +85°C)
Symbol
Max
Unit
VIH
Input High Voltage
Characteristics
Min
1.7
VCC + 0.3
V
LVCMOS
0.7
V
LVCMOS
V
IOH=-15 mAa
V
IOL= 15 mA
VIL
Input Low Voltage
-0.3
VOH
Output High Voltage
1.8
VOL
Output Low Voltage
ZOUT
Output Impedance
IIN
ICCQc
Typ
0.6
17 - 20b
Condition
Ω
Input Currentb
Maximum Quiescent Supply Current
±200
µA
VIN=GND or VIN=VCC
2.0
mA
All VCC Pins
Freescale Semiconductor, Inc...
a. The MPC9446 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per output.
b. Input pull-up / pull-down resistors influence input current.
c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 9: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = --40°C to +85°C)a b
Symbol
fref
Characteristics
Min
Input Frequency
fMAX
Maximum Output Frequency
tP, REF
Reference Input Pulse Width
tr, tf
CCLK Input Rise/Fall Time
tPLH
tPHL
Propagation delay
tPLZ, HZ
Output Disable Time
tPZL, LZ
÷1 output
÷2 output
Max
Unit
0
Typ
250c
MHz
0
0
250b
125
MHz
MHz
1.4
CCLK0,1 to any Q
CCLK0,1 to any Q
1.0d
ns
5.6
5.5
ns
ns
10
ns
Output Enable Time
10
ns
tsk(O)
Output-to-output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
150
200
350
ps
ps
ps
tsk(PP)
Device-to-device Skew
3.0
ns
tSK(P)
Output pulse skewe
200
ps
DCQ
Output Duty Cycle
tr, tf
Output Rise/Fall Time
45
FSELx=0
FSELx=1
ns
2.6
2.6
÷1 or ÷2 output
Condition
50
0.1
0.7 to 1.7V
55
%
DCREF = 50%
1.0
ns
0.6 to 1.8V
a.
b.
c.
d.
AC characteristics apply for parallel output termination of 50Ω to VTT.
AC specifications are design targets, final specification is pending device characterization.
The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
e. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Table 10: AC CHARACTERISTICS (VCC = 3.3V + 5%, VCCA, VCCB, VCCC = 2.5V + 5% or 3.3V + 5%,
TA = --40°C to +85°C)a b
Symbol
Characteristics
tsk(O)
Output-to-output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
tsk(PP)
Device-to-device Skew
tPLH,HL
Propagation delay
tSK(P)
Output pulse skewc
DCQ
Output Duty Cycle
Min
CCLK0,1 to any Q
Typ
Max
Unit
150
250
350
ps
ps
ps
2.5
ns
250
ps
55
%
Condition
See 3.3V table
÷1 or ÷2 output
45
50
DCREF = 50%
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
b. For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.
c. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
TIMING SOLUTIONS
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MOTOROLA
Freescale Semiconductor, Inc.
MPC9446
APPLICATIONS INFORMATION
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
The MPC9446 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091. In
most high performance clock networks point-to-point
distribution of signals is the method of choice. In a
point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC÷2.
VL
Z0
RS
R0
VL
= VS ( Z0 ÷ (RS+R0 +Z0))
= 50Ω || 50Ω
= 36Ω || 36Ω
= 14Ω
= 3.0 ( 25 ÷ (18+14+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
3.0
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9446 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 3. “Single
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
MPC9446 clock driver is effectively doubled due to its
capability to drive multiple lines.
2.5
VOLTAGE (V)
Freescale Semiconductor, Inc...
Driving Transmission Lines
14Ω
MPC9446
OUTPUT
BUFFER
IN
2.0
In
1.5
0.5
RS = 36Ω
ZO = 50Ω
0
OutA
2
4
6
8
TIME (nS)
10
12
14
Figure 4. Single versus Dual Waveforms
RS = 36Ω
ZO = 50Ω
RS = 36Ω
ZO = 50Ω
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 5. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
OutB0
14Ω
OutB1
Figure 3. Single versus Dual Transmission Lines
The waveform plots in Figure 4. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9446 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9446. The output waveform in Figure 4. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
MOTOROLA
OutB
tD = 3.9386
1.0
MPC9446
OUTPUT
BUFFER
IN
OutA
tD = 3.8956
MPC9446
OUTPUT
BUFFER
RS = 22Ω
ZO = 50Ω
RS = 22Ω
ZO = 50Ω
14Ω
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 5. Optimized Dual Line Termination
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9446
MPC9446 DUT
Pulse
Generator
Z = 50Ω
ZO = 50Ω
ZO = 50Ω
RT = 50Ω
RT = 50Ω
VTT
VTT
Freescale Semiconductor, Inc...
Figure 6. CCLK0,1 MPC9446 AC test reference for Vcc = 3.3V and Vcc = 2.5V
tF
VCC=3.3V
VCC=2.5V
2.4
1.8V
0.55
0.6V
VCC
CCLK
VCC÷2
GND
VCC
VCC÷2
QX
GND
tR
t(HL)
t(LH)
Figure 7. Output Transition Time Test Reference
Figure 8. Propagation delay (tPD) test reference
VCC
VCC
CCLK
VCC÷2
VCC÷2
GND
GND
VCC
VCC÷2
VCC
VCC÷2
QX
GND
GND
tSK(LH)
t(HL)
t(LH)
tSK(HL)
The pin-- to-- pin skew is defined as the worst case difference
in propagation delay between any two similar delay paths
within a single device
tSK(P) = | tPLH - tPHL |
Figure 10. Output Pulse Skew (tSK(P)) test reference
Figure 9. Output--to--output Skew tSK(LH, HL)
VCC
VCC÷2
GND
tP
T0
TN
DC = tP /T0 x 100%
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
TJIT(CC) = |TN - TN+1 |
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
Figure 11. Output Duty Cycle (DC)
TIMING SOLUTIONS
TN+1
Figure 12. Cycle--to--cycle Jitter
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Freescale Semiconductor, Inc.
MPC9446
OUTLINE DIMENSIONS
32
A1
A
- T-- , - U-- , - Z--
FA SUFFIX
LQFP PACKAGE
CASE 873A-02
ISSUE A
4X
0.20 (0.008) AB T-- U Z
25
1
- U--
- T-B
V
B1
DETAIL Y
17
9
V1
AE
DETAIL Y
4X
- Z--
0.20 (0.008) AC T-- U Z
S1
S
DETAIL AD
G
- AB-- AC-0.10 (0.004) AC
AC T-- U Z
SEATING
PLANE
BASE
METAL
F
8X
M_
R
J
SECTION AE-- AE
H
W
K
X
DETAIL AD
Q_
0.250 (0.010)
C E
MOTOROLA
D
0.20 (0.008)
M
N
GAUGE PLANE
Freescale Semiconductor, Inc...
8
9
AE
P
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE - AB-- IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS - T-- , - U-- , AND - Z-- TO BE DETERMINED
AT DATUM PLANE - AB-- .
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE - AC-- .
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE - AB-- .
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
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MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9446
Freescale Semiconductor, Inc...
NOTES
TIMING SOLUTIONS
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MPC9446
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
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TIMING SOLUTIONS
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MPC9446
Freescale Semiconductor, Inc...
NOTES
TIMING SOLUTIONS
11
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MPC9446
Freescale Semiconductor, Inc.
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MPC9446/D
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