MOTOROLA Freescale SEMICONDUCTOR TECHNICAL DATA Semiconductor, Inc. Order Number: MPC9447/D Rev 2, 04/2003 DATA SHEET MPC9447 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer 3.3V/2.5V 1:9 LVCMOS Clock The MPC9447 is a 3.3V or 2.5V compatible, 1:9 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 ps, the device meets the needs of most demanding clock applications. Freescale Semiconductor, Inc... Features 9 LVCMOS Compatible Clock Outputs • • • • • 2 Selectable, LVCMOS Compatible Inputs Maximum Clock Frequency of 350 MHz 3.3 V/2.5 V LVCMOS 1:9 CLOCK FANOUT BUFFER Maximum Clock Skew of 150 ps Synchronous Output Stop in Logic Low State Eliminates Output Runt Pulses • High--Impedance Output Control • • • • • 3.3V or 2.5V Power Supply Drives up to 18 Series Terminated Clock Lines Ambient Temperature Range --40_C to +85_C 32 Lead LQFP Packaging Supports Clock Distribution in Networking, Telecommunications, and Computer Applications • Pin and Function Compatible to MPC947 FA SUFFIX 32--LEAD LQFP PACKAGE CASE 873A Functional Description MPC9447 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50Ω terminated transmission lines on the incident edge: each is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable independent LVCMOS compatible clock inputs are available, providing support of redundant clock source systems. The MPC9447 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into high--impedance mode. All inputs have an internal pull--up or pull--down resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of --40_C to +85_C. The MPC9447 is pin and function compatible but performance--enhanced to the MPC947. IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 1 MPC9447 MPC9447 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Freescale Semiconductor, Inc. Q3 VCC Q4 GND Q5 VCC GND NETCOM GND MPC9447 24 23 22 21 20 19 18 17 Q0 25 16 GND Q2 26 15 Q6 VCC 27 14 VCC Q1 28 13 Q7 GND 29 12 GND Q0 30 11 Q8 Q6 VCC 31 10 VCC GND 32 9 GND Q5 SYNC Freescale Semiconductor, Inc... CLK_STOP Q7 VCC 1 2 3 4 5 6 7 8 GND Q4 VCC MPC9447 VCC CLK_SEL OE Q3 CLK_STOP Q2 VCC CCLK1 1 Q1 GND CCLK0 CCLK1 CLK STOP CLK_SEL 0 GND CCLK0 Q8 (all input resistors have a value of 25kΩ) OE Figure 1. Logic Diagram Figure 2. 32--Lead Pinout (Top View) Table 1. Function Table Control Default 0 1 CLK_SEL 1 CLK0 input selected CLK1 input selected OE 1 Outputs disabled (high--impedance state)a Outputs enabled CLK_STOP 1 Outputs synchronously stopped in logic low state Outputs active a. OE = 0 will high--impedance tristate all outputs independent on CLK_STOP Table 2. Pin Configuration Pin I/O Type CCLK0 Input LVCMOS Clock signal input Function CCLK1 Input LVCMOS Alternative clock signal input CLK_SEL Input LVCMOS Clock input select CLK_STOP Input LVCMOS Clock output enable/disable OE Input LVCMOS Output enable/disable (high--impedance tristate) Q0--8 Output LVCMOS Clock outputs GND Supply Ground VCC Supply VCC Negative power supply (GND) Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 3. General Specifications Symbol Characteristics Min Typ Max Condition Output termination voltage MM ESD protection (Machine model) 200 HBM ESD protection (Human body model) 2000 V LU Latch-up immunity 200 mA CPD Power dissipation capacitance 10 pF Per output CIN Input capacitance 4.0 pF Inputs IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer MOTOROLA VCC ÷ 2 Unit VTT 2 V V For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 2 TIMING SOLUTIONS MPC9447 MPC9447 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Freescale Semiconductor, Inc. NETCOM MPC9447 Table 4. Absolute Maximum Ratingsa Symbol Min Max Unit VCC Supply Voltage -0.3 3.9 V VIN DC Input Voltage -0.3 VCC + 0.3 V DC Output Voltage -0.3 VCC + 0.3 V ±20 mA ±50 mA 125 °C VOUT IIN IOUT TS Characteristics DC Input Current DC Output Current Storage temperature -65 Condition a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. DC Characteristics (VCC = 3.3V ± 5%, TA = 40°C to +85°C) Freescale Semiconductor, Inc... Symbol Max Unit VIH Input High Voltage Characteristics Min 2.0 VCC + 0.3 V LVCMOS 0.8 V LVCMOS V IOH = -24 mAa 0.55 0.30 V V IOL = 24 mA IOL = 12 mA ±300 µA VIN = VCC or GND 2.0 mA All VCC Pins VIL Input Low Voltage --0.3 VOH Output High Voltage 2.4 VOL Output Low Voltage ZOUT Output Impedance IIN ICCQ Typ 17 Condition Ω Input Currentb Maximum Quiescent Supply Currentc a. The MPC9447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for VCC=3.3V). b. Inputs have pull-down or pull-up resistors affecting the input current. c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 6. AC Characteristics (VCC = 3.3V ± 5%, TA = --40°C to +85°C)a Symbol 5Characteristics fref Input Frequency fmax Output Frequency fP,REF tr, tf Min Reference Input Pulse Width Max Unit 0 Typ 350 MHz 0 350 MHz 1.4 ns CCLK0, CCLK1 Input Rise/Fall Time ns 3.3 ns Propagation Delay tPLZ, HZ Output Disable Time 11 ns tPZL, ZH Output Enable Time 11 ns tH Setup Time Hold Time 1.3 1.0b tPLH/HL tS CCLK0 or CCLK1 to any Q CCLK0 or CCLK1 to CLK_STOPc 0.0 CLK_STOPc 1.0 CCLK0 or CCLK1 to Condition 0.8 to 2.0V ns ns tsk(O) Output-to-Output Skew 150 ps tsk(PP) Device-to-Device Skew 2.0 ns tSK(P) DCQ Output Pulse Skewd Output Duty Cycle 300 55 ps % DCREF = 50% 1.0 ns 0.55 to 2.4V tr, tf tJIT(CC) fQ<170 MHz Output Rise/Fall Time Cycle-to-cycle jitter 45 50 0.1 RMS (1 σ) TBD ps a. AC characteristics apply for parallel output termination of 50Ω to VTT. b. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. c. Setup and hold times are referenced to the falling edge of the selected clock signal input. d. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer TIMING SOLUTIONS 3 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 3 MOTOROLAMPC9447 MPC9447 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Freescale Semiconductor, Inc. MPC9447 NETCOM Table 7. DC Characteristics (VCC = 2.5V ± 5%, TA = --40°C to +85°C) Symbol Max Unit VIH Input High Voltage 1.7 VCC + 0.3 V LVCMOS VIL Input Low Voltage -0.3 0.7 V LVCMOS VOH Output High Voltage 1.8 V IOH =-15 mAa VOL Output Low Voltage V IOL = 15 mA ZOUT Output Impedance IIN ICCQ Characteristics Min Typ 0.6 19 Condition Ω Input Currentb Maximum Quiescent Supply Currentc ±300 µA VIN = VCC or GND 2.0 mA All VCC Pins a. The MPC9447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50Ω series terminated transmission lines per output (VCC=2.5V). b. Inputs have pull-down or pull-up resistors affecting the input current. Freescale Semiconductor, Inc... c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 8. AC Characteristics (VCC = 2.5V ± 5%, TA = -- 40°C to +85°C)a Symbol Characteristics fref Input Frequency fmax Output frequency fP,REF tr, tf Min Reference Input Pulse Width Max Unit 0 Typ 350 MHz 0 350 MHz 1.4 ns CCLK0, CCLK1 Input Rise/Fall Time CCLK0 or CCLK1 to any Q Condition 1.7 1.0b ns 4.4 ns tPLH/HL Propagation Delay tPLZ, HZ Output Disable Time 11 ns tPZL, ZH Output Enable Time 11 ns tS Setup Time CCLK0 or CCLK1 to CLK_STOPc 0.0 ns tH Hold Time CCLK0 or CCLK1 to CLK_STOPc 1.0 ns 0.7 to 1.7V tsk(O) Output-to-Output Skew 150 ps tsk(PP) Device-to-Device Skew 2.7 ns tSK(P) DCQ Ouput Pulse Skewd Output Duty Cycle 200 55 ps % DCREF = 50% 1.0 ns 0.6 to 1.8V tr, tf tJIT(CC) fQ<350 MHz Output Rise/Fall Time Cycle-to-cycle jitter 45 50 0.1 RMS (1 σ) TBD ps a. AC characteristics apply for parallel output termination of 50Ω to VTT. b. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. c. Setup and hold times are referenced to the falling edge of the selected clock signal input. d. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer MOTOROLA 4 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 4 TIMING SOLUTIONS MPC9447 MPC9447 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Freescale Semiconductor, Inc. NETCOM MPC9447 APPLICATION INFORMATION Figure 3. Output Clock Stop (CLK_STOP) Timing Diagram 3.0 2.5 CLK_STOP 2.0 VOLTAGE (V) CCLK0 or CCLK1 Freescale Semiconductor, Inc... Q0 to Q8 MPC9447 OUTPUT BUFFER IN RS = 33Ω ZO = 50Ω RS = 33Ω ZO = 50Ω RS = 33Ω ZO = 50Ω 1.5 0 2 4 6 8 TIME (nS) 10 12 14 Figure 5. Single versus Dual Line Termination Waveforms The waveform plots in Figure 5 “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the MPC9447 output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output--to--output skew of the MPC9447. The output waveform in Figure 5 “Single versus Dual Line Termination Waveforms” shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 33Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: OutA OutB0 17Ω VL Z0 RS R0 VL OutB1 Figure 4. Single versus Dual Transmission Lines = VS ( Z0 ÷ (RS+R0 +Z0)) = 50Ω || 50Ω = 33Ω || 33Ω = 17Ω = 3.0 ( 25 ÷ (16.5+17+25) = 1.28V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9447 clock driver. For the series terminated case, however, there is no DC current draw; thus, the outputs can drive multiple series terminated lines. Figure 4 “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9447 clock driver is effectively doubled due to its capability to drive multiple lines at VCC=3.3V. IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer TIMING SOLUTIONS In 0.5 MPC9447 OUTPUT BUFFER 17Ω OutB tD = 3.9386 1.0 Driving Transmission Lines The MPC9447 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of 17Ω (VCC=3.3V), the outputs can drive either parallel or series terminated transmission lines. For more information on transmission lines, the reader is referred to Motorola application note AN1091. In most high performance clock networks, point--to--point distribution of signals is the method of choice. In a point--to--point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC÷2. IN OutA tD = 3.8956 Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 6 “Optimized Dual Line Termination” should be used. In this case, the series terminating resistors 5 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 5 MOTOROLAMPC9447 MPC9447 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Freescale Semiconductor, Inc. MPC9447 NETCOM are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9447 OUTPUT BUFFER RS = 16Ω ZO = 50Ω RS = 16Ω ZO = 50Ω 17Ω 17Ω + 16Ω k 16Ω = 50Ω k 50Ω 25Ω = 25Ω Freescale Semiconductor, Inc... Figure 6. Optimized Dual Line Termination The Following Figures Illustrate the Measurement Reference for the MPC9447 Clock Driver Circuit MPC9447 DUT Pulse Generator Z = 50 Ω ZO = 50 Ω ZO = 50 Ω RT = 50 Ω RT = 50 Ω VTT VTT Figure 7. CCLK MPC9447 AC Test Reference for Vcc = 3.3V and Vcc = 2.5V IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer MOTOROLA 6 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 6 TIMING SOLUTIONS MPC9447 MPC9447 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Freescale Semiconductor, Inc. NETCOM MPC9447 VCC CCLK VCC÷2 GND VCC VCC÷2 QX GND tP(LH) tP(HL) Figure 8. Propagation Delay (tPD) Test Reference VCC VCC÷2 VCC Freescale Semiconductor, Inc... GND CCLK VCC÷2 VCC VCC÷2 GND GND tSK(LH) VCC VCC÷2 QX tSK(HL) GND tP(HL) tP(LH) The pin--to--pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device tSK(P) = | tPLH -- tPHL | Figure 9. Output--to--Output Skew tSK(LH, HL) Figure 10. Output Pulse Skew (tSK(P)) Test Reference VCC VCC÷2 GND tP T0 DC = (tP T0 x 100%) tF The time from the output controlled edge to the non--controlled edge, divided by the time between output controlled edges, expressed as a percentage Figure 11. Output Duty Cycle (DC) VCC=3.3V VCC=2.5V 2.4 1.8V 0.55 0.6V tR Figure 12. Output Transition Time Test Reference VCC CCLK PCLK TN TN+1 TJIT(CC) = |TN - TN+1 | GND VCC VCC÷2 CLK_STOP GND The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs tS Figure 13. Cycle--to--Cycle Jitter IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer TIMING SOLUTIONS VCC÷2 tH Figure 14. Setup and Hold Time (tS, tH) Test Reference 7 For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 7 MOTOROLAMPC9447 MPC9447 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Freescale Semiconductor, Inc. MPC9447 NETCOM OUTLINE DIMENSIONS FA SUFFIX LQFP PACKAGE CASE 873A--03 ISSUE B 4X 0.20 H A--B D 6 D1 e/2 D1/2 PIN 1 INDEX 32 3 25 1 E1/2 A F B Freescale Semiconductor, Inc... 6 E1 E 4 F DETAIL G 17 8 9 7 E/2 DETAIL G NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08--mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07--mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25--mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1--mm AND 0.25--mm FROM THE LEAD TIP. D D/2 4 D 4X 0.20 C A--B D H SEATING PLANE 28X e C 32X 0.1 C DETAIL AD BASE METAL PLATING b1 c 8X c1 b ( θ1_) 0.20 R R2 A2 0.25 GAUGE PLANE A1 (S) L θ_ (L1) DETAIL AD IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer MOTOROLA M 8 5 C A--B D SECTION F--F R R1 A A, B, D 8 DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 θ θ1 R1 R2 S For acquired More Information On This Product, Freescale Timing Solutions Organization has been by Integrated Device Technology, Inc Go to: www.freescale.com 8 MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0_ 7_ 12 _REF 0.08 0.20 0.08 -----0.20 REF TIMING SOLUTIONS MPC9447 MPC9447 MPC92459 PART NUMBERS 900 3.3V/2.5V MHzPRODUCT Low 1:9 LVCMOS Voltage LVDS Clock Clock Fanout Synthesizer Buffer TITLE INSERT NAME AND DOCUMENT NETCOM NETCOM Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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