MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Freescale Semiconductor, Inc... Low Voltage PLL Clock Driver The MPC9351 is a 2.5V and 3.3V compatible, PLL based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 200 MHz and a maximum output skew of 150 ps the MPC9351 is an ideal solution for the most demanding clock tree designs. The device offers 9 low skew clock outputs, each is configurable to support the clocking needs of the various high-performance microprocessors including the PowerQuicc II integrated communication microprocessor. The extended temperature range of the MPC9351 supports telecommunication and networking requirements.The devices employs a fully differential PLL design to minimize cycle-to-cycle and long-term jitter. Order this document by MPC9351/D MPC9351 LOW VOLTAGE 2.5V AND 3.3V PLL CLOCK GENERATOR Features • 9 outputs LVCMOS PLL clock generator • 25 - 200 MHz output frequency range • Fully integrated PLL • 2.5V and 3.3V compatible • Compatible to various microprocessors such as PowerQuicc II • Supports networking, telecommunications and computer applications • Configurable outputs: divide-by-2, 4 and 8 of VCO frequency • LVPECL and LVCMOS compatible inputs • External feedback enables zero-delay configurations FA SUFFIX LQFP PACKAGE CASE 873A–02 • Output enable/disable and static test mode (PLL enable/disable) • Low skew characteristics: maximum 150 ps output-to-output • Cycle-to-cycle jitter max. 22 ps RMS • 32 lead LQFP package • Ambient Temperature Range –40°C to +85°C Functional Description The MPC9351 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation of the MPC9351 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. With available output dividers of divide-by-2, divide-by-4 and divide-by-8 the internal VCO of the MPC9351 is running at either 2x, 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input (TCLK). The MPC9351 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9351 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9351 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm2 32-lead LQFP package. W Application Information The fully integrated PLL of the MPC9351 allows the low skew outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal. 06/01 Motorola, Inc. 2001 For More Information On This Product, REV 1 1 Go to: www.freescale.com Freescale Semiconductor, Inc. MPC9351 PCLK PCLK (pullup) TCLK (pulldown) 0 0 Ref ÷2 PLL 0 ÷4 1 1 ÷8 REF_SEL EXT_FB D Q QA D Q QB 1 (pulldown) (pulldown) FB 0 200 - 400 MHz 1 PLL_EN (pullup) QC0 FSELA FSELB FSELC FSELD D (pulldown) QC1 Q 1 (pulldown) QD0 (pulldown) (pulldown) QD1 0 D QD2 Q 1 QD3 QD4 OE (pulldown) The MPC9351 requires an external RC filter for the analog power supply pin VCCA. Please see application section for details. QC0 VCCO QC1 GND QD0 VCCO QD1 GND Figure 1. MPC9351 Logic Diagram 24 23 22 21 20 19 18 17 GND 25 16 QD2 QB 26 15 VCCO VCCO 27 14 QD3 QA 28 13 GND MPC9351 GND 29 12 QD4 TCLK 30 11 VCCO PLL_EN 31 10 OE REF_SEL 32 2 3 4 5 6 7 8 EXT_FB FSELA FSELB FSELC FSELD GND PCLK 9 1 VCCA Freescale Semiconductor, Inc... 0 PCLK Figure 2. Pinout: 32–Lead Package Pinout (Top View) MOTOROLA For More Information On This Product, 2 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9351 PIN CONFIGURATION Freescale Semiconductor, Inc... Pin I/O Type Function PCLK, PCLK Input LVPECL Differential clock reference Low voltage positive ECL input TCLK Input LVCMOS Single ended reference clock signal or test clock EXT_FB Input LVCMOS Feedback signal input, connect to a QA, QB, QC, QD output REF_SEL Input LVCMOS Selects input reference clock FSELA Input LVCMOS Output A divider selection FSELB Input LVCMOS Output B divider selection FSELC Input LVCMOS Outputs C divider selection FSELD Input LVCMOS Outputs D divider selection OE Input LVCMOS Output enable/disable QA Output LVCMOS Bank A clock output QB Output LVCMOS Bank B clock output QC0, QC1 Output LVCMOS Bank C clock outputs QD0 - QD4 Output LVCMOS Bank D clock outputs VCCA Supply VCC Positive power supply for the PLL VCC Supply VCC Positive power supply for I/O and core GND Supply Ground Negative power supply FUNCTION TABLE Control Default 0 1 REF_SEL 0 Selects PCLK as reference clock Selects TCLK as reference clock PLL_EN 1 Test mode with PLL disabled. The input clock is directly routed to the output dividers PLL enabled. The VCO output is routed to the output dividers OE 0 Outputs enabled Outputs disabled, PLL loop is open VCO is forced to its minimum frequency FSELA 0 QA = VCO ÷ 2 QA = VCO ÷ 4 FSELB 0 QB = VCO ÷ 4 QB = VCO ÷ 8 FSELC 0 QC = VCO ÷ 4 QC = VCO ÷ 8 FSELD 0 QD = VCO ÷ 4 QD = VCO ÷ 8 ABSOLUTE MAXIMUM RATINGSa Symbol Min Max Unit VCC Supply Voltage -0.3 4.6 V VIN DC Input Voltage -0.3 VCC+0.3 V DC Output Voltage -0.3 VCC+0.3 V DC Input Current ±20 mA DC Output Current ±50 mA VOUT IIN IOUT Characteristics Condition TS Storage Temperature -55 150 °C a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. GENERAL SPECIFICATIONS Symbol Characteristics Min Typ Max Unit Output Termination Voltage ESD (Machine Model) 200 HBM ESD (Human Body Model) 2000 V Latch–Up 200 mA LU CPD VCC B2 VTT MM Power Dissipation Capacitance CIN TIMING SOLUTIONS Condition V V 10 pF Per output 4.0 pF Inputs For More Information On This Product, 3 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9351 DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to 85°C) Symbol Freescale Semiconductor, Inc... b. Min Input High Voltage VPP Peak-to-Peak Input Voltage PCLK, PCLK 250 Common Mode Range PCLK, PCLK 1.0 VCMRa VOH a. Characteristics VIH VIL Typ 2.0 Input Low Voltage Output High Voltage Max Unit VCC + 0.3 0.8 V LVCMOS VCC-0.6 2.4 VOL Output Low Voltage 0.55 0.30 ZOUT IIN Output Impedance ICCA ICCQ Maximum PLL Supply Current 14 - 17 Input Leakage Current 3.0 Condition V LVCMOS mV LVPECL V LVPECL V IOH=-24 mAb IOL= 24 mA IOL= 12 mA V V W ±150 µA 5.0 mA VIN = VCC or GND VCCA Pin Maximum Quiescent Supply Current 1.0 mA All VCC Pins VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. The MPC9351 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines. AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to 85°C)a Symbol Characteristics Min ÷ 2 feedback ÷ 4 feedback ÷ 8 feedback Static test mode Typ Max Unit 100 50 25 0 200 100 50 300 MHz MHz MHz MHz 200 400 MHz 100 50 25 200 100 50 MHz MHz MHz Condition fref Input Frequency fVCO fMAX VCO Frequency frefDC Reference Input Duty Cycle 25 75 % Peak-to-Peak Input Voltage PCLK, PCLK 500 1000 mV LVPECL Common Mode Range 1.2 VCC-0.9 1.0 V LVPECL ns 0.8 to 2.0V +150 +325 ps ps PLL locked PLL locked 150 ps 55 52.5 51.75 % % % 1.0 ns ns VPP VCMRb Maximum Output Frequency ÷ 2 output ÷ 4 output ÷ 8 output PCLK, PCLK tr, tf TCLK Input Rise/Fall Time t(∅) Propagation Delay (static phase offset) TCLK to EXT_FB PCLK to EXT_FB –50 +25 tsk(o) DC Output-to-Output Skew tr, tf Output Rise/Fall Time tPLZ, HZ tPZL, ZH Output Disable Time 10 Output Enable Time 10 BW Output Duty Cycle PLL closed loop bandwidth 100 – 200 MHz 50 – 100 MHz 25 – 50 MHz 45 47.5 48.75 50 50 50 0.1 ÷ 2 feedback ÷ 4 feedback ÷ 8 feedback 9.0 – 20.0 3.0 – 9.5 1.2 – 2.1 PLL_EN = 1 PLL_EN = 1 PLL_EN = 1 PLL_EN = 0 0.55 to 2.4V ns MHz MHz MHz –3 db point of PLL transfer characteristic tJIT(CC) Cycle-to-cycle jitter ÷ 4 feedback Single Output Frequency Configuration 10 22 ps RMS value tJIT(PER) Period Jitter ÷ 4 feedback Single Output Frequency Configuration 8.0 15 ps RMS value ps RMS value 1.0 ms tJIT(∅) tLOCK a. b. I/O Phase Jitter Maximum PLL Lock Time 4.0 – 17 AC characteristics apply for parallel output termination of 50Ω to VTT VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(∅). MOTOROLA For More Information On This Product, 4 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9351 DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C) Symbol VPP Peak-to-Peak Input Voltage PCLK, PCLK 250 Common Mode Range PCLK, PCLK 1.0 Freescale Semiconductor, Inc... VOL ZOUT IIN b. Min Input High Voltage VCMRa VOH a. Characteristics VIH VIL Typ 1.7 Input Low Voltage Output High Voltage Max Unit VCC + 0.3 0.7 V LVCMOS VCC-0.6 1.8 Output Low Voltage 0.6 Output Impedance ±150 CIN CPD Input Capacitance 4.0 Power Dissipation Capacitance 10 ICCA ICCQ Maximum PLL Supply Current 3.0 V LVCMOS mV LVPECL V LVPECL V V IOH=-15 mAb IOL= 15 mA µA VIN = VCC or GND W 17 - 20 Input Leakage Current Condition pF Maximum Quiescent Supply Current pF Per Output 5.0 mA 1.0 mA VCCA Pin All VCC Pins VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. The MPC9351 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per output. AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)a Symbol Characteristics Min ÷ 2 feedback ÷ 4 feedback ÷ 8 feedback fref Input Frequency fVCO fMAX VCO Frequency frefDC Reference Input Duty Cycle VPP Peak-to-Peak Input Voltage PCLK, PCLK Common Mode Range PCLK, PCLK VCMRb tr, tf t(∅) Maximum Output Frequency Typ Unit 200 100 50 MHz MHz MHz 200 400 MHz 100 50 25 200 100 50 MHz MHz MHz 25 75 % 500 1000 mV LVPECL 1.2 VCC-0.6 1.0 V LVPECL ns 0.7 to 1.7V +100 +300 ps ps PLL locked PLL locked 150 ps 55 52.5 51.75 % % % TCLK Input Rise/Fall Time Propagation Delay (static phase offset) TCLK to EXT_FB PCLK to EXT_FB tsk(o) DC Output-to-Output Skew tr, tf tPLZ, HZ tPZL, ZH Output Rise/Fall Time BW ÷ 2 output ÷ 4 output ÷ 8 output Max 100 50 25 Output Duty Cycle 100 – 200 MHz 50 – 100 MHz 25 – 50 MHz –100 0 45 47.5 48.75 50 50 50 1.0 ns Output Disable Time 12 ns Output Enable Time 12 ns PLL closed loop bandwidth 0.1 ÷ 2 feedback ÷ 4 feedback ÷ 8 feedback 4.0 – 15.0 2.0 – 7.0 0.7 – 2.0 MHz MHz MHz Condition 0.6 to 1.8V –3dB point of PLL transfer characteristic tJIT(CC) Cycle-to-cycle jitter ÷ 4 feedback Single Output Frequency Configuration 10 22 ps RMS value tJIT(PER) Period Jitter ÷ 4 feedback Single Output Frequency Configuration 8.0 15 ps RMS value ps RMS value 1.0 ms tJIT(∅) tLOCK a. b. I/O Phase Jitter 6.0 – 25 Maximum PLL Lock Time AC characteristics apply for parallel output termination of 50Ω to VTT VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(∅). TIMING SOLUTIONS For More Information On This Product, 5 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9351 APPLICATIONS INFORMATION Programming the MPC9351 The MPC9351 clock driver outputs can be configured into several divider modes, in addition the external feedback of the device allows for flexibility in establishing various input to output frequency relationships. The output divider of the four output groups allows the user to configure the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even dividers ensure that the output duty cycle is always 50%. “Output Frequency Relationship for an Example Configuration” illustrates the various output configurations, the table describes the outputs using the input clock frequency CLK as a reference. The output division settings establish the output relationship, in addition, it must be ensured that the VCO will be stable given the frequency of the outputs desired. The feedback frequency should be used to situate the VCO into a frequency range in which the PLL will be stable. The design of the PLL supports output frequencies from 25 MHz to 200 MHz while the VCO frequency range is specified from 200 MHz to 400 MHz and should not be exceeded for stable operation. Freescale Semiconductor, Inc... Output Frequency Relationshipa for an Example Configuration Inputs a. Outputs FSELA FSELB FSELC FSELD QA QB QC QD 0 0 0 0 2 * CLK CLK CLK CLK 0 0 0 1 2 * CLK CLK CLK CLK ÷ 2 0 0 1 0 4 * CLK 2 * CLK CLK 2* CLK 0 0 1 1 4 * CLK 2 * CLK CLK CLK 0 1 0 0 2 * CLK CLK ÷ 2 CLK CLK 0 1 0 1 2 * CLK CLK ÷ 2 CLK CLK ÷ 2 0 1 1 0 4 * CLK CLK CLK 2 * CLK 0 1 1 1 4 * CLK CLK CLK CLK 1 0 0 0 CLK CLK CLK CLK 1 0 0 1 CLK CLK CLK CLK ÷ 2 1 0 1 0 2 * CLK 2 * CLK CLK 2 * CLK 1 0 1 1 2 * CLK 2 * CLK CLK CLK 1 1 0 0 CLK CLK ÷ 2 CLK CLK 1 1 0 1 CLK CLK ÷ 2 CLK CLK ÷ 2 1 1 1 0 2 * CLK CLK CLK 2 * CLK 1 1 1 1 2 * CLK CLK CLK CLK Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB. More frequency ratios are available by the connection of QA to the feedback input (EXT_FB). Using the MPC9351 in zero–delay applications Nested clock trees are typical applications for the MPC9351. For these applications the MPC9351 offers a differential LVPECL clock input pair as a PLL reference. This allows for the use of differential LVPECL primary clock distribution devices such as the Motorola MC100EP111 or MC10EP222, taking advantage of its superior low-skew performance. Clock trees using LVPECL for clock distribution and the MPC9351 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9351 PLL allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge and virtually eliminates the propagation delay through the device. The remaining insertion delay (skew error) of the MPC9351 in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset (SPO or t(∅)), I/O jitter MOTOROLA (tJIT(∅), phase or long-term jitter), feedback path delay and the output-to-output skew (tSK(O) relative to the feedback output. fref = 100 MHz TCLK QA QB 2 x 100 MHz QC0 QC1 2 x 100 MHz 4 x 100 MHz 1 REF_SEL 1 1 0 0 0 PLL_EN FSELA FSELB FSELC FSELD QD0 QD1 QD2 QD3 Ext_FB QD4 MPC9351 100 MHz (Feedback) MPC9351 zero–delay configuration (feedback of QD4) For More Information On This Product, 6 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9351 Calculation of part-to-part skew The MPC9351 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (TCLK or PCLK) of two or more MPC9351 are connected together, the maximum overall timing uncertainty from the common TCLK input to any output is: tSK(PP) = t( ∅) + tSK(O) + tPD, LINE(FB) + tJIT( ∅) CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: Freescale Semiconductor, Inc... TCLKCommon tPD,LINE(FB) –t(∅) QFBDevice 1 Above equation uses the maximum I/O jitter number shown in the AC characteristic table for VCC=3.3V (17 ps RMS). I/O jitter is frequency dependant with a maximum at the lowest VCO frequency (200 MHz for the MPC9351). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter characteristics in Figure 4. and Figure 5. can be used to derive a smaller I/O jitter number at the specific VCO frequency, resulting in tighter timing limits in zero-delay mode and for part-to-part skew tSK(PP). tJIT(∅) Any QDevice 1 +tSK(O) +t(∅) QFBDevice2 Figure 4. Max. I/O Jitter (RMS) versus frequency for VCC=2.5V tJIT(∅) Any QDevice 2 +tSK(O) Max. skew tSK(PP) Figure 3. MPC9351 max. device-to-device skew Due to the statistical nature of I/O jitter a RMS value (1 s) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. Table 8: Confidence Facter CF CF Probability of clock edge within the distribution ± 1s 0.68268948 ± 2s 0.95449988 ± 3s 0.99730007 ± 4s 0.99993663 ± 5s 0.99999943 ± 6s 0.99999999 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% (± 3s) is assumed, resulting in a worst case timing uncertainty from input to any output of -251 ps to 351 ps relative to TCLK (VCC=3.3V and fVCO = 400 MHz): tSK(PP) = [–50ps...150ps] + [–150ps...150ps] + [(17ps @ –3)...(17ps @ 3)] + tPD, LINE(FB) tSK(PP) = [–251ps...351ps] + tPD, LINE(FB) TIMING SOLUTIONS Figure 5. Max. I/O Jitter (RMS) versus frequency for VCC=3.3V Power Supply Filtering The MPC9351 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9351 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9351. Figure 6. illustrates a typical power supply filter scheme. The MPC9351 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to For More Information On This Product, 7 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9351 target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325V (VCC=3.3V or VCC=2.5V) must be maintained on the VCCA pin. The resistor RF shown in Figure 6. “VCCA Power Supply Filter” must have a resistance of 270 (VCC=3.3V) or 9-10 (VCC=2.5V) to meet the voltage drop criteria. W CF = 1 µF for VCC = 3.3V CF = 22 µF for VCC = 2.5V RF = 270Ω for VCC = 3.3V RF = 9–10Ω for VCC = 2.5V RF This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9351 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 7. “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9351 clock driver is effectively doubled due to its capability to drive multiple lines. VCCA VCC Freescale Semiconductor, Inc... W technique terminates the signal at the end of the line with a 50Ω resistance to VCC÷2. CF 10 nF MPC9351 OUTPUT BUFFER MPC9351 VCC IN RS = 36Ω 14Ω ZO = 50Ω OutA 33...100 nF MPC9351 OUTPUT BUFFER Figure 6. VCCA Power Supply Filter The minimum values for RF and the and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 6. “VCCA Power Supply Filter”, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9351 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC9351 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel MOTOROLA IN RS = 36Ω ZO = 50Ω OutB0 14Ω RS = 36Ω ZO = 50Ω OutB1 Figure 7. Single versus Dual Transmission Lines The waveform plots in Figure 8. “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9351 output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9351. The output waveform in Figure 8. “Single versus Dual Line Termination Waveforms” shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: = VS ( Z0 ÷ (RS+R0 +Z0)) = 50Ω || 50Ω = 36Ω || 36Ω = 14Ω = 3.0 ( 25 ÷ (18+17+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). VL Z0 RS R0 VL For More Information On This Product, 8 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9351 3.0 VOLTAGE (V) 2.5 OutA tD = 3.8956 match the impedances when driving multiple lines the situation in Figure 9. “Optimized Dual Line Termination” should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. OutB tD = 3.9386 2.0 In MPC9351 OUTPUT BUFFER 1.5 1.0 ZO = 50Ω RS = 22Ω ZO = 50Ω 14Ω 0.5 Freescale Semiconductor, Inc... RS = 22Ω 0 2 4 6 8 TIME (nS) 10 12 14Ω + 22Ω k 22Ω = 50Ω k 50Ω 25Ω = 25Ω 14 Figure 9. Optimized Dual Line Termination Figure 8. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better MPC9351 DUT Pulse Generator Z = 50 ZO = 50Ω ZO = 50Ω W RT = 50Ω RT = 50Ω VTT VTT Figure 10. TCLK MPC9351 AC test reference for Vcc = 3.3V and Vcc = 2.5V MPC9351 DUT Differential Pulse Generator Z = 50 ZO = 50Ω ZO = 50Ω W RT = 50Ω RT = 50Ω VTT VTT Figure 11. PCLK MPC9351 AC test reference TIMING SOLUTIONS For More Information On This Product, 9 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9351 VCC VCC 2 PCLK VCMR VCMR PCLK B TCLK GND VCC VCC 2 B Ext_FB VCC VCC 2 B Ext_FB GND GND t(∅) t(∅) Figure 12. Propagation delay (tPD, static phase offset) test reference Figure 13. Propagation delay (tPD) test reference VCC VCC 2 VCC VCC 2 GND GND Freescale Semiconductor, Inc... B B tP VCC VCC 2 B T0 GND DC = tP /T0 x 100% tSK(O) The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 14. Output Duty Cycle (DC) TN TN+1 The pin–to–pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 15. Output–to–output Skew tSK(O) TJIT(CC) = |TN –TN+1 | The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs TJIT(P) = |TN –1/f0 | T0 The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 16. Cycle–to–cycle Jitter Figure 17. Period Jitter TCLK (PCLK) Ext_FB TJIT(∅) = |T0 –T1 mean| tF VCC=3.3V 2.4 VCC=2.5V 1.8V 0.55 0.6V tR The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 18. I/O Jitter MOTOROLA Figure 19. Transition Time Test Reference For More Information On This Product, 10 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9351 OUTLINE DIMENSIONS A –T–, –U–, –Z– FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A 4X A1 32 0.20 (0.008) AB T–U Z 25 1 –U– –T– B V AE B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X –Z– 9 0.20 (0.008) AC T–U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T–U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ ÉÉ F 8X M_ R J M N D 0.20 (0.008) SEATING PLANE SECTION AE–AE H W K X DETAIL AD TIMING SOLUTIONS Q_ 0.250 (0.010) C E GAUGE PLANE Freescale Semiconductor, Inc... P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X For More Information On This Product, 11 Go to: www.freescale.com MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MPC9351 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 Technical Information Center: 1–800–521–6274 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA On This Product, 12 ◊For More Information Go to: www.freescale.com TIMING SOLUTIONS MPC9351/D