Ordering number : EN5348 CMOS LSI LC75371M Car Stereo Electronic Tone and Volume Control Overview Package Dimensions The LC75371M is an electronic tone/volume control LSI that can implement, with minimal external components, volume, balance, fader, bass and treble, loudness, input switching, and input level controls. unit: mm 3204-MFP36S [LC75371M] Functions • Volume control: From 0 to –79 dB in 1-dB steps plus –∞ for a total of 81 settings. Since the left and right levels can be set independently, this function can also be used to implement a balance function. • Fader: Attenuates either the rear or front channels to one of 16 levels. (Provides 16 settings, namely, from 0 to –20 dB in 2-dB steps, from –20 to –25 dB in one 5-dB step, from –25 to –45 dB in 10-dB steps, –60 dB, and –∞.) • Bass and treble controls: Forms an NF-type tone control circuit (LUX type) using external capacitors. Provides 15 settings each for the bass and treble controls. • Loudness control: A loudness function can be implemented by attaching external RC circuits at the taps provided from the volume control resistor ladder starting at the –20-dB position. • The input signal can be selected from one of three inputs for each of the left and right channels. The input signal can be amplified by between 0 and +18 dB in 6-dB steps. • Serial data input: Supports CCB* format communication with the system controller. SANYO: MFP36S Features • Built-in buffer amplifiers allow applications to be implemented with few external components. • A VDD/2 reference voltage generation circuit is provided on chip. • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 53096HA (OT) No. 5348-1/17 LC75371M Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions Ratings Maximum supply voltage VDD max VDD Maximum input voltage VIN max CL, DI, CE, LIN, RIN, LFIN, RFIN, L1 to L3, R1 to R3 Allowable power dissipation Pd max Ta ≤ 85°C Unit 12 VSS – 0.3 to VDD + 0.3 230 V V mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –50 to +125 °C max Unit Allowable Operating Ranges at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions min typ Supply voltage VDD VDD 6.0 11.0 V Input high-level voltage VIH CL, DI, CE 4.0 VDD V Input low-level voltage VIL CL, DI, CE VSS 1.0 V Input voltage amplitude VIN CL, DI, CE, LIN, RIN, LFIN, RFIN, L1 to L3, R1 to R3 VSS VDD Vp-p Input pulse width tøW CL 1 µs CL, DI, CE 1 µs thold CL, DI, CE 1 fopg CL Setup time tsetup Hold time Operating frequency µs 500 kHz No. 5348-2/17 LC75371M Electrical Characteristics at Ta = 25°C, VDD = 9 V, VSS = 0 V Parameter Symbol Conditions min typ max Unit [Input Block] Input resistance 30 50 70 kΩ Minimum input gain Gin min –2 0 +2 dB Maximum input gain Gin max +16.0 +18.0 +20.0 dB Step resolution Rin L1 to L3, R1 to R3 Gstep +6.0 dB [Volume Control Block] Input resistance Step resolution Step error Rv10 LIN, RIN: 10-dB steps, loudness off Rv1 1-dB steps 30 50 70 kΩ 6 10 14 kΩ ATstep ATerr 1 dB step = 0 to –20 dB –1 0 +1 dB step = –20 to –50 dB –3 0 +3 dB LFIN, RFIN 12 20 28 kΩ [Fader Block] Input resistance Step resolution Rfed ATstep step = 0 to –20 dB 2 dB step = –20 to –25 dB 5 dB step = –25 to –45 dB Step error Output load resistance ATerr RL 10 dB step = 0 to –45 dB –2 0 +2 step = –45 dB –3 0 +3 LFOUT, LROUT, RFOUT, RROUT 20 dB dB kΩ [Bass and Treble Control Block] Bass control range Treble control range Gbass Max. boost/cut ±9 ±10.5 ±12 dB Gtre Max. boost/cut ±8 ±10.5 ±13 dB [Overall Characteristics] Total harmonic distortion Crosstalk Output at maximum attenuation THD1 VIN = 1 Vrms, f = 1 kHz, all settings flat overall 0.045 % THD2 VIN = 1 Vrms, f = 20 kHz, all settings flat overall 0.045 % CT VIN = 1 Vrms, f = 1 kHz, all settings flat overall, 70 dB VIN = 1 Vrms, f = 1 kHz, main volume control at –∞ –76 dB VIN = 1 Vrms, f = 1 kHz, main volume control at –∞, INMUTE –80 dB VO min Rg = 1 kΩ VN1 All settings flat overall (IHF-A), Rg = 1 kΩ 12 30 VN2 All settings flat overall (DIN-AUDIO), Rg = 1 kΩ 16 40 µV Current drain IDD VDD – VSS = 11 V 19 22.8 mA Input high-level current IIH CL, DI, CE: VIN = 9 V 10 µA Input low-level current IIL CL, DI, CE: VIN = 0 V Output noise voltage Maximum input level VCL THD = 1%, RL = 20 kΩ, all tsettings flat overall, test point = fader output. –10 µV µA 2 Vrms No. 5348-3/17 LC75371M Equivalent Circuit Block Diagram and Sample Application Circuit No. 5348-4/17 LC75371M Test Circuits 1. Total harmonic distortion 2. Output noise voltage No. 5348-5/17 LC75371M 3. Crosstalk Pin Assignment No. 5348-6/17 LC75371M Pin Functions Pin No. Symbol Function 1 Vref2 • Common pin for the main volume control block, fader block, tone control block, gain control block, and input switching block. • Since the capacitor connected between Vref2 and VSS becomes the residual resistance when the volume control is set to maximum attenuation, the value of this capacitor must be selected carefully. • The voltage applied to this pin must never exceed VDD. 36 Vref1 VDD/2 voltage generation block. A capacitor must be connected between Vref1 and VSS to suppress power supply ripple. 2 3 35 34 LROUT LFOUT RROUT RFOUT • Fader outputs. The front and rear can be attenuated independently. The left and right attenuation levels are identical. • These are low-impedance outputs, since they have built-in operational amplifiers. 4 33 LFIN RFIN • Fader inputs • These inputs must be driven by low-impedance outputs. 5 32 LOUT ROUT Tone control outputs 8 7 6 29 30 31 LT1 LT2 LT3 RT1 RT2 RT3 10 9 27 28 LCT1 LCT2 RCT1 RCT2 Notes Connections for the bass and treble supplementary capacitors for the tone control circuit Connect high-frequency compensation capacitors between the T1/T2 pairs. Connect low-frequency compensation capacitors between the T2/T3 pairs. Loudness circuit connections. Connect high-frequency compensation capacitors between the LCT1/RCT1 and LIN/RIN pins, and connect lowfrequency compensation capacitors between LCT2/RCT2 and Vref2. Continued on next page. No. 5348-7/17 LC75371M Continued from preceding page. Pin No. Symbol Function 11 26 LIN RIN 12 25 LSELO RSELO 15 14 13 22 23 24 L1 L2 L3 R1 R2 R3 Signal inputs 16 VDD Power supply 20 VSS Ground 17 CE Chip enable. Data is loaded into the internal latch when this pin goes from high to low, and all analog switches operate at that time. Data transfers are enabled when this pin is high. 18 19 DI CL Serial data and clock inputs for LSI control. 21 TEST Notes • Main volume control inputs • These inputs must be driven by low-impedance outputs. Input selector outputs Test pin. This pin must be left open. No. 5348-8/17 LC75371M Input Block Equivalent Circuit Diagram Main Volume Control Block Equivalent Circuit Diagram No. 5348-9/17 LC75371M Tone Control Block Equivalent Circuit Diagram No. 5348-10/17 LC75371M Fader Block Equivalent Circuit Diagram No. 5348-11/17 LC75371M Sample Calculation of the Loudness Circuit External Constants First, see the LC75371M 10-dB step internal equivalent circuit shown on page 9. Figure 1 below shows a version of that circuit to which the loudness circuit external components have been added, and which has been simplified for this calculation. The sample calculation below uses this circuit diagram to acquire a 5-dB boost at f = 100 Hz. (f = 100 Hz, 5-dB boost) Assuming that the resistors and capacitors in Figure 1 have the following values: R1 = R2 = 50 kΩ R3 = 5 kΩ And C1 = Z1 and C2 = Z2. Then: R2 (R3 + Z2) R2 + R3 + Z2 = –20 dB VOUT = R1 · Z1 R2 (R3 + Z2) + (at = 1 kHz) R1 + Z1 R2 + R3 + Z2 R2 (R3 + 10 · Z2) R2 + R3 + 10 · Z2 = –15 dB VOUT = R1 · 10 · Z1 R2 (R3 + 10 · Z2) + (at = 100 Hz) R1 + 10 · Z1 R2 + R3 + 10 · Z2 From the above equations we find: Z1 = 891.5 kΩ and Z2 = 880 Ω. Therefore, the specifications will be met if capacitors that have these impedances at f = 1 kHz are connected externally. The result is that C1 = 178.5 pF and C2 = 0.18 µF. Figure 1 No. 5348-12/17 LC75371M Control System Timing and Data Format The LC75371M is controlled by applying data in the stipulated format to the CE, CL, and DI pins. The data consists of 40 bits, of which 8 bits are the chip address and 32 bits are the data. Note: The bits D19 and D28 to D31 are LSI test bits, and must be set to 0. No. 5348-13/17 LC75371M No. 5348-14/17 LC75371M No. 5348-15/17 LC75371M No. 5348-16/17 LC75371M Usage Notes 1. The states of the internal analog switches are undefined when power is first applied. Use an external muting circuit or other technique to mute the outputs until correct control data has been set up in the LC75371M. 2. Either cover the lines connected to the CL, DI, and CE pins with the ground pattern or use shielded cable for those lines to prevent the high-frequency digital signals on those lines from entering the analog system. 3. Muting by input switching must be used in conjunction with the volume control setting when the maximum volume control attenuation (the VOL = –∞ position) is used. 4. Since there is significant sample-to-sample variation in the magnitude of the main volume switching noise, request a switching noise verification sample to verify the maximum switching noise. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5348-17/17