Ordering number : ENA1354 CMOS IC LC75412WS Electronic Volume Controller for Car Audio Systems Overview The LC75412WS are electronic volume controllers that enable control of volume, balance, fader, bass/treble, loudness, input switching, and input gain using only a small number of external components. Functions • Volume • Fader : 0dB to -79dB in 1dB steps, and -∞ (81 positions) Balance function with separate L/R control : Rear output or front output can be attenuated across 16 positions (in 1dB steps from 0dB to -2dB, 2dB steps from -2dB to -20dB, 10dB steps from -20dB to -30dB, and -45dB, -60dB, -∞) • Bass/treble : Each band can be controlled in 2dB steps from ±0dB to ±18dB. • Input gain : 0dB to +18.75dB (1.25dB steps) amplification is possible for the input signal. • Input switching : Six input signals can be selected for Left and for Right (five are singleended inputs and one is a differential input.) • Loudness : A tap is output from the -32dB position of a volume control resistor ladder. A loudness function can be implemented by connecting an external RC circuit. Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Symbol Conditions Maximum supply voltage VDD max VDD Maximum input voltage VIN max All input pins Operating temperature Topr • • Ratings Unit 11 V VSS-0.3 to VDD+0.3 V -40 to +85 °C CCB is a registered trademark of SANYO Electric Co., Ltd. CCB is SANYO Semiconductor's original bus format. All bus addresses are managed by SANYO Semiconductor for this format. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 11409HKIM 20081021-S00001 No.A1354-1/19 LC75412WS Allowable Operating Ranges at Ta = 25°C, VSS = 0V Ratings Parameter Symbol Conditions min typ Unit max Supply voltage VDD VDD 6.0 10 V Input high-level voltage VIH CL, DI, CE 4.0 10 V Input low-level voltage VIL CL, DI, CE VSS 1.0 Input amplitude voltage VIN VSS VDD Input pulse width TφW CL V Vp-p 1 μs μs Setup time Tsetup CL, DI, CE 1 Hold time Thold CL, DI, CE 1 Operating frequency fopg CL μs 500 kHz Electrical Characteristics at Ta = 25°C, VDD = 9V, VSS = 0V Parameter Symbol Pin Name Ratings Conditions min typ Unit max [Input block] Input resistance Rin L1 to L4, L6, R1 to R4, R6 Minimum input gain Ginmin L1 to L4, L6, R1 to R4, R6 Maximum input gain Ginmax 30 50 70 kΩ -1 0 +1 dB +16.5 +18.75 +21 dB Step setting error ATerr ±0.6 dB L/R balance BAL ±0.5 dB [Volume block] Input resistance Rvr 100 kΩ Step setting error ATerr LVRIN, RVRIN loudness off 0dB to -40dB ±0.5 dB L/R balance BAL 0dB to -40dB ±0.5 dB ±1.0 dB dB 25 50 [Tone block] Step setting error ATerr -8dB to +8dB Bass control range Gbass max. boost/cut ±15 ±18 ±21 Treble control range Gtre max. boost/cut ±15 ±18 ±21 dB L/R balance BAL ±0.5 dB [Fader block] Input resistance Rfed Step setting error ATerr L/R balance LFIN, RFIN 25 50 100 kΩ ±0.5 dB -2dB to -20dB ±1 dB -20dB to -30dB ±2 dB -30dB to -60dB ±3 dB ±0.5 dB 0dB to -2dB BAL 0dB to -60dB [General] Total harmonic distortion THD (1) VIN = 0dBV, f = 1kHz 0.004 0.01 % THD (2) VIN = -10dBV, f = 10kHz 0.006 0.01 % Input crosstalk CT VIN = 1Vrms, f = 1kHz 80 88 dB L/R crosstalk CT VIN = 1Vrms, f = 1kHz 80 88 dB Maximum attenuated output Vomin (1) VIN = 1Vrms, f = 1kHz 80 88 dB Vomin (2) VIN = 1Vrms, f = 1kHz INMUTE, fader ∞ 90 95 dB VN (1) Flat overall, IHF-A filter VN (2) Flat overall, 20 to 20kHzBPF Output noise voltage Current drain IDD Input high-level current IIH CL, DI, CE, VIN = 9V Input low-level current IIL CL, DI, CE, VIN = 0V Maximum input voltage VCL THD = 1%, RL = 10kΩ flat overall, fIN = 1kHz Common-mode rejection ratio 5 CMRR VIN = 0dB, f = 1kHz μV 7 15 μV 55 60 mA 10 μA μA -10 2.3 10 2.5 Vrms 70 dB No.A1354-2/19 LC75412WS Package Dimensions unit : mm (typ) 3190A 12.0 0.5 10.0 48 33 64 12.0 32 10.0 49 17 1 16 0.5 0.15 0.18 0.1 1.7max (1.5) (1.25) SANYO : SQFP64(10X10) L5P L5M L4 L3 L2 L1 L6 VDD Vref R6 R1 R2 R3 R4 R5M R5P Pin Assignment RSELO 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 LSELO RVRIN 2 47 LVRIN RCT 3 46 LCT NC 4 45 NC NC 5 44 NC NC 6 43 NC RF1C1 7 42 LF1C1 RF1C2 8 41 LF1C2 RF1C3 9 40 LF1C3 NC 10 39 NC NC 11 38 NC LC75412WS LFIN LTOUT LFOUT 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LROUT RTOUT LAVSS LF3C3 TEST 34 CL 15 DVSS RF3C3 DI LF3C2 CE 35 MUTE 14 NC RF3C2 RAVSS LF3C1 TIM NC 36 RROUT 37 13 RFOUT 12 RFIN NC RF3C1 Top view No.A1354-3/19 R5P 64 63 62 61 5 NC 4 NC 0.33μF RCT 1kΩ 3 11 NC 10 NC 9 RF1C3 8 RF1C2 RF1C1 0.1μF 0.1μF RVref RVref No.A1354-4/19 [BASS f0≈100Hz] 13 14 15 0.001μF RF3C2 RF3C1 0.001μF [TREBLE f0≈10kHz] 12 NC 7 ZERO CROSSDET LOGIC CIRCUIT 34 RF3C3 RVRIN 10kΩ RSELO 1000pF 1μF 6 NC 2 RVref Multiplexer CONTROL CIRCUIT 35 33 16 RVref 1 RVref LVref ZERO CROSSDET 36 LVref R5M R4 60 59 58 57 LVref R3 R2 R1 R6 Vref 56 LVref 1μF×7 22μF VDD Multiplexer 0.1μF 55 54 53 LVref 39 0.001μF L6 L1 L2 LSELO 52 LVRIN L3 LCT 1μF×7 NC 51 37 38 NC L4 LF1C1 40 NC 50 LF1C2 41 LF1C3 42 NC L5M 10kΩ 43 LF3C1 49 1kΩ NC 44 0.33μF NC 45 LF3C2 46 0.1μF LF3C3 47 0.001μF 48 [TREBLE f0≈10kHz] LTOUT L5P 1000pF 1μF [BASS f0≈100Hz] 10μF NO SIGNAL TIMMER CCB INTERFACE 10μF 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RFIN RFOUT RROUT TIM NC RAVSS MUTE CE DI CL DVSS TEST LAVSS LROUT LFOUT LFIN PA PA 10μF 10μF PA PA 0.033μF CE DI μCOM CL 10μF 10μF LC75412WS Equivalent Circuit Block Diagram/Sample Application Circuit 1MΩ RTOUT LC75412WS Control Timing and Data Format To control the LC75412WS input specified serial data to the DI, CE, and CL pins. The data configuration consists of a total of 52 bits broken down into 8 address bits and 44 data bits. CE DI B0 B1 B2 B3 A0 A1 A2 A3 D0 1μs min 1μs min D1 D2 D3 D4 D5 D38 D39 D40 D41 D42 D43 CL CE 1μs min 1μs min 1μs min CL DI 1μs≤TDEST 1) Address code (B0 to A3) The LC75412WS use 8-bit address code and can be used in common with ICs that support SANYO’s CCB serial bus. Address Code (LSB) B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 0 0 0 1 (81HEX) 2) Control code allocation Input Switching Control D0 D1 D2 Setting 0 0 0 L1 (R1) 1 0 0 L2 (R2) 0 1 0 L3 (R3) 1 1 0 L4 (R4) 0 0 1 L5 (R5) 1 0 1 L6 (R6) D3 Bit for IC testing: Normally set to 0 Input Gain Control D4 D5 D6 D7 0 0 0 0 Operation 0dB 1 0 0 0 +1.25dB 0 1 0 0 +2.50dB 1 1 0 0 +3.75dB 0 0 1 0 +5.00dB 1 0 1 0 +6.25dB 0 1 1 0 +7.50dB 1 1 1 0 +8.75dB 0 0 0 1 +10.00dB 1 0 0 1 +11.25dB 0 1 0 1 +12.50dB 1 1 0 1 +13.75dB 0 0 1 1 +15.00dB 1 0 1 1 +16.25dB 0 1 1 1 +17.50dB 1 1 1 1 +18.75dB No.A1354-5/19 LC75412WS Volume Control (0 to -50dB) D8 D9 D10 D11 D12 D13 D14 D15 Operation 0 0 0 0 0 0 0 0 0dB 1 0 0 0 0 0 0 0 -1dB 0 1 0 0 0 0 0 0 -2dB 1 1 0 0 0 0 0 0 -3dB 0 0 1 0 0 0 0 0 -4dB 1 0 1 0 0 0 0 0 -5dB 0 1 1 0 0 0 0 0 -6dB 1 1 1 0 0 0 0 0 -7dB 0 0 0 1 0 0 0 0 -8dB 1 0 0 1 0 0 0 0 -9dB 0 1 0 1 0 0 0 0 -10dB 1 1 0 1 0 0 0 0 -11dB 0 0 1 1 0 0 0 0 -12dB 1 0 1 1 0 0 0 0 -13dB 0 1 1 1 0 0 0 0 -14dB 1 1 1 1 0 0 0 0 -15dB 0 0 0 0 1 0 0 0 -16dB 1 0 0 0 1 0 0 0 -17dB 0 1 0 0 1 0 0 0 -18dB 1 1 0 0 1 0 0 0 -19dB 0 0 1 0 1 0 0 0 -20dB 1 0 1 0 1 0 0 0 -21dB 0 1 1 0 1 0 0 0 -22dB 1 1 1 0 1 0 0 0 -23dB 0 0 0 1 1 0 0 0 -24dB 1 0 0 1 1 0 0 0 -25dB 0 1 0 1 1 0 0 0 -26dB 1 1 0 1 1 0 0 0 -27dB 0 0 1 1 1 0 0 0 -28dB 1 0 1 1 1 0 0 0 -29dB 0 1 1 1 1 0 0 0 -30dB 1 1 1 1 1 0 0 0 -31dB 0 0 0 0 0 1 0 0 -32dB 1 0 0 0 0 1 0 0 -33dB 0 1 0 0 0 1 0 0 -34dB 1 1 0 0 0 1 0 0 -35dB 0 0 1 0 0 1 0 0 -36dB 1 0 1 0 0 1 0 0 -37dB 0 1 1 0 0 1 0 0 -38dB 1 1 1 0 0 1 0 0 -39dB 0 0 0 1 0 1 0 0 -40dB 1 0 0 1 0 1 0 0 -41dB 0 1 0 1 0 1 0 0 -42dB 1 1 0 1 0 1 0 0 -43dB 0 0 1 1 0 1 0 0 -44dB 1 0 1 1 0 1 0 0 -45dB 0 1 1 1 0 1 0 0 -46dB 1 1 1 1 0 1 0 0 -47dB 0 0 0 0 1 1 0 0 -48dB 1 0 0 0 1 1 0 0 -49dB 0 1 0 0 1 1 0 0 -50dB Continued on next page. No.A1354-6/19 LC75412WS Continued from preceding page. Volume Control (-51 to -∞dB) D8 D9 D10 D11 D12 D13 D14 D15 Operation 1 1 0 0 1 1 0 0 -51dB 0 0 1 0 1 1 0 0 -52dB 1 0 1 0 1 1 0 0 -53dB 0 1 1 0 1 1 0 0 -54dB 1 1 1 0 1 1 0 0 -55dB 0 0 0 1 1 1 0 0 -56dB 1 0 0 1 1 1 0 0 -57dB 0 1 0 1 1 1 0 0 -58dB 1 1 0 1 1 1 0 0 -59dB 0 0 1 1 1 1 0 0 -60dB 1 0 1 1 1 1 0 0 -61dB 0 1 1 1 1 1 0 0 -62dB 1 1 1 1 1 1 0 0 -63dB 0 0 0 0 0 0 1 0 -64dB 1 0 0 0 0 0 1 0 -65dB 0 1 0 0 0 0 1 0 -66dB 1 1 0 0 0 0 1 0 -67dB 0 0 1 0 0 0 1 0 -68dB 1 0 1 0 0 0 1 0 -69dB 0 1 1 0 0 0 1 0 -70dB 1 1 1 0 0 0 1 0 -71dB 0 0 0 1 0 0 1 0 -72dB 1 0 0 1 0 0 1 0 -73dB 0 1 0 1 0 0 1 0 -74dB 1 1 0 1 0 0 1 0 -75dB 0 0 1 1 0 0 1 0 -76dB 1 0 1 1 0 0 1 0 -77dB 0 1 1 1 0 0 1 0 -78dB 1 1 1 1 0 0 1 0 -79dB *1 1 1 1 1 1 1 0 -∞ *1: ‘0’ or ‘1’ No.A1354-7/19 LC75412WS Tone Control D16 D17 D18 D19 D40 Bass D24 D25 D26 D27 D41 Treble 1 1 0 0 1 +18dB 0 1 0 0 1 +16dB 1 0 0 0 1 +14dB 0 1 1 0 0 +12dB 1 0 1 0 0 +10dB 0 0 1 0 0 +8dB 1 1 0 0 0 +6dB 0 1 0 0 0 +4dB 1 0 0 0 0 +2dB 0 0 0 0 0 0dB 1 0 0 1 0 -2dB 0 1 0 1 0 -4dB 1 1 0 1 0 -6dB 0 0 1 1 0 -8dB 1 0 1 1 0 -10dB 0 1 1 1 0 -12dB 1 0 0 1 1 -14dB 0 1 0 1 1 -16dB 1 1 0 1 1 -18dB D20 D21 D22 D23 Setting 0 0 0 0 Set to 0 Fader Volume Control D28 D29 D30 D31 Operation 0 0 0 0 0dB 1 0 0 0 -1dB 0 1 0 0 -2dB 1 1 0 0 -4dB 0 0 1 0 -6dB 1 0 1 0 -8dB 0 1 1 0 -10dB 1 1 1 0 -12dB 0 0 0 1 -14dB 1 0 0 1 -16dB 0 1 0 1 -18dB 1 1 0 1 -20dB 0 0 1 1 -30dB 1 0 1 1 -45dB 0 1 1 1 -60dB 1 1 1 1 -∞ No.A1354-8/19 LC75412WS Channel Selection Control D32 D33 Setting 1 0 RCH 0 1 LCH 1 1 L/R simultaneously Fader Rear/Front Control D34 Setting 0 Rear 1 Front Loudness Control D35 Setting 0 OFF 1 ON Zero-Cross Control D36 D37 Setting 0 0 Data write through zero-cross detection 1 1 Zero-cross detection stopped (data write at falling edge of CE) Zero-Cross Signal Detection Block Control D38 D39 Setting 0 0 Selector 1 0 Volume 0 1 Tone 1 1 Fader Test Mode Control D42 D43 Setting 0 0 For IC testing. Always set to 0. No.A1354-9/19 LC75412WS Pin Functions Pin Pin No. L1 54 L2 53 L3 52 L4 51 L6 55 R1 59 R2 60 R3 61 R4 62 R6 58 L5M 50 L5P 49 R5M 63 R5P 64 Function Equivalent circuit • Single-end input pins. VDD LVref RVref • Differential input pins. VDD M VDD P LVref RVref LSELO 48 RSELO 1 LCT 46 RCT 3 • Input selector output pins. VDD • Loudness pins. VDD Connect high-pass compensation CR between LCT (RCT) and LVRIN (RVRIN), and connect low-pass compensation CR between LCT (RCT) and GND. • Volume and equalizer input pins. LVRIN 47 RVRIN 2 LF1C1 42 LF1C2 41 connection pins. VDD • Equalizer F1 band filter configuration capacitor LF1C3 40 Connect capacitor between RF1C1 7 LF1C1 (RF1C1) and LF1C2 (RF1C2) RF1C2 8 LF1C2 (RF1C2) and LF1C3 (RF1C3) RF1C3 9 LF3C1 36 LF3C2 35 connection pins. LF3C3 34 Connect capacitor between RF3C1 13 LF3C1 (RF3C1) and LF3C2 (RF3C2) RF3C2 14 LF3C2 (RF3C2) and LF3C3 (RF3C3) RF3C3 15 VDD VDD VDD • Equalizer F3 band filter configuration capacitor FnC1 FnC3 VDD FnC2 Continued on next page. No.A1354-10/19 LC75412WS Continued from preceding page. Pin Pin No. NC 45 NC 44 NC 43 NC 39 NC 38 NC 37 NC 21 NC 12 NC 11 NC 10 NC 6 NC 5 NC 4 TEST 28 Function Equivalent circuit • No connect pin. • Dedicated IC test pin. VDD • Normally this pin is used connected to GND. LTOUT 33 RTOUT 16 • Equalizer output pins. LFIN 32 • Fader block input pins. RFIN 17 • Drive at low impedance. • Fader output pins. Attenuation is possible separately for LFOUT 31 LROUT 30 the front end and rear end. The attenuation amount is the same for L and R. RFOUT 18 RROUT 19 Vref 57 VDD VDD VDD • Connect a capacitor of a few tens of μF between Vref VDD and AVSS (VSS) as a VDD/2 voltage generator, current ripple countermeasure. LVref RVref VDD 56 • Power supply pin. DVSS 27 • Logic system ground pin. LAVSS RAVSS MUTE 29 • Analog system ground pins. 22 23 • External muting control pin. • Setting this pin to VSS level sets forcibly fader volume VDD block to -∞ level. Continued on next page. No.A1354-11/19 LC75412WS Continued from preceding page. Pin Pin No. TIM 20 Function Equivalent circuit • Timer pin when there is no signal in the zero-cross VDD circuit. Forcibly set data when there is no zero-cross signal, from the time the data is set until the timer ends. CL 26 DI 25 CE 24 • Input pin for serial data and clock used for control. VDD • Chip enable pin. Data is written to the internal latch and the analog switches are operated when the level changes from High to Low. Data transfer is enabled when the level is High. Internal Equivalent Circuit Block Diagram Selector Block Equivalent Circuit Block Diagram R3=22.65kΩ L5P LSELO R4=25kΩ LVref L5M 0dB 6.702kΩ R2=25kΩ 1.25dB R1=22.65kΩ 5.804kΩ L4 2.50dB 50kΩ 5.026kΩ 3.75dB LVref 4.352kΩ L3 5.00dB 50kΩ 3.769kΩ 6.25dB LVref 3.264kΩ L2 7.50dB 2.826kΩ 50kΩ 8.75dB LVref 2.447kΩ L1 10.00dB 50kΩ 2.119kΩ 11.25dB LVref 1.835kΩ L6 12.50dB 1.589kΩ 50kΩ 13.75dB LVref 1.376kΩ INMUTE SW 15.00dB 1.192kΩ 16.25dB Total resistance: 50kΩ Same for right channel 1.032kΩ LVref 17.50dB 0.894kΩ 18.75dB 5.774kΩ LVref No.A1354-12/19 LC75412WS Volume Block Equivalent Circuit Block Diagram 0dB& -∞ASW=1kΩ Others ASW=3kΩ LVRIN 0dB R1=5434Ω -1dB R28=243Ω -28dB R55=133Ω -55dB R2=4845Ω -2dB R29=216Ω -29dB R56=119Ω -56dB R3=4319Ω -3dB R30=193Ω -30dB R57=106Ω -57dB R4=3850Ω -4dB R31=172Ω -31dB R58=94Ω -58dB R5=3431Ω -5dB R32=153Ω -32dB R59=84Ω -59dB R6=3058Ω -6dB R33=839Ω -33dB R60=75Ω -60dB R7=2726Ω -7dB R34=748Ω -34dB R61=134Ω -61dB R8=2429Ω -8dB R35=667Ω -35dB R62=119Ω -62dB R9=2165Ω -9dB R36=594Ω -36dB R63=106Ω -63dB R10=1930Ω -10dB R37=530Ω -37dB R11=1720Ω -11dB R38=472Ω -38dB R65=84Ω -65dB R12=1533Ω -12dB R39=421Ω -39dB R66=75Ω -66dB R13=1366Ω -13dB R40=375Ω -40dB R67=134Ω -67dB R14=1218Ω -14dB R41=334Ω -41dB R68=119Ω -68dB R15=1085Ω -15dB R42=298Ω -42dB R69=106Ω -69dB R16=967Ω -16dB R43=266Ω -43dB R70=95Ω -70dB R17=862Ω -17dB R44=237Ω -44dB R71=85Ω -71dB R18=768Ω -18dB R45=211Ω -45dB R72=75Ω -72dB R19=685Ω -19dB R46=188Ω -46dB R20=610Ω -20dB R47=168Ω -47dB R21=544Ω -21dB R22=485Ω -22dB R49=133Ω -49dB R76=95Ω -76dB R23=432Ω -23dB R50=119Ω -50dB R77=85Ω -77dB R24=385Ω -24dB R51=106Ω -51dB R78=76Ω -78dB R25=343Ω -25dB R52=94Ω -52dB R79=67Ω -79dB R26=306Ω -26dB R53=84Ω -53dB R80=552Ω -∞ R27=273Ω -27dB R54=75Ω -54dB To tone block LCT 1MΩ R86 1500Ω R81 R48=149Ω -48dB 1227Ω R82 1230Ω R83 R64=95Ω -64dB R73=134Ω -73dB R74=120Ω -74dB R75=107Ω 1233Ω R84 -75dB Total resistance of 48.746kΩ over tap Total resistance of 1.256kΩ under tap (LOUD OFF) Total resistance of 7.662kΩ under tap (LOUD ON) 1236Ω R85 Same for right channel LVref No.A1354-13/19 LC75412WS Tone Control Block Equivalent Circuit Diagram From Volume Block LTOUT SW2 SW3 SW2 SW1 SW1 0.655kΩ SW4 SW4 0.655kΩ 18dB 2.189kΩ 18dB 2.189kΩ 16dB 2.756kΩ 16dB 2.756kΩ 14dB 3.470kΩ 14dB 3.470kΩ 12dB 4.368kΩ 12dB 4.368kΩ 10dB 5.498kΩ 10dB 5.498kΩ 8dB 6.923kΩ 8dB 6.923kΩ 6dB 8.715kΩ 6dB 8.715kΩ 4dB 10.972kΩ 4dB 10.972kΩ 2dB 13.813kΩ 2dB 13.813kΩ 0dB 0dB 3.90kΩ LF1C1 SW3 LF1C2 3.90kΩ LF1C3 LF3C1 LF3C2 LF3C3 Total resistance: 59.359kΩ Same for right channel During boost, SW1 and SW3 are ON, during cut SW2 and SW4 are ON, and when 0dB, 0dB SW and SW2 and SW3 are ON. No.A1354-14/19 LC75412WS F1/F3 Band Circuit The equivalent circuit and the formula for calculating the external CR with a mean frequency of 1kHz are shown below. • F1/F3 band equivalent circuit block diagram R1 R2 C2 C1 R3 • Calculation example Specification Mean frequency : f0 = 1kHz Gain during maximum boost : G+18dB = 18dB Let us use R1 = 0.665kΩ, R2 = 58.704kΩ, and C1 = C2 = C. ( G+18dB = 20× LOG10 1 + R2 2R3+ R1 ) 1) Calculate R3 with G+18dB = 18dB: ⎛ ⎞ R2 − R1 ⎟ ÷ 2 = 3900Ω G/20 ⎝ 10 − 1 ⎠ R3 = ⎜ 2) Calculate C with the center frequency f0 = 1kHz f0 = 1 2π (R1 + R2)R3C1C2 C= 1 2πf0 (R1 + R2)R3 = 1 2π × 1000 39359 × 3900 = 0.010 × 10 −6 ≅ 0.01μF 3) Calculate Q: Q= R3(R1 + R2 ) 1 × (2R3 + R1) ≅ 1.789 (R1 + R2)R3 No.A1354-15/19 LC75412WS Fader Volume Block Equivalent Circuit Block Diagram S1 LFIN LFOUT 5.437kΩ 0dB -1dB S2 S3 4.846kΩ -2dB S4 LROUT 8.169kΩ -4dB 6.489kΩ -6dB 5.154kΩ -8dB 4.094kΩ When FADER = "1", S2 and S3 are ON. When FADER = "0", S1 and S4 are ON. -10dB 3.252kΩ -12dB 2.583kΩ -14dB 2.052kΩ -16dB 1.630kΩ -18dB 1.295kΩ -20dB 3.419kΩ -30dB 1.300kΩ Total resistance: 50kΩ Same for right channel -45dB 0.231kΩ -60dB 0.050kΩ -∞dB LVref When -∞ data is sent to the main volume, S1 and S2 become open, and S3 and S4 simultaneously become ON. No.A1354-16/19 LC75412WS Usage Cautions (1) Data transmission at power ON The status of internal analog switches is unstable at power ON. Therefore, perform muting or some other countermeasure until the data has been set. (2) Description of zero-cross switching circuit operation The LC75412WS have a function to switch zero-cross comparator signal detection locations, enabling the selection of the optimum detection location for blocks whose data is to be updated. Basically, the switching noise can be minimized by inputting the signal immediately following the block whose data is to be updated to the zero-cross comparator, so it is necessary to switch the detection location every time. Selector Tone Volume Fader Switch Zero-cross comparator LC75412WS Zero-Cross Detection Circuit (3) Zero-cross switching control method The zero-cross switching control method consists of setting the zero-cross control bits to the zero-cross detection mode (D36, D37 = 0), and specifying the detection blocks (D38, D39) before transmitting the data. These control bits are latched immediately following data transfer, that is to say beforehand in sync with the falling edge of CE, so when updating data of volumes, etc., it is possible to perform mode setting and zero-cross switching with one data transfer. An example of control when updating the data of the volume block is shown below. D36 D37 D38 D39 0 0 1 0 Zero-cross detection mode setting Volume block setting (4) Zero-cross timer setting If the input signal becomes lower than the zero-cross comparator detection sensitivity, or if only low-frequency signals are input, zero-cross detection continues to be impossible, and data is not latched during this time. The zero-cross timer can set a time for forcible latch during such a status when zero-cross detection is not possible. For example, to set 25ms, using T = 0.69CR and C = 0.033μF, we obtain R= 25×10-3 0.69×0.033×10-6 ≈1.1MΩ Normally, a value between 10ms and 50ms is set. No.A1354-17/19 LC75412WS (5) Cautions related to serial data transfer 1) To ensure that the high-frequency digital signals transferred to the CL, DI, and CE pins do not spill over to the analog signal block, either guard these signal lines with a ground pattern, or perform transmission using shielded wires. 2) The data format of the LC75412WS uses 8-bit addresses and 44-bit data. When sending data using multiples of 8 (when sending 48 bits), use the method described in Figure 1. Method for Receiving Data Using Multiple of 8 of LC75412WS X X X X Dummy data D0 D1 D2 D3 ••••• D36 D37 D38 D39 D40 Input switching control D41 D42 D43 Test mode control X: don’t care Figure 1 (6) Note on usage of external muting See Figure 2, to control muting with an external switch. If a microcontroller is used for the control, it is likely that an overvoltage is applied to the microcontroller via the MUTE pin because the MUTE pin is connected internally to VDD. To avoid such problems, add the resister R2 as shown in Figure 3 to resistor-divide the voltage at the MUTE pin. R1 R1 Switch MUTE MUTE R2 Figure 2 Microcontroller VDD VDD Figure 3 As an example, the relationship between the voltages at the MUTE pin and the values of R2 when VDD is 9 volts is shown below. The characteristic curve shown in the figure is a standard one. Relationship between R2 values and MUTE pin voltages when VDD is 9 volt 10 Ta=25°C MUTE pin voltage - V 8 6 4 2 0 0 50 100 150 200 R2 - kΩ *VIH (High detection voltage) at the MUTE pin must always be 4V or higher regardless of the supply voltage to be used. No.A1354-18/19 LC75412WS SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2009. Specifications and information herein are subject to change without notice. PS No.A1354-19/19