Revised February 2005 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear General Description Features The VHCT74A is an advanced high speed CMOS Dual D-Type Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to the Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. ■ High speed: fMAX 160 MHz (typ) at TA ■ High noise immunity: VIH 2.0V, VIL 25qC 0.8V ■ Power down protection is provided on all inputs and outputs ■ Low power dissipation: ICC 2 PA (max) at TA 25qC ■ Pin and function compatible with 74HCT74 Protection circuits ensure that 0V to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with VCC 0V. These circuits prevent device destruction due to mismatched supply and input/ output voltages. This device can be used to interface 3V to 5V systems and two supply systems such as battery backup. Ordering Code: Order Number Package Package Description Number 74VHCT74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHCT74AMX_NL (Note 1) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHCT74ASJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHCT74AMTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHCT74AMTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHCT74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. © 2005 Fairchild Semiconductor Corporation DS500026 www.fairchildsemi.com 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear July 1997 74VHCT74A Logic Symbol Connection Diagram IEEE/IEC Truth Table Pin Descriptions Pin Names Inputs Description Function PR D CK D1 , D2 Data Inputs L H X CK1, CK2 Clock Pulse Inputs H L X CLR1, CLR2 Direct Clear Inputs L L X PR1, PR2 Direct Preset Inputs H H L Outputs H H H H H X Q1, Q1, Q2, Q2 www.fairchildsemi.com Outputs CLR 2 Q Q X L H Clear X H L Preset H H L H X H L Qn Qn No Change Recommended Operating Conditions (Note 6) 0.5V to 7.0V 0.5V to 7.0V Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) 0.5V to VCC 0.5V 0.5V to 7.0V 20 mA (Note 3) (Note 4) Input Diode Current (IIK) Supply Voltage (VCC) 4.5V to 5.5V Input Voltage (VIN) 0V to 5.5V Output Voltage (VOUT) Output Diode Current (IOK) (Note 3) 0V to VCC (Note 4) 0V to 5.5V 40qC to 85qC Operating Temperature (TOPR) r20 mA r25 mA r50 mA 65qC to 150qC (Note 5) DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Input Rise and Fall Time (tr, tf) VCC Lead Temperature (TL) 260qC Soldering (10 seconds) 5.0V r 0.5V 0 ns/V a 20 ns/V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading varaibles. Fairchild does not recommend operation outside databook specifications. Note 3: HIGH or LOW state. IOUT absolute maximum rating must be observed. Note 4: VCC 0V. Note 5: VOUT GND, V OUT ! VCC.(Outputs Active) Note 6: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter (V) TA Min 25qC Typ TA Max 40qC to 85qC Min HIGH Level 4.5 2.0 2.0 Input Voltage 5.5 2.0 2.0 Max 4.5 0.8 0.8 Input Voltage 5.5 0.8 0.8 HIGH Level 4.5 4.40 Output Voltage 4.5 3.94 LOW Level 4.5 Output Voltage Input Leakage Current ICC Quiescent Supply Current ICCT Maximum ICC/Input Output Leakage Current 4.50 4.40 0.1 0.1 4.5 0.36 0.44 0–5.5 r0.1 r1.0 PA 5.5 2.0 20.0 PA 5.5 1.35 1.50 0.0 0.5 5.0 (Power Down State) 3 Conditions V V 3.80 0.0 Units V LOW Level IIN IOFF VCC V mA PA VIN VIH IOH 50 PA or VIL IOH 8 mA VIH IOL 50 PA or VIL IOL 8 mA VIN VIN 5.5V or GND VIN VCC or GND VIN 3.4V Other Inputs VOUT VCC or GND 5.5V www.fairchildsemi.com 74VHCT74A Absolute Maximum Ratings(Note 2) 74VHCT74A AC Electrical Characteristics Symbol Parameter 25qC VCC (V) (Note 7) Min TA Typ TA Max 40qC to 85qC Min Max Maximum Clock 5.0 100 160 80 Frequency 5.0 80 140 65 tPLH Propagation Delay Time 5.0 5.8 7.8 1.0 9.0 tPHL (CK-Q, Q) 5.0 6.3 8.8 1.0 10.0 tPLH Propagation Delay time 5.0 7.6 10.4 1.0 12.0 tPHL (CLR, PR -Q, Q) 5.0 8.1 11.4 1.0 13.0 CIN Input Capacitance 4 10 CPD Power Dissipation Capacitance 24 fMAX Units MHz 10 ns ns Conditions CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 15 pF CL 50 pF pF VCC pF (Note 8) Open Note 7: VCC is 5.0 r 0.5V Note 8: CPD is defined as the value of internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) CPD u VCC u fIN ICC/2 (per flip-flop). AC Operating Requirements Symbol tW(L) Parameter Minimum Pulse Width (CK) tW(H) tW(L) Minimum Pulse Width (CLR, PR) TA VCC (V) Typ 25qC TA 40qC to 85qC Guaranteed Minimum Units 5.0 r 0.5 5.0 5.0 ns 5.0 r 0.5 5.0 5.0 ns tS Minimum Setup Time 5.0 r 0.5 5.0 5.0 ns tH Minimum Hold Time 5.0 r 0.5 0 0 ns tREM Minimum Removal Time 5.0 r 0.5 3.5 3.5 ns (CLR, PR) www.fairchildsemi.com 4 74VHCT74A Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com 74VHCT74A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 74VHCT74A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com 74VHCT74A Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8