Revised February 2005 74VHC164 8-Bit Serial-In, Parallel-Out Shift Register General Description Features The VHC164 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC164 is a high-speed 8-Bit Serial-In/Parallel-Out Shift Register. Serial data is entered through a 2input AND gate synchronous with the LOW-to-HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register, setting all outputs LOW independent of the clock. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. ■ High Speed: fMAX 175 MHz at VCC 5V ■ Low power dissipation: ICC 4 PA (max) at TA ■ High noise immunity: VNIH VNIL 25qC 28% VCC (min) ■ Power down protection provided on all inputs ■ Low noise: VOLP 0.8V (max) ■ Pin and function compatible with 74HC164 Ordering Code: Package Order Number Package Description Number 74VHC164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC164MX_NL (Note 1) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC164SJ 74VHC164MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC164MTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description A, B Data Inputs CP Clock Pulse Input (Active Rising Edge) MR Master Reset Input (Active LOW) Q0–Q7 Outputs © 2005 Fairchild Semiconductor Corporation DS011636 www.fairchildsemi.com 74VHC164 8-Bit Serial-In, Parallel-Out Shift Register August 1993 74VHC164 Functional Description Function Table The VHC164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active High Enable for data entry through the other input. An unused input must be tied HIGH. Operating Outputs MR A B Q0 Reset (Clear) L X X L L–L Shift H L L L Q0–Q6 H L H L Q0–Q6 H H L L Q0–Q6 H H H H Q0–Q6 Mode Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A • B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW. Inputs H HIGH Voltage Levels L LOW Voltage Levels X Immaterial Q Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com Q1–Q7 2 Recommended Operating Conditions (Note 3) 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) DC Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) 2.0V to 5.5V 0V to 5.5V Output Voltage (VOUT) 0V to VCC 40qC to 85qC Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) Lead Temperature (TL) VCC 3.3V r 0.3V 0 ns/V a 100 ns/V VCC 5.0V r 0.5V 0 ns/V a 20 ns/V Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications. 260qC (Soldering, 10 seconds) Supply Voltage (VCC) Input Voltage (VIN) Note 3: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH HIGH Level Input Voltage VIL VOL TA Min 25qC TA Typ Max 40qC to 85qC Min 2.0 1.50 1.50 3.0 5.5 0.7 VCC 0.7 VCC LOW Level Input Voltage VOH VCC (V) Parameter 2.0 0.50 0.50 0.3 VCC 0.3 VCC HIGH Level Output 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 VIN 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 Quiescent Supply Current 0.0 V Voltage ICC VIH IOH 50 PA IOH 4 mA or VIL 4.4 2.0 Input Leakage Current V V LOW Level Output IIN Conditions V 3.0 5.5 Voltage Units Max 0.1 0.1 VIN V VIH IOH 8 mA IOL 50 PA IOL 4 mA IOL 8 mA or VIL 3.0 0.36 0.44 4.5 0.36 0.44 0 5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 4.0 40.0 PA VIN VCC or GND V Noise Characteristics Symbol Parameter VOLP Quiet Output Maximum (Note 4) Dynamic VOL VOLV Quiet Output Minimum (Note 4) Dynamic VOL VIHD Minimum HIGH Level (Note 4) Dynamic Input Voltage VILD Maximum LOW Level (Note 4) Dynamic Input Voltage VCC TA 25qC Units Conditions (V) Typ Limits 5.0 0.5 0.8 V CL 50 pF 5.0 0.5 0.8 V CL 50 pF 5.0 3.5 V CL 50 pF 5.0 1.5 V CL 50 pF Note 4: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC164 Absolute Maximum Ratings(Note 2) 74VHC164 AC Electrical Characteristics Symbol fMAX VCC (V) Parameter Maximum Clock Frequency 3.3 r 0.3 5.0 r 0.5 tPLH Propagation Delay tPHL Time (CP–Qn) 3.3 r 0.3 5.0 r 0.5 tPHL Propagation Delay 3.3 r 0.3 Time (MR–Qn) 5.0 r 0.5 CIN Input Capacitance CPD Power Dissipation TA 25qC 40qC to 85qC TA Min Typ Max Min 80 125 65 50 75 45 125 175 105 85 115 75 Max MHz MHz 8.4 12.8 1.0 15.0 10.9 16.3 1.0 18.5 5.8 9.0 1.0 10.5 7.3 11.0 1.0 12.5 8.3 12.8 1.0 15.0 10.8 16.3 1.0 18.5 5.2 8.6 1.0 10.0 6.7 10.6 1.0 12.0 4 10 10 76 Capacitance Units ns ns ns ns Conditions CL 15 pF, RL 1k CL 50 pF, RL 1k CL 15 pF, RL 1k CL 50 pF, RL 1k CL 15 pF, RL 1k CL 50 pF, RL 1k CL 15 pF, RL 1k CL 50 pF, RL 1k CL 15 pF, RL 1k CL 50 pF, RL 1k CL 15 pF, RL 1k CL 50 pF, RL 1k pF VCC Open pF (Note 5) Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) CPD * VCC * fIN I CC. AC Operating Requirements Symbol tW(L) Parameter VCC (V) (Note 6) Minimum Pulse Width (CP) tW(H) tW(L) Minimum Pulse Width (MR) TA Typ 25qC TA 40qC to 85qC Guaranteed Minimum 3.3 5.0 5.0 5.0 5.0 5.0 3.3 5.0 5.0 5.0 5.0 5.0 5.0 6.0 tS Minimum Setup Time 3.3 5.0 4.5 4.5 tH Minimum Hold Time 3.3 0.0 0.0 5.0 1.0 1.0 3.3 2.5 2.5 5.0 2.5 2.5 tREC Minimum Removal Time (MR) Note 6: VCC is 3.3 r 0.3V or 5.0 r 0.5V www.fairchildsemi.com 4 Units ns ns ns ns ns 74VHC164 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com 74VHC164 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 74VHC164 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com 74VHC164 8-Bit Serial-In, Parallel-Out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8