Revised April 1999 74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description The VHC574 is an advanced high speed CMOS octal flipflop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CP) and an output enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This cir- cuit prevents device destruction due to mismatched supply and input voltages. Features ■ High Speed: tPD = 5.6 ns (typ) at VCC = 5V ■ High Noise Immunity: VNIH = VNIL = 28% VCC (Min) ■ Power Down Protection is provided on all inputs ■ Low Noise: VOLP = 0.6V (typ) ■ Low Power Dissipation: ICC = 4 µA (Max) @ TA = 25°C ■ Pin and Function Compatible with 74HC574 Ordering Code: Order Number Package Number 74VHC574M 74VHC574SJ 74VHC574MTC 74VHC574N M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names © 1999 Fairchild Semiconductor Corporation Description D0–D7 Data Inputs CP Clock Pulse Input OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs DS011565.prf www.fairchildsemi.com 74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs March 1993 74VHC574 Functional Description Truth Table The VHC574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. Inputs Dn H L X CP Outputs OE On L H L L X H Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 2) 2.0V to +5.5V Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Voltage (VOUT) 0V to +5.5V Input Voltage (VIN) Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT) ±25 mA Input Rise and Fall Time (tr, tf) DC VCC /GND Current (ICC ) ±75 mA VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V −65°C to +150°C VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 0V to VCC −40°C to +85°C Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VCC (V) Parameter HIGH Level Input Voltage VIL VOH VOL IOZ TA = −40°C to +85°C Typ Max Min 2.0 1.50 1.50 3.0 − 5.5 0.7 VCC 0.7 VCC LOW Level Input Voltage TA = 25°C Min Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC HIGH Level 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 V VIN = VIH V IOH = −4 mA V LOW Level 2.0 0.0 0.1 0.1 Output Voltage 3.0 0.0 0.1 0.1 4.5 0.0 IOH = −8 mA VIN = VIH V IOL = 50 µA or VIL 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 ±0.25 ±2.5 µA 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND 5.5 4.0 40.0 µA VIN = VCC or GND 3-STATE Input Leakage IOH = −50 µA or VIL 4.4 IOL = 4 mA V IOL = 8 mA VIN = VIH or VIL VOUT = VCC or GND Output Off-State Current IIN Conditions V 3.0 − 5.5 Output Voltage Units Current ICC Quiescent Supply Current Noise Characteristics Symbol Parameter TA = 25°C VCC (V) Typ Limits Units Conditions VOLP (Note 3) Quiet Output Maximum Dynamic VOL 5.0 1.0 1.2 V CL = 50 pF VOLV (Note 3) Quiet Output Minimum Dynamic VOL 5.0 −0.8 −1.0 V CL = 50 pF VIHD (Note 3) Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL = 50 pF VILD (Note 3) Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL = 50 pF Note 3: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC574 Absolute Maximum Ratings(Note 1) 74VHC574 AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay tPHL Time (CP to On) VCC (V) TA = 25°C Min 3.3 ± 0.3 5.0 ± 0.5 tPZL 3-STATE Output tPZH Enable Time 3.3 ± 0.3 5.0 ± 0.5 TA = −40°C to +85°C Typ Max Min Max 8.5 13.2 1.0 15.5 11.0 16.7 1.0 19.0 5.6 8.6 1.0 10.0 7.1 10.6 1.0 12.0 8.2 12.8 1.0 15.0 10.7 16.3 1.0 18.5 5.9 9.0 1.0 10.5 7.4 11.0 1.0 12.5 tPLZ 3-STATE Output 3.3 ± 0.3 11.0 15.0 1.0 17.0 tPHZ Disable Time 5.0 ± 0.5 7.1 10.1 1.0 11.5 tOSLH Output to 3.3 ± 0.3 1.5 1.5 tOSHL Output Skew 5.0 ± 0.5 1.0 1.0 fMAX Maximum Clock 3.3 ± 0.3 Frequency 5.0 ± 0.5 CIN Units Conditions CL = 15 pF ns CL = 50 pF CL = 15 pF ns ns CL = 50 pF RL = 1 kΩ CL = 15 pF CL = 50 pF CL = 15 pF ns ns ns CL = 50 pF RL = 1 kΩ CL = 50 pF CL = 50 pF (Note 4) CL = 50 pF CL = 50 pF 80 125 65 CL = 15 pF 50 75 45 CL = 50 pF 130 180 110 85 115 75 Input MHz CL = 15 pF CL = 50 pF pF VCC = Open 6 pF VCC = 5.0V 28 pF (Note 5) 4 10 10 Capacitance COUT Output Capacitance CPD Power Dissipation Capacitance Note 4: Parameter guaranteed by design. tOSLH = |tPLH max − t PLH min|; tOSHL = |tPHL max − tPHL min| Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC/8 (per F/F). The total CPD when n pcs. of the Octal D Flip-Flop operates can be calculated by the equation: CPD (total) = 20 + 8n. AC Operating Requirements Symbol tW(H) Parameter Minimum Pulse Width (CP) tW(L) tS tH Minimum Set-Up Time Minimum Hold Time www.fairchildsemi.com TA = 25°C TA = −40°C to +85°C VCC (V) Min 3.3 ± 0.3 5.0 5.0 5.0 ± 0.5 5.0 5.0 Typ Max Min 3.3 ± 0.3 3.5 3.5 5.0 ± 0.5 3.5 3.5 3.3 ± 0.3 1.5 1.5 5.0 ± 0.5 1.5 1.5 4 Max Units ns ns 74VHC574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74VHC574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)