Revised April 1999 74VHCT573A Octal D-Type Latch with 3-STATE Outputs General Description Features The VHCT573A is an advanced high speed CMOS octal latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a Latch Enable input (LE) and an Output Enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. ■ High speed: tPD = 7.7 ns (typ) at TA = 25°C ■ High Noise Immunity: VIH = 2.0V, VIL = 0.8V ■ Power Down Protection is provided on all inputs and outputs ■ Low Noise: VOLP = 1.6V (max) ■ Low Power Dissipation: ICC = 4 µA (max) @ TA = 25°C ■ Pin and function compatible with 74HCT573 Note 1: Outputs in OFF-State. Ordering Code: Order Number Package Number 74VHCT573AM 74VHCT573ASJ 74VHCT573AMTC 74VHCT573AN Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names D0–D7 Description Data Inputs LE Latch Enable Input OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs © 1999 Fairchild Semiconductor Corporation DS500028.prf www.fairchildsemi.com 74VHCT573A Octal D-Type Latch with 3-STATE Outputs January 1998 74VHCT573A Functional Description Truth Table The VHCT573A contains eight D-type latches with 3STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs, a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode, but, this does not interfere with entering new data into the latches. Inputs Outputs OE LE D On L H H H L H L L L L X O0 H X X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 6) 4.5V to +5.5V Supply Voltage (VCC) DC Output Voltage (VOUT) 0V to +5.5V Input Voltage (VIN) (Note 3) −0.5V to VCC + 0.5V (Note 4) Output Voltage (VOUT) −0.5V to +7.0V (Note 3) 0V to VCC Input Diode Current (IIK) −20 mA (Note 4) 0V to 5.5V Output Diode Current (IOK) (Note 5) ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT) ±25 mA Input Rise and Fall Time (tr, tf) ±75 mA DC VCC/GND Current (ICC) VCC = 5.0V ± 0.5V −65°C to +150°C Storage Temperature (TSTG) 0 ns/V ∼ 20 ns/V Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Lead Temperature (TL) (Soldering, 10 seconds) −40°C to +85°C 260°C Note 3: HIGH or LOW state. IOUT absolute maximum rating must be observed. Note 4: When outputs are in OFF-State or when VCC = OV. Note 5: VOUT < GND, V OUT > VCC (Outputs Active). Note 6: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL IOZ VCC (V) Parameter TA = 25°C Min Typ TA = −40°C to +85°C Max Min HIGH Level 4.5 2.0 2.0 Input Voltage 5.5 2.0 2.0 Max Units V LOW Level 4.5 0.8 0.8 Input Voltage 5.5 0.8 0.8 HIGH Level 4.5 4.40 Output Voltage 4.5 3.94 LOW Level 4.5 0.1 0.1 V Output Voltage 4.5 0.36 0.44 V 5.5 ±0.25 ±2.5 µA 0 − 5.5 ±0.1 ±1.0 µA 5.5 4.0 40.0 µA 3-STATE Output Off-State Current IIN Input Leakage Current ICC Quiescent Supply Current ICCT Maximum ICC/Input IOFF Output Leakage Current (Power Down State) 4.50 0.0 5.5 0.0 V 4.40 V 3.80 V 1.35 1.50 0.5 Conditions mA µA 5.0 VIN = VIH IOH = −50 µA or VIL IOH = −8 mA VIN = VIH IOL = 50 µA or VIL IOL = 8 mA VIN = VIH or VIL VOUT = VCC or GND VIN = 5.5V or GND VIN = VCC or GND VIN = 3.4V Other Inputs = V CC or GND VOUT = 5.5V Noise Characteristics Symbol VOLP TA = 25°C VCC (V) Typ Limits Quiet Output Maximum Dynamic VOL 5.0 1.2 1.6 V CL = 50 pF Quiet Output Minimum Dynamic VOL 5.0 −1.2 −1.6 V CL = 50 pF Minimum HIGH Level Dynamic Input Voltage 5.0 2.0 V CL = 50 pF Maximum LOW Level Dynamic Input Voltage 5.0 0.8 V CL = 50 pF Parameter Units Conditions (Note 7) VOLV (Note 7) VIHD (Note 7) VILD (Note 7) Note 7: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHCT573A Absolute Maximum Ratings(Note 2) 74VHCT573A AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay Time tPHL (LE to On) tPLH Propagation Delay Time tPHL (D to On) tPZL 3-STATE Output tPZH Enable Time tPLZ 3-STATE Output tPHZ Disable Time tOSLH Output to Output tOSHL Skew VCC (V) TA = 25°C Min 5.0 ± 0.5 5.0 ± 0.5 5.0 ± 0.5 5.0 ± 0.5 TA = −40°C to +85°C Typ Max Min Max 7.7 12.3 1.0 13.5 8.5 13.3 1.0 14.5 5.1 8.5 1.0 9.5 5.9 9.5 1.0 10.5 6.3 10.9 1.0 12.5 7.1 11.9 1.0 13.5 8.8 11.2 5.0 ± 0.5 CIN Input Capacitance 4 COUT Output Capacitance 6 CPD Power Dissipation 25 1.0 Units CL = 15 pF ns CL = 50 pF CL = 15 pF ns ns 12.0 ns 1.0 1.0 ns 10 10 pF pF pF Capacitance Conditions CL = 50 pF RL = 1 kΩ CL = 15 pF CL = 50 pF RL = 1 kΩ CL = 50 pF (Note 8) VCC = Open VCC = 5.0V (Note 9) Note 8: Parameter guaranteed by design. tOSLH = |tPLH max − t PLH min|; tOSHL = |tPHL max − tPHL min| Note 9: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC/8 (per F/F). The total CPD when n pcs. of the Latch operates can be calculated by the equation: CPD(total) = 14 + 13n. AC Operating Requirements Symbol Parameter TA = 25°C VCC (V) Min Typ TA = −40°C to +85°C Max Min Max Units tW(H) Minimum Pulse Width (LE) 5.0 ± 0.5 6.5 8.5 tS Minimum Setup Time 5.0 ± 0.5 1.5 1.5 ns tH Minimum Hold Time 5.0 ± 0.5 3.5 3.5 ns www.fairchildsemi.com 4 ns 74VHCT573A Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 5 www.fairchildsemi.com 74VHCT573A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 6 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHCT573A Octal D-Type Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)