Revised April 1999 74VHC175 Quad D-Type Flip-Flop General Description The VHC175 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Features ■ High Speed: fMAX = 210 MHz (typ) at VCC = 5V ■ Low power dissipation: ICC = 4 µA (max) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min) ■ Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (max) ■ Pin and function compatible with 74HC175 Ordering Code: Order Number 74VHC175M 74VHC175SJ 74VHC175MTC Package Number M16A M16D MTC16 74VHC175N N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description D0–D3 Data Inputs CP Clock Pulse Input MR Master Reset Input Q0–Q3 True Outputs Q0–Q 3 Complement Outputs Logic Symbols IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS011637.prf www.fairchildsemi.com 74VHC175 Quad D-Type Flip-Flop August 1993 74VHC175 Functional Description Truth Table The VHC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The VHC175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Inputs Outputs @ tn, MR = H @ tn+1 Dn Qn Qn L L H H H L H = HIGH Voltage Level L = LOW Voltage Level tn = Bit Time before Clock Pulse tn+1 = Bit Time after Clock Pulse Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 2) 2.0V to +5.5V Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Voltage (VOUT) 0V to +5.5V Input Voltage (VIN) Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current (IOK) ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT) ±25 mA Input Rise and Fall Time (tr, tf) DC VCC /GND Current (ICC ) ±50 mA VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V −65°C to +150°C VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 0V to VCC −40°C to +85°C Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH HIGH Level Input Voltage VIL VOL TA = 25°C Min Typ TA = −40°C to +85°C Max Min 2.0 1.50 1.50 3.0 − 5.5 0.7 VCC 0.7 VCC LOW Level Input Voltage VOH VCC (V) Parameter Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 VIN = VIH 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 Quiescent Supply Current 0.0 0.1 IOH = −4 mA V Voltage Input Leakage Current IOH = −50 µA or VIL 4.4 2.0 ICC V V LOW Level Output IIN Conditions V 3.0 − 5.5 HIGH Level Output Units IOH = −8 mA VIN = VIH 0.1 V IOL = 50 µA or VIL IOL = 4 mA 3.0 0.36 0.44 4.5 0.36 0.44 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND 5.5 4.0 40.0 µA VIN = VCC or GND V IOL = 8 mA Noise Characteristics Symbol Parameter TA = 25°C VCC (V) Typ Limits Units Conditions VOLP (Note 3) Quiet Output Maximum Dynamic VOL 5.0 0.4 0.8 V CL = 50 pF VOLV (Note 3) Quiet Output Minimum Dynamic VOL 5.0 −0.4 −0.8 V CL = 50 pF VIHD (Note 3) Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL = 50 pF VILD (Note 3) Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL = 50 pF Note 3: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC175 Absolute Maximum Ratings(Note 1) 74VHC175 AC Electrical Characteristics Symbol fMAX Maximum Clock Typ 3.3 ± 0.3 90 140 50 75 45 5.0 ± 0.5 150 210 125 85 115 75 3.3 ± 0.3 Propagation Delay tPHL Time (CP to Qn or Qn) 5.0 ± 0.5 tPLH Propagation Delay Time tPHL (MR to Qn or Qn) 3.3 ± 0.3 5.0 ± 0.5 tOSLH Output to tOSHL Output Skew TA = −40°C to +85°C Min Frequency tPLH TA = 25°C VCC (V) Parameter Max Min Max 75 Units MHz MHz 7.5 11.5 1.0 13.5 10.0 15.0 1.0 17.0 4.8 7.3 1.0 8.5 6.3 9.3 1.0 10.5 6.3 10.1 1.0 12.0 8.8 13.6 1.0 15.5 4.3 6.4 1.0 7.5 5.8 8.4 1.0 9.5 Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF CL = 15 pF ns CL = 50 pF 3.3 ± 0.3 1.5 1.5 CL = 50 pF 5.0 ± 0.5 1.0 1.0 CL = 50 pF 10 10 (Note 4) CIN Input Capacitance 4 CPD Power Dissipation 44 pF VCC = Open pF (Note 5) Capacitance Note 4: Parameter guaranteed by design. tOSLH = |tPLHmax − tPLHmin|; tOSHL =| tPHLmax − tPHLmin|. Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC/4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated by the following equation: CPD (total) = 30 + 14 • n AC Operating Requirements Symbol tW(L) Parameter Minimum Pulse Width (CP) tW(H) tW(L) tS tH tREC Minimum Pulse Width (MR) Minimum Setup Time (Dn to CP) Minimum Hold Time (Dn to CP) Minimum Removal Time (MR) VCC (V) (Note 6) TA = −40°C to +85°C Guaranteed Minimum 3.3 5.0 5.0 5.0 5.0 5.0 3.3 5.0 5.0 5.0 5.0 5.0 3.3 5.0 5.0 5.0 4.0 4.0 3.3 1.0 1.0 5.0 1.0 1.0 3.3 5.0 5.0 5.0 5.0 5.0 Note 6: VCC is 3.3 ± 0.3V or 5.0 ± 0.5V www.fairchildsemi.com TA = 25°C Typ 4 Units ns ns ns ns ns 74VHC175 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com 74VHC175 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 6 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74VHC175 Quad D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued)