19-0379; Rev 0; 3/95 155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector ____________________________Features ♦ Supports Both 155Mbps and 622Mbps Clock Recovery and Data Retiming ♦ Fully Integrated Phase/Frequency Detector ♦ Capable of Switching to an External Clock ♦ Differential 100K ECL Data and Clock I/Os ♦ Output Monitor Provides Lock Detection ♦ No External Reference Clock Required The MAX3270 has differential ECL input and output interfaces, so it is less susceptible to noise in a highfrequency environment. The fully integrated PLL includes an integrated phase-frequency detector that eliminates the need for external references. ______________Ordering Information ________________________Applications 155Mbps (STM-1/OC-3)/622Mbps (STM-4/ OC-12) SDH/SONET Transmission Systems PART TEMP. RANGE PIN-PACKAGE MAX3270EMH -40°C to +85°C 44 MQFP 155Mbps/622Mbps ATM/SONET Access Nodes Add/Drop Multiplexers Cross-Connects Pin Configuration appears at end of data sheet. ___________________________________________________Typical Operating Circuit -2V -4.5V +5V 50Ω 2 12 1 -2V EXCS AND CRS ARE CONNECTED FOR 622Mbps OPERATION. -4.5V -4.5V -4.5V ANALOG SUPPLY 35 DVEE DVEE EXC DVEE FILP FILG EXCS CRS RST 50Ω 50Ω 50Ω 50Ω 450Ω 26 25 31 30 28 MAX3270 VR DVEE +5V CRP DVEE -2V 13 18 20 14 SDIN PHADJ GVEE 50Ω RDOP RDON RCOP RCON AVEE2 4 41 42 AVEE1 -2V 50Ω 32 29 OVCC 27 OVCC 24 OVCC 5 OVCC 15 AVCC 16 AVCC AVCC 7 AVCC 38 DVCC DVCC 17 19 DVCC VTTL SDIP 39 DVCC 11 3 FILN FM 9 8 2.2µF 20Ω 2.2µF 20Ω 10 6 36 22 21 34 -4.5V DIGITAL SUPPLY BYPASS SUPPLIES WITH 0.1µF AND 0.01µF CAPACITORS. DECOUPLE AVEE1, AVEE2, AND GVEE SUPPLY PINS. ________________________________________________________________ Maxim Integrated Products Call toll free 1-800-998-8800 for free samples or literature. 1 MAX3270 _______________General Description The MAX3270 is a complete Clock Recovery and Data Retiming IC for 155Mbps and 622Mbps SDH/SONET and ATM applications. The MAX3270 meets Bellcore and CCITT jitter tolerance specifications ensuring errorfree data recovery. Recovered clock and data are phase aligned using a fully integrated phase-locked loop (PLL). An output frequency monitor (FM) is included to detect loss of PLL acquisition or a loss of input data. MAX3270 155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector ABSOLUTE MAXIMUM RATINGS Supply Voltages VTTL to GND .....................................................-0.5V to +8.0V VCC to GND .......................................................-0.5V to +8.0V VEE to GND........................................................-8.0V to +0.5V SDIP, SDIN, EXC ...................................................-8.0V to +0.5V RDOP, RDON, RCOP, RCON, CRP.......................-8.0V to +0.5V EXCS, RST, CRS....................................................-0.5V to +8.0V FILP, FILG, FILN ....................................................-8.0V to +0.5V PHADJ, VR ............................................................-8.0V to +8.0V FM .........................................................................-8.0V to +8.0V Input Differential Voltage Level, SDIP, SDIN ......................+3.0V Continuous Power Dissipation (TA = +85°C) .......................1.3W Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VEE = -4.5V ±5%, VTTL = 5V ±5%, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER Positive Voltage Supply (with respect to ground) Negative Voltage Supply (with respect to ground) Static Supply Current from VTTL Static Supply Current from VEE SYMBOL CONDITIONS MIN TYP MAX UNITS VTTL 4.75 5.00 5.25 V VEE -4.725 -4.50 -4.275 V ITTL 2.4 5 mA IVEE 150 210 mA ECL INPUTS: EXC, SDIP, SDIN Input High Voltage VIH -1165 -870 mV Input Low Voltage VIL -1830 -1475 mV Input High Current IIH VIN = VOH (typ) 0 100 µA Input Low Current IIL VIN = VOL (typ) -100 100 nA ECL OUTPUTS: RCOP, RCON, RDOP, RDON Output High Voltage VOH Loaded with 50Ω to -2V -1025 -955 -870 mV Output Low Voltage VOL Loaded with 50Ω to -2V -1830 -1705 -1550 mV Output High Voltage VOH Loaded with 470Ω to VEE -1025 -955 -870 mV Output Low Voltage VOL Loaded with 470Ω to VEE -1830 -1705 -1620 mV LOW-POWER ECL OUTPUT: CRP TTL INPUTS: CRS, RST, EXCS Input High Voltage VIH Input Low Voltage VIL 2 Input High Current IIH VTTL = 5.00V, VIN = 2V Input Low Current IIL V 0.8 V 0 40 µA VTTL = 5.00V, VIN = 0.8V 0 40 µA VR = PHADJ = 0, TA = +25°C 0 10 µA PHASE ADJUST INPUTS: PHADJ, VR Input Bias Current 2 IBIAS _______________________________________________________________________________________ 155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector MAX3270 AC ELECTRICAL CHARACTERISTICS (continued) (VEE = -4.5V, VTTL = 5V, TA = 25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ECL OUTPUTS: RDOP, RDON, RCOP, RCON Transition Time 20% to 80% tr, tf Time Difference between RDO and RCO TD Loaded with 50Ω to -2V and 5pF to GND Loaded with 50Ω to -2V and 5pF to GND 600 ps 100 ps PFD AND FILTER AMPLIFIER TEST LEVELS Output Offset Voltage of the Monitor Amplifier VO PHADJ = 0, FILP and FILN shorted -35 35 mV Gain of the Monitor Amplifier GFM PHADJ = 0 0.95 1.05 V/V Filter Amplifier Open-Loop Voltage Gain GOL FILP and FILN open 21 26 dB VCO TEST PARAMETERS; CPR OUTPUT FILP and FILN shorted, PFD = neutral state Center Frequency FO 38.00 39.50 Frequency Range DFO FILP - FILN = 1.6V 6 10 MHz KO FILP - FILN = 1.6V 3.75 6 MHz/V KOV FILP and FILN shorted 550 kHz/V Mean Frequency Sensitivity Frequency Sensitivity to Power-Supply Voltage PLL ELECTRICAL SPECIFICATIONS Frequency of VCO FO Incremental Tuning Sensitivity (Incremental Slope, ∆f/∆Vt) KO ft = 622.08MHz MHz 622.08 MHz 75 MHz/V Phase-Detector Gain KD 192 mV/rad Transconduction Gain of Filter Amplifier Gm 1.25 mA/V KPHADJ 2 rad/V Phase Offset Sensitivity, ∆Φ/∆PHADJ __________________________________________Typical Operating Characteristics VEE SUPPLY CURRENT vs. TEMPERATURE CRP FREE-RUNNING FREQUENCY (VCO/16) vs. DIE TEMPERATURE 180 175 -4.5V 170 165 39.0 -4.25V 38.9 MEASURED 38.8 38.7 38.6 160 38.5 155 38.4 150 MAX3270-TOC5 -4.75V FREQUENCY (MHz) VEE SUPPLY CURRENT (mA) 185 MAX3270-TOC9 190 38.3 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) _______________________________________________________________________________________ 3 __________________________________________Typical Operating Characteristics MAX3270-TOC1 JITTER TOLERANCE (155Mbps, 223-1 PRBS) AMPLITUDE (UI p-p) 10.0 1.0 DATA BELLCORE MASK 0.1 10 100 1k 10k 100k 1M FREQUENCY (Hz) MAX3270-TOC2 JITTER TOLERANCE (622Mbps, 223-1 PRBS) 10.0 AMPLITUDE (UI p-p) MAX3270 155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector 1.0 DATA BELLCORE MASK 0.1 10 100 1k 10k 100k FREQUENCY (Hz) 4 _______________________________________________________________________________________ 1M 155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector 155Mbps RECOVERED CLOCK AND RETIMED DATA (SINGLE ENDED) 622Mbps RECOVERED CLOCK AND RETIMED DATA (SINGLE ENDED) DATA DATA CLOCK CLOCK 2ns/div RECOVERED CLOCK JITTER (155Mbps, 27-1 PRBS, 5.1ps RMS) 500ps/div RECOVERED CLOCK JITTER (155Mbps, 1-0 PATTERN, 4.7ps RMS) RF = 20Ω CF = 2.2µF RF = 20Ω CF = 2.2µF 10ps/div Mean 40.61ns RMS∆ 5.13ps PkPk 45.6ps RECOVERED CLOCK JITTER (622Mbps 27-1 PRBS 9.0ps RMS) RF = 20Ω CF = 2.2µF 10ps/div 10ps/div µ±1σ µ±2σ µ±3σ 68.961% 95.844% 99.717% Mean 40.65ns RMS∆ 4.7ps PkPk 38.4ps µ±1σ µ±2σ µ±3σ 69.674% 95.558% 99.698% Mean 38.68ns RMS∆ 9.049ps PkPk 79.4ps µ±1σ µ±2σ µ±3σ 69.747% 95.453% 99.582% _______________________________________________________________________________________ 5 MAX3270 __________________________________________Typical Operating Characteristics MAX3270 155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector ______________________________________________________________Pin Description 6 PIN NAME 1 GVEE Guard-Ring Negative Supply to Substrate: -4.5V FUNCTION 2 AVEE1 Negative Supply for Input Buffers: -4.5V 3 SDIP Serial Data Input: 155Mbps or 622Mbps. Differential ECL Positive. 4 SDIN Serial Data Input: 155Mbps or 622Mbps. Differential ECL Negative. 5 AVCC Ground for Input Buffers: 0V 6 FM 7 AVCC Guard-Ring Positive Supply to Epi: 0V 8 FILG Loop Filter Ground. This pin connects to an external filter. 9 FILP Loop Filter Positive. This pin connects to an external filter. 10 FILN Loop Filter Negative. This pin connects to an external filter. 11 VTTL TTL Positive Supply: +5.0V 12 AVEE2 Negative Supply for VCO: -4.5V 13 EXCS External Clock-Select TTL Input. A logical high selects the external clock. 14 EXC 15, 16 AVCC Ground for VCO: 0V 17, 19, 38, 39 DVCC Digital Ground for Mux: 0V 18 CRS Clock-Rate Select TTL Input. This selects the clock rate to be either 155Mbps or 622Mbps. A logichigh level selects the 622Mbps mode. Resets all digital flip-flops, TTL input. Reset is assert when low. Frequency Monitor Output. This pin monitors the input voltage to the VCO. When the PLL is locked, the pin will be ≅ 0V. External Clock. Single-ended ECL input. 20 RST 21, 22, 34, 35, 36 DVEE Digital Negative Supply: -4.5V 23, 33, 37, 40, 43, 44 N.C. No Connection 24, 27, 29, 32 OVCC Output Driver Ground: 0V 25 RDON Negative Recovered Data Output, differential ECL output: 155Mbps or 622Mbps. 26 RDOP Positive Recovered Data Output, differential ECL output: 155Mbps or 622Mbps. 28 CRP 30 RCON Negative Recovered Clock Output, differential ECL output: 155Mbps or 622Mbps. 31 RCOP Positive Recovered Clock Output, differential ECL output: 155Mbps or 622Mbps. 41 PHADJ Phase Adjust. This is an analog adjustment that varies the static phase between the input data and the recovered clock. If not used, this input should be grounded. The range is from -1V to 1V. 42 VR Clock-Reference Output Divide-by-4. ECL low-power single-ended: 38Mbps or 155Mbps. Phase Reference Voltage: 0V. The PHADJ pin compares to this voltage. Set to ground. _______________________________________________________________________________________ 155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector The block diagram of Figure 1 shows the MAX3270’s architecture. The phase-locked loop (PLL) consists of a phase/frequency detector (PFD), a loop filter amplifier, and a voltage-controlled oscillator (VCO). Phase Detector The phase detector produces a voltage proportional to the phase difference of the incoming data and the output of the recovered clock. Because of its feedback nature, the PLL will drive the error voltage to zero, making the phase difference zero and aligning the recovered clock to the incoming data. An external phase-adjustment pin (PHADJ) allows the user to vary phase alignment. Frequency Detector A frequency detector is also incorporated into the PLL. Frequency detection aids in the acquisition of the input data; this frequency-aided acquisition is necessary during start-up conditions, since the input data stream and VCO difference frequency may be outside the PLL PHADJ VR FILP bandwidth. The input data stream is sampled by quadrature components of the VCO clock, generating a difference frequency. Depending on the rotation of the difference frequency, the PFD will drive the VCO so that the difference frequency is driven to zero. Once frequency acquisition is obtained, the frequency detector will return to a neutral state. Loop Filter and VCO The PLL is a second-order transfer function whose bandwidth is set by the loop filter. The VCO is integrated into the PLL and always operates at 622MHz. The center frequency is tightly controlled by laser trimming, limiting frequency drift when lock is lost. 155Mbps or 622Mbps mode is selected by the clock-rate select (CRS) pin. CRS selects the inputs to multiplexer MUX2. The internal VCO can be bypassed with an external clock applied to the EXC input. The external clock select (EXCS) controls the input selections to multiplexers MUX1 and MUX2. FILN FM 100k ECL SDIP Q D CLK SDIN PHASE/FREQ DETECTOR VCO 622.08MHz FILTER AMP DIVIDEBY-4 CLK RST RDOP RECOVERED DATA RDON 100k ECL CRP 38/155MHz 100k ECL RCOP RECOVERED CLOCK RCON EXCS MUX 2 MUX 3 OUTPUT MAX3270 1 0 155MHz MUX 1 0 INPUT 0 622MHz 1 EXC 1 RST CRS Figure 1. Block Diagram _______________________________________________________________________________________ 7 MAX3270 _______________Detailed Description MAX3270 155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector __________________Design Procedure Selecting the Data Rate MAX3270 The MAX3270 is intended for use in SDH/SONET systems operating at 155.52Mbps or 622.08Mbps data rates. TTL inputs (CRS and EXCS) are provided for selecting the recovered clock rate (Table 1). It is also possible to switch to an externally supplied clock by enabling the EXC input. The EXC input is a high-speed single-ended ECL interface capable of handling serial clock rates of 155MHz and 622MHz. F(s) Gm FILP FILG Rf Rf Cf Cf FILN s Gm ( ___ wz + 1) F(s) = ____________ Cf s 1 wz = ____ Rf Cf Table 1. MAX3270 Logic Table EXCS CRS RCOP/RCON CRP 0 1 155.52Mbps 38.88Mbps 0 0 622.08Mbps 155.52Mbps 1 0 EXC EXC/4 1 1 EXC/4 EXC/16 Setting the Loop Filter The loop filter within the PLL consist of a transconductance amplifier and the external filter elements Rf and Cf (Figure 2). The closed-loop bandwidth of a PLL can be approximated by: KD KO Gm Rf where KD is the gain of the phase detector, KO is the gain of the VCO, and Gm is the transconductance of the filter amplifier. Because this filter is an integrator, a zero in the open-loop gain is required for stability. This zero is set by the following equation: wz = 1 / (Rf Cf) where the recommended external values are Rf = 20Ω and Cf = 2.2µF. To decrease the PLL’s closed-loop bandwidth, reduce the value of Rf. Decreasing this bandwidth will improve the MAX3270’s jitter transfer performance but reduce jitter tolerance. The MAX3270 has been designed (using the recommended values of Rf and Cf) to meet the Bellcore and CCITT specifications for jitter tolerance of a Network Element. Carefully consider the application if a reduction in loop bandwidth is desired. By reducing Rf an order of magnitude, the PLL’s bandwidth becomes more sensitive to the internal tolerances of the IC. As a result, the loop bandwidth may have a wider variation. If Rf is reduced, then Cf should also be increased to maintain loop stability and minimize jitter peaking. 8 Rf = 20Ω Cf = 2.2µF Figure 2. Loop Filter RECOVERED DATA OUTPUT (213-1 PRBS WITH 200 CONSECUTIVE ONES BER <10-12, 622Mbps) PRBS 200 ONES 1.532µs 100ns/div 2.532µs Figure 3. Recovered Data Output The MAX3270 is optimally designed to acquire lock and to provide a bit-error rate (BER) of less than 10-12 for long strings of consecutive zeros or ones. Using the recommended external values for Rf = 20Ω and Cf = 2.2µF, measured results show that the MAX3270 can tolerate more than 200 consecutive ones or zeros. Figure 3 shows a bit stream of 213 - 1 PRBS with 200 consecutive ones. _______________________________________________________________________________________ 155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector supply decoupling should be placed as close to the VEE and VTTL pins as possible. AVEE1, AVEE2 and GVEE should each have their own bypass/decoupling elements, independent of each other and any other 4.5V supply. Make sure to isolate the inputs from the outputs to reduce feedthrough. ECL INPUTS ECL OUTPUTS Zo = 50Ω Zo = 50Ω Zo = 50Ω 50Ω 50Ω Phase Adjust In some applications, the optimum alignment point between the recovered clock and the serial data is not at the center of the eye diagram. The MAX3270 has a PHADJ input that can be used in these applications to introduce a phase difference between the recovered clock and the serial data. When no phase difference is desired, this input should be set to 0V. The VR pin is the reference input for PHADJ and is normally tied to GND. 50Ω -2V -4.5V -4.5V MAX3270 ECL INPUTS ECL OUTPUTS Zo = 50Ω CRP 450Ω 90.9Ω Zo = 50Ω MAX3270 50Ω Lock Detection The MAX3270 has an output (FM) that monitors the input voltage to the VCO. FM is an analog output that can be used as a flag to indicate that the PLL is locked. Under normal operation, the loop is locked and the FM output is approximately equal to 0V. When the PLL is unlocked, the VCO will drift. The FM output monitors this drift and will equal approximately ±1V in the limit. 90.9Ω Zo = 50Ω -2V __________Applications Information 111Ω 90.9Ω 90.9Ω Zo = 50Ω Zo = 50Ω 111Ω 111Ω 111Ω -4.5V CRP 450Ω -4.5V 50Ω to -2V TERMINATION THEVENIN EQUIVALENT TERMINATION Figure 4. Typical Input and Output Terminations _______________________________________________________________________________________ 9 MAX3270 Input and Output Termination The MAX3270 data and clock I/Os (SDIP, SDIN, RDOP, RDON, RCOP, RCON, and EXC) are open emitters, designed to interface with ECL signal levels. It is important to bias these ports appropriately. A circuit that provides a Thevenin equivalent of 50Ω to -2V should be used with fixed-impedance transmission lines for proper termination. Figure 4 shows some typical input and output termination methods. The serial data input signals (SDIP and SDIN) are the differential inputs to an emitter coupled pair. As a result, the MAX3270 can accept differential input signal levels as low as 250mV. The serial input (SDIP) can also be driven single-ended by externally biasing SDIN to the center of the voltage swing (approximately -1.3V). Make sure that the differential inputs and outputs each see the same termination impedance for balanced operation. CRP is also an open-emitter ECL output, but it requires a termination resistor of 450Ω to -4.5V. If this output is not used, reduce power by connecting CRP to V EE through a resistor valued at 10kΩ or more. The MAX3270’s performance can be greatly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductances and using fixed-impedance transmission lines on the data and clock signals. Power- __________________Pin Configuration 44 43 42 41 40 39 38 37 36 35 34 N.C. N.C. VR PHADJ N.C. DVCC DVCC N.C. DVEE DVEE DVEE TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 MAX3270 33 32 31 30 29 28 27 26 25 24 23 N.C. OVCC RCOP RCON OVCC CRP OVCC RDOP RDON OVCC N.C. 12 13 14 15 16 17 18 19 20 21 22 GVEE AVEE1 SDIP SDIN AVCC FM AVCC FILG FILP FILN VTTL AVEE2 EXCS EXC AVCC AVCC DVCC CRS DVCC RST DVEE DVEE MAX3270 155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector MQFP 10 ______________________________________________________________________________________ 155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector DIM DETAIL "A" SEE DETAIL "A" C α A2 L A A1 D D1 D3 E A A1 A2 b C D D1 D3 E E1 E3 e L α MILLIMETERS MIN MAX 2.032 2.388 0.102 0.254 1.930 2.134 0.305 0.457 0.102 0.254 12.954 13.462 9.906 10.109 3.429 REF 12.954 13.462 9.906 10.109 3.429 REF 0.800 REF 0.660 0.940 0° 10° INCHES MIN MAX 0.080 0.094 0.004 0.010 0.076 0.084 0.012 0.018 0.004 0.010 0.510 0.530 0.390 0.398 0.315 REF 0.510 0.530 0.390 0.398 0.315 REF 0.315 REF 0.025 0.037 0° 10° 21-0826A E1 E3 44-PIN MQFP METRIC QUAD FLAT PACK b e ______________________________________________________________________________________ 11 MAX3270 ________________________________________________________Package Information MAX3270 155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.