19-1537; Rev 0; 7/99 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier ____________________________Features ♦ Single +3.3V or +5.0V Power Supply ♦ Exceeds ITU/Bellcore SDH/SONET Regenerator Specifications ♦ Low Power: 237mW at +3.3V ♦ Selectable Data Inputs, Differential PECL or Analog ♦ Received-Signal-Strength Indicator ♦ Loss-of-Power and Loss-of-Lock Monitors ♦ Differential PECL Clock and Data Outputs ♦ No External Reference Clock Required _________________Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX3676EHJ -40°C to +85°C 5mm 32 TQFP MAX3676E/D -40°C to +85°C Dice* *Contact factory for availability. Dice are designed to operate over a -40°C to +140°C junction temperature (Tj) range, but are tested and guaranteed at Tj = +45°C. ________________________Applications SDH/SONET Receivers and Regenerators SDH/SONET Access Nodes Add/Drop Multiplexers ATM Switches Digital Cross-Connects Pin Configuration appears at end of data sheet. ___________________________________________________ Typical Operating Circuit +3.3V CLOL 0.01µF +3.3V 2.2µF +3.3V 130Ω INSEL FILT PHADJ+ FIL+ PHADJ- FIL- DDI+ VCC LOL SDO+ PHOTODIODE CIN 0.01µF MAX3664 INREF ZO = 50Ω ZO = 50Ω DDISDO- 100pF 130Ω 0.1µF 0.01µF OUT+ ZO = 50Ω ADI+ 82Ω MAX3676 82Ω +3.3V 100Ω IN OUTGND ZO = 50Ω SCLKO+ ADI- 130Ω C +3.3V IN 0.01µF COMP 130Ω SCLKOZO = 50Ω VCC 220pF CFILT OLC+ OLC- GND RSSI INV VTH LOP CF 47nF COLC 33nF ZO = 50Ω 82Ω 82Ω R2 R1 20k ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3676 _____________________ General Description The MAX3676 is a complete clock-recovery and dataretiming IC incorporating a limiting amplifier. It is intended for 622Mbps SDH/SONET applications and operates from a single +3.3V supply. The MAX3676 is designed for both section-regenerator and terminal-receiver applications in OC12/STM-4 transmission systems. Its jitter performance exceeds all SONET/SDH specifications. The MAX3676 has two differential input amplifiers: one accepts positive-referenced emitter-coupled logic (PECL) levels, while the other accepts small-signal analog levels. The analog inputs access the limiting amplifier stage, which provides both a received-signal-strength indicator (RSSI) and a programmable-threshold loss-ofpower (LOP) monitor. Selecting the PECL amplifier disables the limiting amplifier, conserving power. A loss-of-lock (LOL) monitor is also incorporated as part of the fully integrated phase-locked loop (PLL). MAX3676 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +6.5V Input Voltage Levels, DDI+, DDI-, ADI+, ADI- ...........................-0.5V to (VCC + 0.5V) Input Differential Voltage (ADI+) - (ADI-)...............................±3V PECL Output Currents, SDO+, SDO-, SCLKO+, SCLKO- ...100mA LOL, LOP, INSEL, PHADJ+, PHADJ- .........-0.5V to (VCC + 0.5V) FIL+, FIL-, OLC+, OLC-, RSSI, VTH ...........-0.5V to (VCC + 0.5V) (OLC+) - (OLC-).....................................................................±3V (FIL+) - (FIL-) ..................................................................±700mV CFILT ...............................................(VCC - 2.5V) to (VCC + 0.5V) INV.........................................................................-0.5V to +2.0V Continuous Power Dissipation (TA = +85°C) TQFP (derate 11.1mW/°C above +85°C) .....................721mW Operating Junction Temperature Range ...........-40°C to +150°C Storage Temperature Range .............................-65°C to +150°C Processing Temperature (die) .........................................+400°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2) PARAMETER Supply Current SYMBOL ICC CONDITIONS MAX3676EHJ, PECL outputs unterminated MIN TYP MAX INSEL = VCC 72 111 INSEL = GND 51 81 UNITS mA PECL Input Voltage High VIH VCC - 1.16 VCC - 0.88 PECL Input Voltage Low VIL VCC - 1.81 VCC - 1.48 V PECL Input Current High IIH -10 10 µA PECL Input Current Low IIL µA PECL Output Voltage High VOH PECL Output Voltage Low VOL LOP, LOL Voltage High VOH LOP, LOL Voltage Low VOL INV Input Bias Voltage -10 10 TA = 0°C to +85°C VCC - 1.025 VCC - 0.88 TA = -40°C VCC - 1.085 VCC - 0.88 TA = 0°C to +85°C VCC - 1.81 VCC - 1.620 TA = -40°C VCC - 1.83 VCC - 1.555 2.4 1.10 1.23 Note 1: Dice are tested at Tj = +45°C, VCC = +4.25V. Note 2: At TA = -40°C, DC characteristics are guaranteed by design and characterization. 2 V V V 0.1 4kΩ between INV and VTH V _______________________________________________________________________________________ 0.4 V 1.30 V 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier (VCC = +3.0V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS MIN Differential Input Voltage Range VID BER < 10-10, ADI inputs (Note 5) Input-Referred Noise VN ADI inputs Power-Detect Hysteresis Limiting Amplifier SmallSignal Bandwidth RSSI Output Voltage Threshold Voltage VTH 0.003 MAX UNITS 1.2000 Vp-p 80 3 (Notes 6, 7) BW TYP (Note 8) 650 (ADI+) - (ADI-) = 2mVp-p 1.40 (ADI+) - (ADI-) = 20mVp-p 1.93 (Note 7) 1.41 -2 LOP Threshold Accuracy (Note 7) RSSI Linearity (ADI+) - (ADI-) = 2mVp-p to 50mVp-p RSSI Slope µVRMS 6 dB MHz V V +2 dB ±0.7 % (ADI+) - (ADI-) = 2mVp-p to 50mVp-p (Note 9) 26 mV/dB Loop Bandwidth CF = 2.2µF 250 500 kHz Jitter Generation (Note 10) CF = 2.2µF 2.0 2.6 mUI Jitter-Transfer Peaking CF = 2.2µF 0.03 0.08 dB 8.9 f = 10kHz Jitter Tolerance (Note 11) CF = 2.2µF f = 25kHz (Note 12) 3.64 f = 250kHz 0.55 0.77 f = 1MHz 0.45 0.69 Maximum Consecutive Input Run Length (1 or 0) Clock Transition Time Data Transition Time UI 1200 tr, tf 20% to 80% tr, tf 20% to 80% Serial Clock-to-Q Delay tCLK-Q Serial Clock Frequency fSCLK 205 140 Bits 245 ps 180 230 ps 275 400 622.08 ps MHz Note 3: AC parameters are guaranteed by design and characterization. Note 4: The MAX3676 is characterized with a PRBS of 223 - 1 maintaining a BER of ≤ 10-10 having a confidence level of 99.9%. Note 5: A lower minimum input voltage of 2mVp-p is achievable; however, the LOP hysteresis is not guaranteed below 3.6mVp-p. Note 6: Hysteresis = 20log(VRELEASE / VASSERT). Note 7: R1 = 20kΩ, R2 = 3.0kΩ, resulting in VRELEASE ≈ 3.6mVp-p. Note 8: Small-signal bandwidth cannot be measured directly. Note 9: RSSI slope = [VRSSI2 - VRSSI1] / [20log (VID2 / VID1)]. Note 10: 1UI = 1 unit interval = (622.08MHz)-1 = 1.608ns. Note 11: At jitter frequencies <10kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. The low-frequency jitter tolerance outperforms the instrument’s measurement capability. Note 12: See Typical Operating Characteristics for worst-case distribution. _______________________________________________________________________________________ 3 MAX3676 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) 10-2 MAX3676 toc02 MAX3676 toc01 223 -1 PATTERN BIT ERROR RATE vs. ADI INPUT VOLTAGE RECOVERED CLOCK JITTER 223 -1 PATTERN 223 -1 PATTERN 10-3 10-4 BIT ERROR RATE DATA MAX3676 toc03 RECOVERED DATA AND CLOCK (SINGLE ENDED) 10-5 10-6 10-7 10-8 10-9 CLOCK 10-10 WIDEBAND RMS JITTER = 5.84ps 400ps/div 10-11 10-12 400µ 500µ 600µ 700µ 800µ 900µ 1m 1.1m 1.2m 20ps/div INPUT VOLTAGE (V) DISTRIBUTION OF JITTER TOLERANCE (WORST-CASE CONDITIONS) BELLCORE MASK 20 15 10 5 0 0.1 10k 100k 1M JITTER FREQUENCY (Hz) 4 10M 1.5 2.0 2.2 2.4 2.6 2.8 3.0 JITTER TOLERANCE (UIp-p) 3.5 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 -2.4 -2.6 -2.8 -3.0 MAX3676 toc05 fJITTER = 25kHz VCC = +3.0V TA = +85°C JITTER TRANSFER JITTER TRANSFER (dB) 1 MEAN = 2.42UI σ = 0.227UI 25 PERCENT OF UNITS (%) 223 -1 PATTERN 30 MAX3676 toc04 10 MAX3676 toc06 JITTER TOLERANCE INPUT JITTER (UIp-p) MAX3676 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier BELLCORE MASK 223 - 1 PRBS 2k 10k 100k JITTER FREQUENCY (Hz) _______________________________________________________________________________________ 700k 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier 2.5 RSSI (V) 3.5 223 -1 PATTERN 2.1 1.9 1010 PATTERN 1.7 3.0 1.5 223 -1 PATTERN LOP RELEASE LOP ASSERT 10 2.5 1.3 -20 0 20 40 60 80 1 1.1 100 0.1 AMBIENT TEMPERATURE (°C) 1.0 10 100 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 1000 DETECTOR THRESHOLD VOLTAGE, VTH (V) INPUT VOLTAGE (mVp-p) SUPPLY CURRENT vs. TEMPERATURE RECEIVED-SIGNAL-STRENGTH INDICATOR vs. INPUT VOLTAGE 2.7 223 -1 PATTERN VCC = +3.3V OR +5.0V 2.5 100 MAX3676 toc10 2.3 90 SUPPLY CURRENT (mA) -40 2.1 1.9 1.7 1.5 MAX3676 toc11 2.0 RSSI (V) HYSTERESIS (dB) 2.3 4.0 100 ANALOG VOLTAGE (mVp-p) 4.5 2.7 MAX3676 toc08 223 -1 PATTERN VCC = +3.3V OR +5.0V MAS3676 toc07 5.0 LOSS-OF-POWER ASSERT AND RELEASE LEVEL vs. DETECTOR THRESHOLD VOLTAGE RECEIVED-SIGNAL-STRENGTH INDICATOR vs. INPUT VOLTAGE MAX3676 toc09 LOSS-OF-POWER HYSTERESIS vs. TEMPERATURE VCC = +5.0V 80 70 60 50 VCC = +3.3V 40 1.3 30 1.1 0.1 1.0 10 100 INPUT VOLTAGE (mVp-p) 1000 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX3676 Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier MAX3676 Pin Description 6 PIN NAME FUNCTION 1 OLC+ Positive Offset-Correction Loop Capacitor Input 2 OLC- Negative Offset-Correction Loop Capacitor Input 3 RSSI Received-Signal-Strength Indicator Output 4, 8, 16, 24, 25 GND Supply Ground 5 INV Op Amp Inverting Input. Attach to ground if op amp is not used. 6 VTH Voltage Threshold Input. Threshold voltage for loss-of-power monitor. Attach to VCC if LOP function is not used. 7 LOP Loss-of-Power Output, TTL. Limiting amplifier loss-of-power monitor. Asserts high when input signal is below threshold set by VTH. 9, 12, 15, 18, 21, 31 VCC Positive Supply Voltage 10 SCLKO- Negative Serial-Clock Output, PECL, 622.08MHz. SDO- is clocked out on the falling edge of SCLKO-. 11 SCLKO+ Positive Serial-Clock Output, PECL, 622.08MHz. SDO+ is clocked out on the rising edge of SCLKO+. 13 SDO- Negative Serial-Data Output, PECL, 622.08Mbps 14 SDO+ Positive Serial-Data Output, PECL, 622.08Mbps 17 LOL 19 PHADJ- Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCC if not used. 20 PHADJ+ Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCC if not used. 22 FIL- Negative Filter Input. PLL loop filter connection. 23 FIL+ Positive Filter Input. PLL loop filter connection. 26 DDI+ Positive Digital Data Input, PECL, 622.08Mbps serial-data stream 27 DDI- Negative Digital Data Input, PECL, 622.08Mbps serial-data stream 28 INSEL 29 ADI- Negative Analog Data Input, 622.08Mbps serial-data stream 30 ADI+ Positive Analog Data Input, 622.08Mbps serial-data stream 32 CFILT RSSI Filter Capacitor Input Loss-of-Lock Output, TTL. PLL loss-of-lock monitor, active low (see Design Procedure). Input Select. Connect to GND to select digital data inputs or VCC for analog data inputs. _______________________________________________________________________________________ 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier MAX3676 PHADJ+ PHADJ- LOL FIL+ FIL- VCC SDO+ 6k D Q SDOPECL DDI+ SCLKO+ I DDI- Σ PHASE/FREQ DETECTOR PECL FILTER VCO PECL SCLKO- Q INSEL 622.08MHz VCC ADIADI+ LIMITER 42dB BIAS 1.23V 6k POWER DETECT OFFSET CORRECTION OLC+ OLC- MAX3676 CFILT RSSI INV VTH LOP Figure 1. Functional Diagram _______________Detailed Description The block diagram in Figure 1 shows the MAX3676’s architecture. It consists of a limiting-amplifier input stage followed by a fully integrated clock/data-recovery (CDR) block implemented with a PLL. The input stage is selectable between a limiting amplifier or a simple PECL input buffer. The limiting amplifier provides an LOP monitor and an RSSI output. The PLL consists of a phase/frequency detector (PFD), a loop filter amplifier, and a voltage-controlled oscillator (VCO). Limiting Amplifier The MAX3676’s on-chip limiting amplifier accepts an input signal level from 3.0mVp-p to 1.2Vp-p. The amplifier consists of a cascade of gain stages that include full-wave logarithmic detectors. The combined smallsignal gain is approximately 42dB, and the -3dB bandwidth is 650MHz. Input-referred noise is typically 80µVRMS, providing excellent sensitivity for small-amplitude data streams. In addition to driving the CDR, the limiting amplifier provides both an RSSI output and an LOP monitor that allow the user to program the threshold voltage. The RSSI circuitry provides an output voltage that is linearly proportional to the input power (in decibels) detected between the ADI+ and ADI- input pins and is sensitive enough to reliably detect signals as small as 2mVp-p (see Typical Operating Characteristics). Input DC offset reduces the accuracy of the power detector; therefore, an integrated feedback loop is included that automatically nulls the input offset of the gain stage. The addition of this offset-correction loop requires that the input signal be AC-coupled when using the ADI+ and ADI- inputs. Finally, for applications that do not require the limiting amplifier, selecting the digital inputs conserves power by turning off the postamplifier block. _______________________________________________________________________________________ 7 MAX3676 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier Phase Detector The phase detector produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the incoming data. The external phase adjustment pins (PHADJ+, PHADJ-) allow the user to vary the internal phase alignment. Frequency Detector The frequency detector incorporated into the PLL uses the input data stream edges to sample the quadrature components of the VCO clock. This generates a difference frequency that aids acquisition during start-up. Depending on the polarity of the difference frequency, the PFD drives the VCO so that the difference frequency is reduced to zero. Once frequency acquisition is obtained, the frequency detector returns to a neutral state. Loop Filter and VCO The VCO is fully integrated, while the loop filter requires an external R-C network. This filter network determines the bandwidth and peaking of the second-order PLL. __________________Design Procedure Received-Signal-Strength Indicator The RSSI output voltage is insensitive to temperature and supply fluctuations. The power detector functions as a broadband power meter that detects the total RMS power of all signals within the detector bandwidth (including input signal noise). The RSSI voltage varies linearly (in decibels) for inputs of 2mVp-p to 50mVp-p. The slope over this input range is approximately 26mV/dB. The high-speed RSSI signal is filtered to an RMS level with one external capacitor tied from CFILT to VCC. The impedance looking into CFILT is about 500Ω to VCC. As a result, the lower -3dB cutoff frequency is set by the following simple relationship: [ ( ) ] fFILT = 1 / 2π 500 CF For 622Mbps applications, Maxim recommends a cutoff frequency of 6.8kHz, which requires CF = 47nF. The RSSI output is designed to drive a minimum load resistance of 100kΩ to ground and a maximum of 20pF. Loads greater than 20pF must be buffered by a series resistance of 100kΩ (i.e., voltmeter). Input Offset Correction The on-chip limiting amplifier provides more than 42dB of gain. A low-frequency feedback loop is integrated 8 into the MAX3676 to remove the input offset. DC-coupling to the ADI+ and ADI- inputs is not allowed, as this would prevent the proper functioning of the DC offsetcorrection circuitry. The differential input impedance (ZIN) is approximately 2.5kΩ. The impedance between OLC+ and OLC- (ZOLC) is approximately 120kΩ. Take care when setting the combined low-frequency cutoff (fCUTOFF), due to the input DC-blocking capacitor (CIN) and the offset correction loop capacitor (COLC). See Table 1 for selecting the values of CIN and COLC. These values ensure that the poles associated with CIN and COLC work together to provide a flat response at the lower -3dB corner frequency (no gain peaking). CIN must be a low-TC, high-quality capacitor of type X7R or better in order to minimize fCUTOFF deviations. COLC must be a capacitor of type Z5U or better. Loss-of-Power Monitor An LOP monitor with a user-programmable threshold and a hysteresis comparator is also included with the limiting amplifier circuitry. Internally, one comparator input is tied to the RSSI output signal, and the other is tied to the threshold voltage (VTH), which is set externally and provides a trip point for the LOP indication. A low-voltage, low-drift op amp, referenced to an internal bandgap voltage (1.23V), is supplied for programming a supply independent threshold voltage. This op amp requires two external resistors to program the LOP trip point. VTH is programmable from 1.23V to 2.6V using the equation: VTH = 1.23(1 + R2 / R1) The op amp can source only 100µA of current. Therefore, an R1 value of 20kΩ is recommended for proper operation. The input bias current of the op amp at the INV pin is less than ±100nA. Table 1. Setting the Low-Frequency Cutoff CIN COLC COMBINED LOW fCUTOFF (kHz) 0.022µF 0.15µF 3.0 0.010µF 0.1µF 6.8 6800pF 0.082µF 10 4700pF 0.033µF 13.5 2200pF 0.015µF 29 1000pF 0.01µF 68 470pF 3300pF 135 330pF 2200pF 190 220pF 1500pF 290 _______________________________________________________________________________________ 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier MAX3676 The comparator is configured with an active-high LOP output. An on-chip, 6kΩ pull-up resistor is provided to reduce the external part count. OPEN-LOOP GAIN Setting the Loop Filter The MAX3676 is designed for both regenerator and receiver applications. Its fully integrated PLL is a classic second-order feedback system, with a loop bandwidth (fL) fixed at 250kHz. The external capacitor, CF, can be adjusted to set the loop damping. Figures 2 and 3 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CF, and can be approximated according to: 1 fZ = 2π(90) CF CF = 0.22µF fZ = 8.04kHz CF = 2.2µF fZ = 804Hz f (Hz) 100 1k 10k 100k 1M 10M For an overdamped system (fZ/fL) <0.25, the jitter peaking (MP) of a second-order system can be approximated by: Figure 2. Open-Loop Transfer Function For example, using CF = 0.22µF results in a jitter peaking of 0.27dB. Reducing CF below 0.22µF may result in PLL instability. The recommended value for CF is 2.2µF to guarantee a maximum jitter peaking of less than 0.1dB. The MAX3676 is optimally designed to acquire lock and to provide a bit-error rate (BER) of less than 10 -10 for long strings of consecutive zeros and ones. Measured results show that the MAX3676 can tolerate 1200 consecutive ones or zeros. Decreasing CF reduces the number of tolerated consecutive identical zeros and ones. CF must be a low-TC, high-quality capacitor of type X7R or better. H(J2πf) (dB) CF = 0.22µF 0 CLOSED-LOOP GAIN f MP = 20log1+ Z fL -3 CF = 2.2µF Lock Detect The MAX3676’s LOL monitor indicates when the PLL is locked. Under normal operation, the loop is locked and the LOL output signal is high. When the MAX3676 loses lock, a fast negative-edge transition occurs on LOL. The output level remains at a low level (held by CLOL) until the loop reacquires lock (Figure 4). f (kHz) 100 1k 10k 100k 1M 10M Figure 3. Closed-Loop Transfer Function _______________________________________________________________________________________ 9 Note that the LOL monitor is only valid when a data stream is present on the inputs to the MAX3676. As a result, LOL does not detect a loss-of-power condition resulting from a loss of the incoming signal. See the Loss-of-Power Monitor section for this type of indicator. Input and Output Terminations The MAX3676 digital data and clock I/Os (DDI+, DDI-, SDO+, SDO-, SCLK+, and SCLK-) are designed to interface with PECL signal levels. It is important to bias these ports appropriately. A circuit that provides a Thevenin equivalent of 50Ω to VCC - 2V should be used with fixed-impedance transmission lines for proper termination. Make sure that the differential outputs have balanced loads. The digital data input signals (DDI+ and DDI-) are differential inputs to an emitter-coupled pair. As a result, the MAX3676 can accept differential input signals as low as 250mV. These inputs can also be driven singleended by externally biasing DDI- to the center of the voltage swing. The MAX3676’s performance can be greatly affected by circuit board layout and design. Use good high-fre- quency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the data and clock signals. Power-supply decoupling should be placed as close to VCC as possible. Take care to isolate the input from the output signals to reduce feedthrough. __________Applications Information Driving the Limiting Amplifier Single-Ended There are three important requirements for driving the limiting amplifier from a single-ended source (Figure 5): 1) There must be no DC-coupling to the ADI+ and ADIinputs. DC levels at these inputs disrupt the offsetcorrection loop. 2) The terminating resistor RT (50Ω) must be referenced to the ADI- input to minimize common-mode coupling problems. 3) The low-frequency cutoff for the limiting amplifier is determined by either C IN and the 2.5kΩ input impedance or Cb/2 together with RT. With Cb = 0.22µF and RT = 50Ω, the low-frequency cutoff is 29kHz. LOP OUTPUT LEVEL MAX3676 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier Cb 0.22µF CIN 5.6nF MAX3676 ADI+ RT 50Ω LOL 2.5k ADI- Cb 0.22µF NO DATA ACQUIRE LOCKED TIME Figure 4. Loss-of-Lock Output 10 Figure 5. Single-Ended Input Termination ______________________________________________________________________________________ 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier The limiting amplifier is biased independently from the clock recovery circuitry. Grounding INSEL turns off the limiting amplifier and selects the PECL DDI inputs. Converting Average Optical Power to Signal Amplitude Many of the MAX3676’s specifications relate to inputsignal amplitude. When working with fiber optic receivers, the input is usually expressed in terms of average optical power and extinction ratio. The relations given in Table 2 and Figure 6 are helpful for converting optical power to input signal when designing with the MAX3676. In an optical receiver, the input voltage to the limiting amplifier can be found by multiplying the relationship in Table 2 by the photodiode responsivity and transimpedance amplifier gain. In an optical receiver, the decibel change at the MAX3676 always equals 2x the optical decibel change. The MAX3676’s typical voltage hysteresis is 3.0dB. This provides an optical hysteresis of 1.5dB. Jitter in Optical Receivers Timing jitter, edge speeds, aberrations, optical dispersion, and attenuation all impact the performance of high-speed clock recovery for SDH/SONET receivers (Figure 7). These effects decrease the time available for error-free data recovery by reducing the received “eye opening” of nonreturn-to-zero (NRZ) transmitted signals. P1 Optical Hysteresis Power and hysteresis are often expressed in decibels. By definition, decibels are always 10log (power). At the inputs to the MAX3676 limiting amplifier, the power is VIN2/R. If a receiver’s optical input power (x) increases by a factor of two, and the preamplifier is linear, then the voltage at the input to the MAX3676 also increases by a factor of two. The optical power increase is: 10log(2x / x) = 10log(2) = +3dB (2VIN )2 / R 2 P0 TIME Figure 6. Optical Power Relations At the MAX3676, the voltage increase is: 10 log PAVE = 10 log(22 ) = 20 log(2) = + 6dB AMPLITUDE VIN / R Table 2. Optical-Power Relations* SYMBOL RELATION ( ) Average Power PAVG Extinction Ratio re re = P1 / P0 Optical Power of a “1” P1 P1 = 2PAVG Optical Power of a “0” P0 P0 = 2PAVG / re + 1 Signal Amplitude PIN PIN = P1 − P0 = 2PAVG PAVG = P0 + P1 / 2 EYE DIAGRAM WITH NO TIMING JITTER re re + 1 ( ) *Assuming a 50% average input-data duty cycle MIDPOINT AMPLITUDE PARAMETER (re − 1) TIME MIDPOINT EFFECTS OF TIMING JITTER ON EYE DIAGRAM TIME re + 1 Figure 7. Eye Diagram With and Without Timing Jitter ______________________________________________________________________________________ 11 MAX3676 Reduced Power Consumption Without the Limiting Amplifier Optical receivers, incorporating transimpedance preamplifiers and limiting postamplifiers, can significantly clean up the effects of dispersion and attenuation. In addition, these amplifiers can provide fast transitions with minimal aberrations to the subsequent CDR blocks. However, these stages also add distortions to the midpoint crossing, contributing to timing jitter. Timing jitter is one of the most critical technical issues to consider when developing optical receivers and CDR circuits. A better understanding of the different sources of jitter helps in the design and application of optical receiver modules and integrated CDR solutions. SDH/SONET specifications are well defined regarding the amount of jitter tolerance allowed at the inputs of optical receivers, as well as jitter peaking requirements, but they do little to define the different sources of jitter. The jitter that must be tolerated at an optical receiver input involves three significant sources, all of which are present in varying degrees in typical receiver systems: of the transitions, the lower the effect of noise on random jitter. The following equation is a simple worstcase estimation of random jitter: RJ (rms) = (rms noise) / (slew rate) Pattern-Dependent Jitter PDJ results from wide variations in the number of consecutive bits contained in NRZ data streams working against the bandwidth requirements of the receiver (Figure 9). The location of the lower -3dB cutoff frequency is important, and must be set to pass the low frequencies associated with long consecutive bit streams. AC-coupling is common in optical receiver design. When using a preamplifier with a highpass frequency response, select the input AC-coupling capacitor, CIN, to provide a low-frequency cutoff (fC) one decade lower than the preamplifier low-frequency cutoff. As a result, the PDJ is dominated by the low-frequency cutoff of the preamplifier. When using a preamplifier without a highpass response with the MAX3676, the following equation provides a good starting point for choosing CIN: 1) Random jitter (RJ) 2) Pattern-dependent jitter (PDJ) 3) Pulse-width distortion (PWD) Random Jitter RJ is caused by random noise present during edge transitions (Figure 8). This random noise results in random midpoint crossings. All electrical systems generate some random noise; however, the faster the speed CIN ≥ -tL PDJ BW 1.25kΩ In 1− 0.5 ( ) ( )( ) where tL = duration of the longest run of consecutive bits of the same value (seconds); PDJ = maximum DESIRED MIDPOINT CROSSING LF DROOP 0-1-0 BIT STREAM MIDPOINT 0–1 TRANSITION WITH RANDOM NOISE RANDOM JITTER MIDPOINT LONG CONSECUTIVE BIT STREAM AMPLITUDE ACTUAL MIDPOINT CROSSING MIDPOINT AMPLITUDE MAX3676 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier LF PDJ TIME TIME Figure 8. Random Jitter on Edge Transition 12 Figure 9. Pattern-Dependent Jitter Due to Low-Frequency Cutoff ______________________________________________________________________________________ 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier Pulse-Width Distortion same level (Figure 11). DC offsets and nonsymmetrical rising and falling edge speeds both contribute to PWD. For a 1–0 bit stream, calculate PWD as follows: PWD = [(width of wider pulse) (width of narrower pulse)] / 2 Phase Adjust The internal clock and data alignment in the MAX3676 is well maintained close to the center of the data eye. Although not required, this sampling point can be shifted using the PHADJ inputs to optimize BER performance. The PHADJ inputs operate with differential input signals to approximately ±1V. A simple resistor divider with a bypass capacitor is sufficient to set up these levels. When the PHADJ inputs are not used, they should be tied directly to VCC. Finally, PWD occurs when the midpoint crossing of a 0–1 transition and a 1–0 transition does not occur at the AMPLITUDE 0-1-0 BIT STREAM MIDPOINT AMPLITUDE LONG CONSECUTIVE BIT STREAM PWD RESULTS WHEN THE WIDTH OF A ZERO DOES NOT EQUAL THE WIDTH OF A ONE. MIDPOINT tFALL ≠ tRISE WIDTH OF A ZERO HF PDJ TIME Figure 10. Pattern-Dependent Jitter Due to High-Frequency Rolloff WIDTH OF A ONE TIME Figure 11. Pulse-Width Distortion ______________________________________________________________________________________ 13 MAX3676 allowable pattern-dependent jitter, peak-to-peak (seconds); and BW = typical system bandwidth, normally 0.6 to 1.0 times the data rate (Hertz). If the PDJ is still larger than desired, continue increasing the value of C IN . Note that to maintain stability when using the MAX3676 analog inputs (ADI+, ADI-), it is important to keep the low-frequency cutoff associated with COLC below the corner frequency associated with CIN (fC) (Table 1). PDJ can also be present due to insufficient high-frequency bandwidth (Figure 10). If the amplifiers are not fast enough to allow for complete transitions during single-bit patterns, or if the amplifier does not allow adequate settling time, high-frequency PDJ can result. __________________Pin Configuration ___________________Chip Topography GND 17 LOL 18 VCC 19 PHADJ- 21 VCC 22 FIL- 23 FIL+ 24 GND 20 PHADJ+ FIL+ TOP VIEW GND 25 16 GND DDI+ 26 15 VCC DDI- 27 14 SDO+ MAX3676 INSEL 28 13 SDO- ADIADI+ VCC 31 10 SCLKO- VCC SCLKOVCC CFILT GND 8 7 LOP 6 5 INV VTH GND 4 3 RSSI 1 2 OLC- TQFP VCC GND VCC SDO+ SDO0.083" VCC (2.108mm) SCLKO+ INSEL 11 SCLKO+ 9 PHADJ+ VCC DDI- 12 VCC CFILT 32 FIL- VCC PHADJ- LOL GND DDI+ 30 ADI- 29 ADI+ OLC+ MAX3676 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier OLC+ RSSI INV LOP OLC- GND VTH GND 0.076" (1.930mm) Chip Information TRANSISTOR COUNT: 2528 14 ______________________________________________________________________________________ 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier 32L/48L,TQFP.EPS ______________________________________________________________________________________ 15 MAX3676 ________________________________________________________Package Information MAX3676 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.