19-1467; Rev 1; 12/99 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery Features ♦ Single +3.3V Supply ♦ 910mW Operating Power ♦ Fully Integrated Clock Recovery and Data Retiming ♦ Exceeds ANSI, ITU, and Bellcore Specifications ♦ Additional High-Speed Input Facilitates System Loopback Diagnostic Testing ♦ 2.488Gbps Serial to 155Mbps Parallel Conversion ♦ LVDS Data Outputs and Synchronization Inputs ♦ Tolerates >2000 Consecutive Identical Digits ♦ Loss-of-Lock Indicator Ordering Information PART MAX3880ECB Applications TEMP. RANGE -40°C to +85°C PIN-PACKAGE 64 TQFP-EP* *Exposed pad 2.488Gbps SDH/SONET Transmission Systems Add/Drop Multiplexers Pin Configuration appears at end of data sheet. Digital Cross-Connects Typical Application Circuit +3.3V 0.01µF PHADJ+ VCC PHADJ- 100Ω* PD15- VCC OUT+ FIL IN+ VCC PD15+ +3.3V SDI+ PD0+ MAX3866 100Ω* MAX3880 PRE/POSTAMPLIFIER OUTLOP OVERHEAD TERMINATION PD0- SDI- PCLK+ 100Ω* SLBIPCLK- SLBI+ TTL SYNC+ SIS FIL+ FIL- GND LOL SYNC- SYSTEM LOOPBACK CF 1µF TTL TTL *REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω. ________________________________________________________________ Maxim Integrated Products 1 For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3880 General Description The MAX3880 deserializer with clock recovery is ideal for converting 2.488Gbps serial data to 16-bit-wide, 155Mbps parallel data for SDH/SONET applications. Operating from a single +3.3V supply, this device accepts high-speed serial-data inputs and delivers lowvoltage differential-signal (LVDS) parallel clock and data outputs for interfacing with digital circuitry. The MAX3880 includes a low-power clock recovery and data retiming function for 2.488Gbps applications. The fully integrated phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input; the signal is then retimed by the recovered clock. The MAX3880’s jitter performance exceeds all SDH/SONET specifications. An additional 2.488Gbps serial input is available for system loopback diagnostic testing. The device also includes a TTL-compatible loss-of-lock (LOL) monitor and LVDS synchronization inputs that enable data realignment and reframing. The MAX3880 is available in the extended temperature range (-40°C to +85°C) in a 64-pin TQFP-EP (exposed pad) package. MAX3880 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery ABSOLUTE MAXIMUM RATINGS Positive Supply Voltage (VCC)...............................-0.5V to +7.0V Input Voltage Level (SDI+, SDI-, SLBI+, SLBI-, SYNC+, SYNC-)........................... (VCC - 0.5V) to (VCC + 0.5V) Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................±10mA Voltage at LOL, SIS, PHADJ+, PHADJ-, FIL+, FIL- .................................................-0.5V to (VCC + 0.5V) Output Current LVDS Outputs ............................................10mA Continuous Power Dissipation (TA = +85°C) TQFP (derate 33.3mW/°C above +85°C) .......................1.44W Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, differential loads = 100Ω ±1%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER Supply Current SYMBOL CONDITIONS MIN ICC TYP MAX UNITS 275 380 mA 800 mVp-p SERIAL DATA INPUTS (SDI±, SLBI±) Differential Input Voltage VID Single-Ended Input Voltage VIS Input Termination to Vcc RIN Figure 1 50 VCC - 0.4 VCC + 0.2 V Ω 50 LVDS INPUTS AND OUTPUTS (SYNC±, PCLK±, PD_±) Input Voltage Range VI Differential Input Threshold VIDTH Threshold Hysteresis VHYST Differential Input Resistance RIN Output High Voltage VOH Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Single-Ended Output Resistance Change in Magnitude of SingleEnded Output Resistance for Complementary Outputs Differential input voltage = 100mV Common-mode voltage = 50mV 2.4 V 100 mV 78 85 VOL |VOD| 0 -100 Ω 1.475 V 400 mV ±25 mV 1.275 V ±25 mV 95 140 Ω ±2.5 ±10 % 0.925 Figure 2 V 250 ∆|VOD| VOS 1.125 ∆VOS RO mV 115 100 40 ∆RO TTL INPUTS AND OUTPUTS (SIS, LOL) Input High Voltage VIH Input Low Voltage VIL Input Current Output High Voltage VOH Output Low Voltage VOL 2 2.0 V 0.8 V -10 +10 µA 2.4 VCC V 0.4 V _______________________________________________________________________________________ +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery (VCC = +3.0V to +3.6V, differential loads = 100Ω ±1%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL Serial Data Rate CONDITIONS MIN SDI Parallel Output Data Rate Parallel Clock-to-Data Output Delay tCLK-Q Jitter Tolerance TYP Gbps Mbps 200 450 f = 70kHz (Note 2) 2.31 3.3 f = 100kHz 1.74 2.41 f = 1MHz 0.38 0.57 f = 10MHz 0.28 0.46 900 >2,000 Input Return Loss (SDI±, SLBI±) UNITS 155.52 Figure 5 Tolerated Consecutive Identical Digits MAX 2.488 100kHz to 2.5GHz -18 2.5GHz to 4.0GHz -11 ps UIp-p Bits dB Note 1: AC characteristics are guaranteed by design and characterization. Note 2: At jitter frequencies <70kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. The low-frequency jitter tolerance outperforms the instrument’s measurement capability. SDI+ 25mV MIN 400mV MAX SDI- (SDI+) - (SDI-) VID 50mVp-p MIN 800mVp-p MAX Figure 1. Input Amplitude PD+ RL = 100Ω D V VOD PDVPD- VOH |VOD| SINGLE-ENDED OUTPUT VPD+ VOS VOL +VOD VPD+ - VPDDIFFERENTIAL OUTPUT 0V (DIFF) 0V VOD, p-p = VPD+ - VPD-VOD Figure 2. Driver Output Levels _______________________________________________________________________________________ 3 MAX3880 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) RECOVERED DATA AND CLOCK (DIFFERENTIAL OUTPUT) SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (mA) CLOCK INPUT JITTER (UIPp-p) 290 223 - 1 PATTERN JITTER TOLERANCE 10 MAX3880-02 DATA 300 VCC = 3.6V 280 270 VCC = 3.0V 260 MAX3880-03 MAX3880-01 1 250 240 50 75 100 BIT ERROR RATE 0.4 JITTER FREQUENCY = 5MHz 0.3 PARALLEL CLOCK TO DATA OUTPUT PROPAGATION DELAY vs. TEMPERATURE 10-6 10-7 10-9 SONET SPEC 10-10 0 10 100 INPUT VOLTAGE (mVp-p) 1,000 10,000 BIT ERROR RATE vs. INPUT VOLTAGE 10-8 0.2 1,000 100 JITTER FREQUENCY (kHz) 10-5 0.5 10 TEMPERATURE (°C) 6.0 6.5 7.0 7.5 8.0 8.5 9.0 INPUT VOLTAGE (mVp-p) 9.5 10.0 700 MAX3880-06 10-4 0.6 0.1 4 25 MAX3880-05 0.7 0 10-3 MAX3880-04 JITTER FREQUENCY = 1MHz -25 PCLK TO DATA OUTPUT PROPAGATION DELAY (ps) JITTER TOLERANCE vs. INPUT VOLTAGE 0.8 0.1 -50 1.64ns/div JITTER TOLERANCE (UIp-p) MAX3880 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery 600 500 400 300 200 -50 -25 0 25 50 TEMPERATURE (°C) _______________________________________________________________________________________ 75 100 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery PIN NAME FUNCTION 1, 17, 25, 33, 41, 49, 56, 62, 64 GND Ground 2 FIL+ Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. 3 FIL- Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. 4, 7, 10, 13, 24, 32, 40, 48, 57 VCC +3.3V Supply Voltage 5 PHADJ+ Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. 6 PHADJ- Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. 8 SDI+ Positive Serial Data Input. 2.488Gbps data stream. 9 SDI- Negative Serial Data Input. 2.488Gbps data stream. 11 SLBI+ Positive System Loopback Input. 2.488Gbps data stream. 12 SLBI- Negative System Loopback Input. 2.488Gbps data stream. 14 SIS 15 SYNC- Negative Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data bit periods (1.6ns) to shift the data alignment by dropping 1 bit. 16 SYNC+ Positive Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data bit periods (1.6ns) to shift the data alignment by dropping 1 bit. 18 PCLK- Negative Parallel Clock LVDS Output 19 PCLK+ Positive Parallel Clock LVDS Output 20, 22, 26, 28, 30, 34, 36, 38, 42, 44, 46, 50, 52, 54, 58, 60 PD0- to PD15- Negative Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK signal (Figure 5). 21, 23, 27, 29, 31, 35, 37, 39, 43, 45, 47, 51, 53, 55, 59, 61 PD0+ to PD15+ Positive Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK signal (Figure 5). 63 LOL EP Exposed Pad Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input (SLBI). Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩ pull-up resistor). The LOL monitor is valid only when a data stream is present on the inputs to the MAX3880. Ground. This must be soldered to a circuit board for proper thermal performance (see Package Information). _______________________________________________________________________________________ 5 MAX3880 Pin Description MAX3880 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery PHADJ+ PHADJ- FIL+ FIL- VCC 50Ω PD15+ Q D SDI+ LVDS CK PD15- AMP SDI- MUX SLBI+ PHASE & FREQUENCY DETECTOR LOOP FILTER VCO 16-BIT DEMULTIPLEXER PD1+ AMP LVDS SLBI- PD1- 50Ω PD0+ LVDS PD0VCC SIS MAX3880 SYNC- CLOCK DIVIDER 100Ω PCLK+ LVDS PCLK- LVDS SYNC+ TTL LOL Figure 3. MAX3880 Functional Diagram Detailed Description The MAX3880 deserializer with clock recovery converts 2.488Gbps serial data to 16-bit-wide, 155Mbps parallel data. The device combines a fully integrated phaselocked loop (PLL), input amplifier, data retiming block, 16-bit demultiplexer, clock divider, and LVDS output buffer (Figure 3). The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). The MAX3880 is designed to deliver the best combination of jitter performance and power 6 dissipation by using a fully differential signal architecture and low-noise design techniques. The PLL recovers the serial clock from the serial input data stream. The demultiplexer generates a 16-bit-wide 155Mbps parallel data output. The synchronization inputs (SYNC+, SYNC-) realign the output data word. Realignment is guaranteed to occur within two complete PCLK cycles of the SYNC signal’s positive transition. During synchronization, the first incoming bit of data during that PCLK cycle is _______________________________________________________________________________________ +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery Input Amplifier The input amplifiers on both the main data and system loopback accept a differential input amplitude from 50mVp-p to 800mVp-p. The bit error rate (BER) is better than 1 x 10-10 for input signals as small as 9.5mVpp, although the jitter tolerance performance will be degraded. For interfacing with PECL signal levels, see Applications Information. Phase Detector The phase detector in the MAX3880 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. The external phase adjust pins (PHADJ+, PHADJ-) allow the user to vary the internal phase alignment. Frequency Detector The digital frequency detector (FD) aids frequency acquisition during start-up conditions. The frequency difference between the received data and the VCO D15 D14 clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is completely eliminated by this digital frequency detector. Loop Filter and VCO The phase detector and frequency detector outputs are summed into the loop filter. A 1.0µF capacitor, CF, is required to set the PLL damping ratio. The loop filter output controls the on-chip LC VCO running at 2.488GHz. The VCO provides low phase noise and is trimmed to the correct frequency. Loss-of-Lock Monitor A loss-of-lock (LOL) monitor is included in the MAX3880 frequency detector. A loss-of-lock condition is signaled immediately with a TTL low. When the PLL is frequency-locked, LOL switches to TTL high in approximately 800ns. Note that the LOL monitor is only valid when a data stream is present on the inputs to the MAX3880. As a result, LOL does not detect a loss-of-power condition resulting from a loss of the incoming signal. D13 SDI SYNC PCLK (LSB) PD0 D0 D16 D32 D48 D65 PD1 D1 D17 D33 D49 D66 • • • (MSB) PD15 TRANSMITTED FIRST 1 BIT HAS SLIPPED IN THIS TIME SLICE D15 D31 D47 D64 D80 Figure 4. Timing Diagram _______________________________________________________________________________________ 7 MAX3880 dropped, shifting the alignment between PCLK and data by 1 bit. The SYNC signal must be at least four serial bit periods wide (4 x 402ps). See Figure 4 for the timing diagram and Figure 5 for the timing parameters diagram. MAX3880 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery PCLK tCLK-Q 3.3V PD0–PD15 MAX3880 PHADJ+ (PIN 5) NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLK = (PCLK+) - (PCLK-). PHADJ- (PIN 6) Figure 5. Timing Parameters Low-Voltage Differential-Signal (LVDS) Inputs and Outputs The MAX3880 features LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 500mVp-p to 800mVp-p differential low-voltage swings to achieve fast transition times, minimize power dissipation, and improve noise immunity. For proper operation, the parallel clock and data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-) require 100Ω differential DC termination between the positive and negative outputs. Do not terminate these outputs to ground. The synchronization LVDS inputs (SYNC+, SYNC-) are internally terminated with 100Ω differential input resistance and therefore do not require external termination. Design Procedure Jitter Tolerance and Input Sensitivity Trade-Offs When the received data amplitude is higher than 50mVp-p, the MAX3880 provides a typical jitter tolerance of 0.46 UI at jitter frequencies greater than 10MHz. The SDH/SONET jitter tolerance specification is 0.15UI, leaving a jitter allowance of 0.31UI for receiver preamplifier and postamplifier design. The BER is better than 1 x 10 -10 for input signals greater than 9.5mVp-p. At 25mVp-p, jitter tolerance will be degraded, but will still be above the SDH/SONET requirement. Trade-offs can be made between jitter tolerance and input sensitivity according to the specific application. See the Typical Operating Characteristics for Jitter Tolerance and BER vs. Input Voltage graphs. 8 Figure 6. Phase-Adjust Resistor-Divider Applications Information Consecutive Identical Digits (CIDs) The MAX3880 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER of 1 x 10-10. The CID tolerance is tested using a 2 13 - 1 pseudorandom bit stream (PRBS), substituting a long run of zeros to simulate the worst case. A CID tolerance of greater than 2,000 bits is typical. Phase Adjust The internal clock is aligned to the center of the data eye. For specific applications, this sampling position can be shifted using the PHADJ inputs to optimize BER performance. The PHADJ inputs operate with differential input voltages up to ±1.5V. A simple resistor-divider with a bypass capacitor is sufficient to set these levels (Figure 6). When the PHADJ inputs are not used, they should be tied directly to VCC. System Loopback The MAX3880 is designed to allow system loopback testing. The user can connect a serializer output (MAX3890) in a transceiver directly to the SLBI+ and SLBI- inputs of the MAX3880 for system diagnostics. To select the SLBI± inputs, apply a TTL logic high to the SIS pin. _______________________________________________________________________________________ +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3880 Interfacing with PECL Input Levels When interfacing with differential PECL input levels, it is important to attenuate the signal while still maintaining 50Ω termination (Figure 7). AC-coupling is also required to maintain the input common-mode level. VCC Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled impedance transmission lines to interface with the MAX3880 high-speed inputs and outputs. Power-supply decoupling should be placed as close to VCC as possible. To reduce feedthrough, take care to isolate the input signals from the output signals. Chip Information 50Ω 0.1µF 25Ω PECL LEVELS 50Ω SDI+ 100Ω 0.1µF 25Ω SDI- MAX3880 TRANSISTOR COUNT: 4102 Figure 7. Interfacing with PECL Input Levels _______________________________________________________________________________________ 9 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery GND PD11- PD11+ PD12- PD12+ PD13- PD13+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCC GND PD14- PD14+ PD15- PD15+ GND LOL TOP VIEW GND MAX3880 Pin Configuration GND 1 48 VCC FIL+ 2 47 PD10+ FIL- 3 46 PD10- VCC 4 45 PD9+ PHADJ+ 5 44 PD9- PHADJ- 6 43 PD8+ VCC 7 42 PD8- SDI+ 8 41 GND SDI- 9 40 VCC VCC 10 39 PD7+ SLBI+ 11 38 PD7- SLBI- 12 37 PD6+ VCC 13 36 PD6- MAX3880 SIS 14 35 PD5+ SYNC- 15 34 PD5- SYNC+ 16 33 GND VCC PD4+ PD4- PD3+ PD3- PD2+ PD2- GND VCC PD1+ PD1- PD0+ PD0- PCLK+ GND PCLK- 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TQFP-EP 10 ______________________________________________________________________________________ +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery 64L, TQFP.EPS ______________________________________________________________________________________ 11 MAX3880 Package Information +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery MAX3880 Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.