MOTOROLA MC145053D

Order this document
by MC145053/D
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC
CASE 646
CMOS
This ratiometric 10-bit ADC has a serial interface port to provide communication with MCUs and MPUs. Either a 10- or 16-bit format can be used. The
16-bit format can be one continuous 16-bit stream or two intermittent 8-bit
streams. The converter operates from a single power supply with no external
trimming required. Reference voltages down to 4.0 V are accommodated.
The MC145053 has an internal clock oscillator to operate the dynamic A/D
conversion sequence and an end-of-conversion (EOC) output.
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ORDERING INFORMATION
5 Analog Input Channels with Internal Sample-and-Hold
Operating Temperature Range: – 40 to 125° C
Successive Approximation Conversion Time: 44 µs Maximum
Maximum Sample Rate: 20.4 ks/s
Analog Input Range with 5-Volt Supply: 0 to 5 V
Monotonic with No Missing Codes
Direct Interface to Motorola SPI and National MICROWIRE Serial Data
Ports
Digital Inputs/Outputs are TTL, NMOS, and CMOS Compatible
Low Power Consumption: 14 mW
Chip Complexity: 1630 Elements (FETs, Capacitors, etc.)
See Application Note AN1062 for Operation with QSPI
MC145053P
MC145053D
MUX OUT
INTERNAL
TEST
VOLTAGES
AN0 2
AN1 3
ANALOG
4
AN2
MUX
5
AN3
AN4 6
AN5
AN6
AN7
12
Din
11
Dout
CS
SCLK
EOC
EOC
1
14
VDD
AN0
2
13
SCLK
AN1
3
12
Din
AN2
4
11
Dout
AN3
5
10
CS
AN4
6
9
Vref
VSS
7
8
VAG
VAG
9
8
10-BIT RC DAC
WITH SAMPLE AND HOLD
SUCCESSIVE APPROXIMATION
REGISTER
MUX ADDRESS
REGISTER
PIN 14 = VDD
PIN 7 = VSS
DATA REGISTER
AUTO-ZEROED
COMPARATOR
10
13
Plastic DIP
SOG Package
PIN ASSIGNMENT
BLOCK DIAGRAM
Vref
D SUFFIX
SOG
CASE 751A
DIGITAL CONTROL
LOGIC
1
MICROWIRE is a trademark of National Semiconductor Corp.
REV 2
1/99
WIRELESS SEMICONDUCTOR
MOTOROLA
Motorola, Inc. 1998
SOLUTIONS DEVICE DATA
MC145053
1
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage (Referenced to VSS)
– 0.5 to + 6.0
V
Vref
DC Reference Voltage
VAG to VDD + 0.1
V
VAG
Analog Ground
VSS – 0.1 to Vref
V
Vin
DC Input Voltage, Any Analog or Digital
Input
VSS – 0.5 to
VDD + 0.5
V
Vout
DC Output Voltage
VSS – 0.5 to
VDD + 0.5
V
DC Input Current, per Pin
± 20
mA
DC Output Current, per Pin
± 25
mA
DC Supply Current, VDD and VSS Pins
± 50
mA
– 65 to 150
°C
260
°C
Iin
Iout
IDD, ISS
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for
10 Seconds
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications
of any voltage higher than maximum rated
voltages to this high-impedance circuit. For
proper operation, Vin and Vout should be
constrained to the range VSS ≤ (Vin or Vout) ≤
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSS or VDD). Unused outputs must be left
open.
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Operation Ranges below..
OPERATION RANGES (Applicable to Guaranteed Limits)
Parameter
Symbol
Value
Unit
VDD
DC Supply Voltage, Referenced to VSS
4.5 to 5.5
V
Vref
DC Reference Voltage
VAG + 4.0 to VDD + 0.1
V
VAG
Analog Ground
VSS – 0.1 to Vref – 4.0
V
VAI
Analog Input Voltage (See Note)
VAG to Vref
V
Digital Input Voltage, Output Voltage
VSS to VDD
V
Ambient Operating Temperature
– 40 to 125
°C
Vin, Vout
TA
NOTE: Analog input voltages greater than Vref convert to full scale. Input voltages less than VAG convert to zero. See Vref and VAG pin
descriptions.
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, Full Temperature and Voltage Ranges per Operation Ranges Table, unless otherwise indicated)
Parameter
Symbol
Guaranteed
Limit
Unit
VIH
Minimum High-Level Input Voltage
(Din, SCLK, CS)
2.0
V
VIL
Maximum Low-Level Input Voltage
(Din, SCLK, CS)
0.8
V
VOH
Minimum High-Level Output Voltage
(Dout, EOC)
Iout = – 1.6 mA
Iout = – 20 µA
2.4
VDD – 0.1
V
VOL
Minimum Low-Level Output Voltage
(Dout, EOC)
Iout = + 1.6 mA
Iout = + 20 µA
0.4
0.1
V
Maximum Input Leakage Current
(Din, SCLK, CS)
Vin = VSS or VDD
± 2.5
µA
Iin
IOZ
Maximum Three-State Leakage Current (Dout)
Vout = VSS or VDD
± 10
µA
IDD
Maximum Power Supply Current
Vin = VSS or VDD, All Outputs Open
2.5
mA
Iref
Maximum Static Analog Reference Current (Vref)
Vref = VDD, VAG = VSS
100
µA
IAl
Maximum Analog Mux Input Leakage Current between all
deselected inputs and any selected input (AN0 – AN4)
VAl = VSS to VDD
±1
µA
MC145053
2
Test Condition
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
A/D CONVERTER ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Definition and Test Conditions
Characteristic
Guaranteed
Limit
Unit
Resolution
Number of bits resolved by the A/D converter
10
Bits
Maximum Nonlinearity
Maximum difference between an ideal and an actual ADC transfer function
±1
LSB
Maximum Zero Error
Difference between the maximum input voltage of an ideal and an actual
ADC for zero output code
±1
LSB
Maximum Full-Scale Error
Difference between the minimum input voltage of an ideal and an actual
ADC for full-scale output code
±1
LSB
Maximum Total Unadjusted Error
Maximum sum of nonlinearity, zero error, and full-scale error
±1
LSB
Maximum Quantization Error
Uncertainty due to converter resolution
± 1/2
LSB
Absolute Accuracy
Difference between the actual input voltage and the full-scale weighted
equivalent of the binary output code, all error sources included
± 1-1/2
LSB
Maximum Conversion Time
Total time to perform a single analog-to-digital conversion
44
µs
Data Transfer Time
Total time to transfer digital serial data into and out of the device
10 to 16
SCLK
cycles
Sample Acquisition Time
Analog input acquisition time window
6
SCLK
cycles
Minimum Total Cycle Time
Total time to transfer serial data, sample the analog input, and perform the
conversion; SCLK = 2.1 MHz
49
µs
Maximum Sample Rate
Rate at which analog inputs may be sampled; SCLK = 2.1 MHz
20.4
ks/s
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
MC145053
3
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Figure
Symbol
1
f
Guaranteed
Limit
Parameter
Clock Frequency, SCLK
Note: Refer to twH, twL below
(10-bit xfer) Min
(11- to 16-bit xfer) Min
(10- to 16-bit xfer) Max)
Unit
0
Note 1
2.1
MHz
1
twH
Minimum Clock High Time, SCLK
190
ns
1
twL
Minimum Clock Low Time, SCLK
190
ns
1, 7
tPLH, tPHL
Maximum Propagation Delay, SCLK to Dout
125
ns
1, 7
th
Minimum Hold Time, SCLK to Dout
10
ns
2, 7
tPLZ, tPHZ
Maximum Propagation Delay, CS to Dout High-Z
150
ns
2, 7
tPZL, tPZH
Maximum Propagation Delay, CS to Dout Driven
2.3
µs
3
tsu
Minimum Setup Time, Din to SCLK
100
ns
3
th
Minimum Hold Time, SCLK to Din
0
ns
4, 7, 8
td
Maximum Delay Time, EOC to Dout (MSB)
100
ns
5
tsu
Minimum Setup Time, CS to SCLK
2.425
µs
—
tCSd
Minimum Time Required Between 10th SCLK Falling Edge (≤ 0.8 V) and
CS to Allow a Conversion
Note 2
—
tCAs
Maximum Delay Between 10th SCLK Falling Edge (≤ 2 V) and CS to
Abort a Conversion
5
th
6, 8
tPHL
Maximum Propagation Delay, 10th SCLK to EOC
1
tr, tf
Maximum Input Rise and Fall Times
1, 4, 6 – 8
tTLH, tTHL
—
Cin
—
Cout
9
Minimum Hold Time, Last SCLK to CS
SCLK
Din, CS
Maximum Output Transition Time, Any Output
Maximum Input Capacitance
Maximum Three-State Output Capacitance
µs
0
ns
2.35
µs
1
10
ms
µs
300
ns
AN0 – AN4
SCLK, CS, Din
55
15
pF
Dout
15
pF
NOTES:
1. After the 10th SCLK falling edge (≤ 2 V), at least 1 SCLK rising edge (≥ 2 V) must occur within 18.5 µs.
2. A CS edge may be received immediately after an active transition on the EOC pin.
MC145053
4
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
SWITCHING WAVEFORMS
twL
twH
tr
tf
2.0 V
SCLK
0.8 V
2.0 V
CS
1/f
0.8 V
tPLH, tPHL
tPZH, tPZL
th
tPHZ, tPLZ
2.4 V
Dout
0.4 V
2.4 V
0.4 V
Dout
tTLH, tTHL
90%
Figure 1.
10%
Figure 2.
tTLH
EOC
VALID
2.4 V
0.4 V
2.0 V
0.8 V
Din
td
2.4 V
th
tsu
0.4 V
Dout
VALID MSB
2.0 V
SCLK
0.8 V
NOTE: Dout is driven only when CS is active (low).
Figure 3.
Figure 4.
2.0 V
CS
0.8 V
tsu
SCLK
SCLK
0.8 V
10TH
CLOCK
0.8 V
tPHL
th
FIRST
CLOCK
2.4 V
EOC
LAST
CLOCK
0.4 V
0.8 V
tTHL
Figure 5.
Figure 6.
VDD
TEST
POINT
VDD
TEST
POINT
2.18 k
Dout
DEVICE
UNDER
TEST
2.18 k
EOC
12 k
100 pF
Figure 7. Test Circuit
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
DEVICE
UNDER
TEST
12 k
50 pF
Figure 8. Test Circuit
MC145053
5
Dout
Serial Data Output of the A/D Conversion Result
(Pin 11)
PIN DESCRIPTIONS
DIGITAL INPUTS AND OUTPUT
The various serial bit-stream formats for the MC145053
are illustrated in the timing diagrams of Figures 9 through 14.
Table 1 assists in selection of the appropriate diagram. Note
that the ADC accepts 16 clocks which makes it SPI (Serial
Peripheral Interface) compatible.
Table 1. Timing Diagram Selection
No. of Clocks in
Serial Transfer
Using
CS
10
10
11 to 16
16
11 to 16
16
Yes
No
Yes
No
Yes
No
Serial Transfer
Interval
Figure
No.
Don’t Care
Don’t Care
Shorter than Conversion
Shorter than Conversion
Longer than Conversion
Longer than Conversion
9
10
11
12
13
14
CS
Active-Low Chip Select Input (Pin 10)
Chip select initializes the chip to perform conversions and
provides 3-state control of the data output pin (Dout). While
inactive high, CS forces Dout to the high-impedance state
and disables the data input (Din) and serial clock (SCLK)
pins. A high-to-low transition on CS resets the serial data
port and synchronizes it to the MPU data stream. CS can remain active during the conversion cycle and can stay in the
active low state for multiple serial transfers or CS can be inactive high after each transfer. If CS is kept active low between transfers, the length of each transfer is limited to either
10 or 16 SCLK cycles. If CS is in the inactive high state between transfers, each transfer can be anywhere from 10 to
16 SCLK cycles long. See the SCLK pin description for a
more detailed discussion of these requirements.
Spurious chip selects caused by system noise are minimized by the internal circuitry. Any transitions on the CS pin
are recognized as valid only if the level is maintained for
about 2 µs after the transition.
NOTE
If CS is inactive high after the 10th SCLK cycle
and then goes active low before the A/D conversion is complete, the conversion is aborted and
the chip enters the initial state, ready for another
serial transfer/conversion sequence. At this point,
the output data register contains the result from
the conversion before the aborted conversion.
Note that the last step of the A/D conversion sequence is to update the output data register with
the result. Therefore, if CS goes active low in an
attempt to abort the conversion too close to the
end of the conversion sequence, the result register may be corrupted and the chip could be thrown
out of sync with the processor until CS is toggled
again (refer to the AC Electrical Characteristics in
the spec tables).
MC145053
6
This output is in the high-impedance state when CS is inactive high. When the chip recognizes a valid active low on
CS, Dout is taken out of the high-impedance state and is driven with the MSB of the previous conversion result. (For the
first transfer after power-up, data on Dout is undefined for the
entire transfer.) The value on Dout changes to the second
most significant result bit upon the first falling edge of SCLK.
The remaining result bits are shifted out in order, with the
LSB appearing on Dout upon the ninth falling edge of SCLK.
Note that the order of the transfer is MSB to LSB. Upon the
10th falling edge of SCLK, Dout is immediately driven low (if
allowed by CS) so that transfers of more than 10 SCLKs read
zeroes as the unused LSBs.
When CS is held active low between transfers, Dout is driven from a low level to the MSB of the conversion result for
three cases: Case 1 — upon the 16th SCLK falling edge if
the transfer is longer than the conversion time (Figure 14);
Case 2 — upon completion of a conversion for a 16-bit transfer interval shorter than the conversion (Figure 12); Case 3
— upon completion of a conversion for a 10-bit transfer (Figure 10).
Din
Serial Data Input (Pin 12)
The four-bit serial input stream begins with the MSB of the
analog mux address (or the user test mode) that is to be converted next. The address is shifted in on the first four rising
edges of SCLK. After the four mux address bits have been
received, the data on Din is ignored for the remainder of the
present serial transfer. See Table 2 in Applications Information.
SCLK
Serial Data Clock (Pin 13)
This clock input drives the internal I/O state machine to
perform three major functions: (1) drives the data shift registers to simultaneously shift in the next mux address from the
Din pin and shift out the previous conversion result on the
Dout pin, (2) begins sampling the analog voltage onto the RC
DAC as soon as the new mux address is available, and (3)
transfers control to the A/D conversion state machine after
the last bit of the previous conversion result has been shifted
out on the Dout pin.
The serial data shift registers are completely static, allowing SCLK rates down to the dc. There are some cases, however, that require a minimum SCLK frequency as discussed
later in this section. At least ten SCLK cycles are required for
each simultaneous data transfer. If the 16-bit format is used,
SCLK can be one continuous 16-bit stream or two intermittent 8-bit streams. After the serial port has been initiated to
perform a serial transfer*, the new mux address is shifted in
* The serial port can be initiated in three ways: (1) a recognized CS
falling edge, (2) the end of an A/D conversion if the port is performing either a 10-bit or a 16-bit “shorter-than-conversion” transfer
with CS active low between transfers, and (3) the 16th falling edge
of SCLK if the port is performing 16-bit “longer-than-conversion”
transfers with CS active low between transfers.
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
on the first four rising edges of SCLK, and the previous 10-bit
conversion result is shifted out on the first nine falling edges
of SCLK. After the fourth rising edge of SCLK, the new mux
address is available; therefore, on the next edge of SCLK
(the fourth falling edge), the analog input voltage on the
selected mux input begins charging the RC DAC and continues to do so until the tenth falling edge of SCLK. After this
tenth SCLK edge, the analog input voltage is disabled from
the RC DAC and the RC DAC begins the “hold” portion of the
A/D conversion sequence. Also upon this tenth SCLK edge,
control of the internal circuitry is transferred to the internal
clock oscillator which drives the successive approximation
logic to complete the conversion. If 16 SCLK cycles are used
during each transfer, then there is a constraint on the minimum SCLK frequency. Specifically, there must be at least
one rising edge on SCLK before the A/D conversion is complete. If the SCLK frequency is too low and a rising edge
does not occur during the conversion, the chip is thrown out
of sync with the processor and CS needs to be toggled in order to restore proper operation. If 10 SCLKs are used per
transfer, then there is no lower frequency limit on SCLK. Also
note that if the ADC is operated such that CS is inactive high
between transfers, then the number of SCLK cycles per
transfer can be anything between 10 and 16 cycles, but the
“rising edge” constraint is still in effect if more than 10 SCLKs
are used. (If CS stays active low for multiple transfers, the
number of SCLK cycles must be either 10 or 16.)
EOC
End-of-Conversion Output (Pin 1)
EOC goes low on the tenth falling edge of SCLK. A low-tohigh transition on EOC occurs when the A/D conversion is
complete and the data is ready for transfer.
and leakage currents through the ESD protection diodes on
the selected channel occur. These leakage currents cause
an offset voltage to appear across any series source resistance on the selected channel. Therefore, any source resistance greater than 1 kΩ (Motorola test condition) may induce
errors in excess of guaranteed specifications.
There are three tests available that verify the functionality
of all the control logic as well as the successive approximation comparator. These tests are performed by addressing
$B, $C, or $D and they convert a voltage of (Vref + VAG)/2,
VAG, or Vref, respectively. The voltages are obtained internally by sampling Vref or VAG onto the appropriate elements of
the RC DAC during the sample phase. Addressing $B, $C, or
$D produces an output of $200 (half scale), $000, or $3FF
(full scale), respectively, if the converter is functioning properly. However, deviation from these values occurs in the
presence of sufficient system noise (external to the chip) on
VDD, VSS, Vref, or VAG.
POWER AND REFERENCE PINS
VSS and VDD
Device Supply Pins (Pins 7 and 14)
VSS is normally connected to digital ground; VDD is connected to a positive digital supply voltage. Low frequency
(VDD – VSS) variations over the range of 4.5 to 5.5 volts do
not affect the A/D accuracy. (See the Operations Ranges
Table for restrictions on Vref and VAG relative to VDD and
VSS.) Excessive inductance in the VDD or VSS lines, as on
automatic test equipment, may cause A/D offsets > ± 1 LSB.
Use of a 0.1 µF bypass capacitor across these pins is recommended.
ANALOG INPUTS AND TEST MODES
VAG and Vref
Analog Reference Voltage Pins (Pins 8 and 9)
AN0 through AN4
Analog Multiplexer Inputs (Pins 2 – 6)
Analog reference voltage pins which determine the lower
and upper boundary of the A/D conversion. Analog input voltages ≥ Vref produce a full scale output and input voltages
≤ VAG produce an output of zero. CAUTION: The analog
input voltage must be ≥ V SS and ≤ V DD. The A/D conversion
result is ratiometric to Vref – VAG. Vref and VAG must be as
noise-free as possible to avoid degradation of the A/D
conversion. Ideally, Vref and VAG should be single-point connected to the voltage supply driving the system’s transducers. Use of a 0.22 µF bypass capacitor across these pins is
strongly urged.
The input AN0 is addressed by loading $0 into the mux
address register. AN1 is addressed by $1, AN2 by $2, AN3
by $3, and AN4 by $4. Table 2 shows the input format for a
16-bit stream. The mux features a break-before-make
switching structure to minimize noise injection into the analog inputs. The source resistance driving these inputs must
be
1 kΩ.
During normal operation, leakage currents through the
analog mux from unselected channels to a selected channel
v
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
MC145053
7
CS
Dout
D9 – MSB
D8
1
SCLK
D7
2
D6
3
4
D5
D4
5
D3
6
D2
7
8
D1
9
HIGH IMPEDANCE
D0
D9
10
1
SAMPLE ANALOG INPUT
Din
A3
A2
A1
A3
A0
MSB
EOC
A/D CONVERSION
INTERVAL
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
INITIALIZE
RE-INITIALIZE
Figure 9. Timing for 10-Clock Transfer Using CS
MUST BE HIGH ON POWER UP
CS
Dout
D9 – MSB
SCLK
1
D8
D7
2
D6
3
4
D5
5
D4
D3
6
D2
7
8
D1
9
D0
LOW LEVEL
D9
10
1
SAMPLE ANALOG INPUT
Din
A3
A2
A1
A0
A3
MSB
EOC
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A/D CONVERSION
INTERVAL
INITIALIZE
Figure 10. Timing for 10-Clock Transfer Not Using CS
NOTES:
1. D9, D8, D7, D6, D5, …, D0 = the result of the previous A/D conversion.
2. A3, A2, A1, A0 = the mux address for the next A/D conversion.
MC145053
8
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
MC145053
9
A1
3
A0
D6
4
D5
5
6
D3
7
D2
8
SAMPLE ANALOG INPUT
D4
D1
9
10
D0
16
A/D CONVERSION
INTERVAL
11
HIGH
IMPEDANCE
RE-INITIALIZE
A3
D9
2
A1
D7
3
A0
4
D6
D5
5
6
D3
7
D2
8
SAMPLE ANALOG INPUT
D4
D1
9
D0
10
11
12
14
15
A/D CONVERSION INTERVAL
13
LOW LEVEL
16
Figure 12. Timing for 16-Clock Transfer Not Using CS* (Serial Transfer Interval Shorter Than Conversion)
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A2
D8
NOTES:
D9, D8, D7, . . . , D0 = the result of the previous A/D conversion.
A3, A2, A1, A0 = the mux address for the next A/D conversion.
*This figure illustrates the behavior of the MC145051. The MC145050 behaves identically except there is no EOC signal and the conversion time is 44 ADCLK cycles (user-controlled time).
INITIALIZE
EOC
MSB
A3
1
SCLK
D in
D9 – MSB
MUST BE HIGH ON POWER UP
D out
CS
2
D7
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A2
D8
LOW
LEVEL
Figure 11. Timing for 11- to 16-Clock Transfer Using CS* (Serial Transfer Interval Shorter than Conversion)
INITIALIZE
EOC
A3
1
SCLK
D in
D9 – MSB
D out
CS
1
A3
D9
1
10
MC145053
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
A1
3
A0
D6
4
D5
5
6
D3
7
D2
8
SAMPLE ANALOG INPUT
D4
D1
9
10
D0
NOTE
2
HIGH
IMPEDANCE
16
A/D
CONVERSION
INTERVAL
11
LOW
LEVEL
RE-INITIALIZE
A3
D9
A1
3
A0
D6
4
D5
5
6
D3
7
D2
8
SAMPLE ANALOG INPUT
D4
D1
9
10
D0
11
13
A/D CONVERSION
INTERVAL
12
NOTE 2
14
LOW LEVEL
15
16
Figure 14. Timing for 16-Clock Transfer Not Using CS* (Serial Transfer Interval Longer Than Conversion)
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A2
2
D7
1
NOTES:
D9, D8, D7, . . . , D0 = the result of the previous A/D conversion.
A3, A2, A1, A0 = the mux address for the next A/D conversion.
*NOTES:
1. This figure illustrates the behavior of the MC145051. The MC145050 behaves identically except there is no EOC signal and the conversion time is 44 ADCLK cycles (user-controlled time).
2. The 11th SCLK rising edge must occur before the conversion is complete. Otherwise the serial port is thrown out of sync with the microprocessor for the remainder of the transfer.
MSB
A3
1
D8
MUST BE HIGH ON POWER UP
D9 – MSB
INITIALIZE
EOC
D in
SCLK
D out
CS
2
D7
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A2
D8
Figure 13. Timing for 11- to 16-Clock Transfer Using CS* (Serial Transfer Interval Longer Than Conversion)
INITIALIZE
EOC
A3
1
SCLK
D in
D9 – MSB
D out
CS
D9
A3
1
APPLICATIONS INFORMATION
DESCRIPTION
This example application of the MC145053 ADC interfaces
four analog signals to a microprocessor.
Figure 15 illustrates how the MC145053 is used as a costeffective means to simplify this type of circuit design. Utilizing
one ADC, four analog inputs are interfaced to a CMOS or
NMOS microprocessor with a serial peripheral interface
(SPI) port. Processors with National Semiconductor’s
MICROWIRE serial port may also be used. Full duplex
operation optimizes throughput for this system.
DIGITAL DESIGN CONSIDERATIONS
Motorola’s MC68HC05C4 CMOS MCU may be chosen to
reduce power supply size and cost. The NMOS MCUs may
be used if power consumption is not critical. A VDD or VSS
0.1 µF bypass capacitor should be closely mounted to the
ADC.
The MC145053 has the end-of-conversion (EOC) signal at
output pin 1 to define when data is ready.
ANALOG DESIGN CONSIDERATIONS
Analog signal sources with output impedances of less than
1 kΩ may be directly interfaced to the ADC, eliminating the
need for buffer amplifiers. Separate lines connect the Vref
and VAG pins on the ADC with the controllers to provide
isolation from system noise.
Although not indicated in Figure 15, the Vref and sensor
output lines may need to be shielded, depending on their
length and electrical environment. This should be verified
during prototyping with an oscilloscope. If shielding is
required, a twisted pair or foil-shielded wire (not coax) is
appropriate for this low frequency application. One wire of
the pair or the shield must be VAG.
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
A reference circuit voltage of 5 volts is used for the application shown in Figure 15. However, the reference circuitry
may be simplified by tying VAG to system ground and Vref to
the system’s positive supply. (See Figure 16.)
A bypass capacitor of approximately 0.22 µF across the
Vref and VAG pins is recommended. These pins are adjacent
on the ADC package which facilitates mounting the capacitor
very close to the ADC.
SOFTWARE CONSIDERATIONS
The software flow for acquisition is straightforward. The
four analog inputs, AN0 through AN3, are scanned by reading the analog value of the previously addressed channel
into the MCU and sending the address of the next channel to
be read to the ADC, simultaneously.
The designer utilizing the MC145053 has the end-of-conversion signal (at pin 1) to define the conversion interval.
EOC may be used to generate an interrupt, which is serviced
by reading the serial data from the ADC. The software flow
should then process and format the data.
When this ADC is used with a 16-bit (2-byte) transfer, there
are two types of offsets involved. In the first type of offset, the
channel information sent to the ADCs is offset by 12 bits.
That is, in the 16-bit stream, only the first 4 bits (4 MSBs)
contain the channel information. The balance of the bits are
don’t cares. This results in 3 don’t-care nibbles, as shown in
Table 2. The second type of offset is in the conversion result
returned from the ADC; this is offset by 6 bits. In the 16-bit
stream, the first 10 bits (10 MSBs) contain the conversion
result. The last 6 bits are zeroes. The hexadecimal result is
shown in the first column of Table 3. The second column
shows the result after the offset is removed by a microprocessor routine. If the 16-bit format is used, the ADC can
transfer one continuous 16-bit stream or two intermittent 8-bit
streams.
MC145053
11
Table 2. Programmer’s Guide for 16-Bit Transfers:
Input Code
Input
Address
in Hex
Channel to be
Converted Next
Comment
$0XXX
$1XXX
$2XXX
$3XXX
$4XXX
$5XXX
$6XXX
$7XXX
$8XXX
$9XXX
$AXXX
$BXXX
$CXXX
$DXXX
$EXXX
$FXXX
AN0
AN1
AN2
AN3
AN4
None
None
None
None
None
None
AN5
AN6
AN7
None
None
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Half Scale Test: Output = $8000
Zero Test: Output = $0000
Full Scale Test: Output = $FFC0
Not Allowed
Not Allowed
Table 3. Programmer’s Guide for 16-Bit Transfers:
Output Code
Conversion
Result Without
Offset Removed
Conversion
Result With
Offset Removed
$0000
$0040
$0080
$00C0
$0100
$0140
$0180
$01C0
$0200
$0240
$0280
$02C0
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
L
L
$FF40
$FF80
$FFC0
$03FD
$03FE
$03FF
+5V
0.22 µF
Vref
L
Full Scale – 2 LSBs
Full Scale – 1 LSB
Full Scale
0.1 µF
VDD
CS
Din
SCLK
AN0
ANALOG
SENSORS,
ETC.
Value
Zero
Zero + 1 LSB
Zero + 2 LSBs
Zero + 3 LSBs
Zero + 4 LSBs
Zero + 5 LSBs
Zero + 6 LSBs
Zero + 7 LSBs
Zero + 8 LSBs
Zero + 9 LSBs
Zero + 10 LSBs
Zero + 11 LSBs
AN1 MC145053
ADC
AN2
µP
SPI PORT
Dout
AN3
EOC
5 VOLT
REFERENCE
CIRCUIT
AN4
VAG
VSS
Figure 15. Example Application
MC145053
12
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
DIGITAL + V
DO NOT CONNECT
AT IC
ANALOG + V
Vref
TO
SENSORS,
ETC.
5V
SUPPLY
0.22 µF
VDD
VAG
ANALOG GND
0.1 µF
MC145053
VSS
DO NOT CONNECT
AT IC
DIGITAL GND
Figure 16. Alternate Configuration Using the Digital Supply for the Reference Voltage
Compatible Motorola MCUs/MPUs
This is not a complete listing of Motorola’s MCUs/MPUs.
Contact your Motorola representative if you need
additional information.
Instruction
Set
Memory (Bytes)
SPI
SCI
ROM
EEPROM
M6805
2096
2096
4160
4160
8K
4160
8K
7700
—
—
—
—
—
—
—
—
—
4160
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
M68000
—
—
—
Device
Number
MC68HC05C2
MC68HC05C3
MC68HC05C4
MC68HSC05C4
MC68HSC05C8
MC68HCL05C4
MC68HCL05C8
MC68HC05C8
MC68HC805C4
MC68HC000
SPI = Serial Peripheral Interface.
SCI = Serial Communication Interface.
High Speed.
Low Power.
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
MC145053
13
PACKAGE DIMENSIONS
PLASTIC DIP
P SUFFIX
CASE 646-06
14
8
1
7
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION
AT SEATING PLANE AT MAXIMUM MATERIAL
CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN FORMED
PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
4. ROUNDED CORNERS OPTIONAL.
B
A
F
L
C
J
N
H
MC145053
14
G
D
SEATING
PLANE
K
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0°
10°
0.015
0.039
MILLIMETERS
MIN
MAX
18.16 19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0°
10°
1.01
0.39
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
SOG PACKAGE
D SUFFIX
CASE 751A-03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
-A14
8
-B1
P7
PL
0.25 (0.010)
7
G
0.25 (0.010)
M
T B
S
M
F
M
K
D 14 PL
B
R X 45°
C
SEATING
PLANE
M
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.228 0.244
0.010 0.019
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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MOTOROLA WIRELESS SEMICONDUCTOR
◊
SOLUTIONS DEVICE DATA
MC145053
MC145053/D
15