ADC0819 8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer General Description The ADC0819 is an 8-Bit successive approximation A/D converter with simultaneous serial I/O. The serial input controls an analog multiplexer which selects from 19 input channels or an internal half scale test voltage. An input sample-and-hold is implemented by a capacitive reference ladder and sampled data comparator. This allows the input signal to vary during the conversion cycle. Separate serial I/O and conversion clock inputs are provided to facilitate the interface to various microprocessors. Y Features Y Y Y Y Y Y Y Y Y Key Specifications Y Y Separate asynchronous converter clock and serial data I/O clock. 19-Channel multiplexer with 5-Bit serial address logic. Built-in sample and hold function. Connection Diagrams Ratiometric or absolute voltage referencing. No zero or full-scale adjust required. Internally addressable test voltage. 0V to 5V input range with single 5V power supply. TTL/MOS input/output compatible. 28-pin molded chip carrier or 28-pin molded DIP Y Y Resolution Total unadjusted error Single supply Low Power Conversion Time 8-Bits g (/2LSB and g 1LSB 5VDC 15 mW 16 ms Functional Diagram Molded Chip Carrier (PCC) Package TL/H/9287–1 Top View Order Number ADC0819BCV, CCV See NS Package Number V28A Dual-In-Line Package TL/H/9287 – 2 TL/H/9287–20 Top View Order Number ADC0819BCN, CIN See NS Package Number N28B C1995 National Semiconductor Corporation TL/H/9287 RRD-B30M115/Printed in U. S. A. ADC0819 8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer December 1994 Absolute Maximum Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Voltage Inputs and Outputs Input Current Per Pin (Note 3) Total Package Input Current (Note 3) Storage Temperature Package Dissipation at TA e 25§ C 6.5V b 0.3V to VCC a 0.3V g 5mA Lead Temperature (Soldering, 10 sec.) Dual-In-Line Package (Plastic) Surface Mount Package Vapor Phase (60 sec.) Infrared (15 sec.) 215§ C 220§ C ESD Susceptibility (Note 11) 2000V 260§ C Operating Ratings (Notes 1 & 2) g 20mA Supply Voltage (VCC) Temperature Range ADC0819BCV, ADC0819CCV ADC0819BCN ADC0819CIN b 65§ C to a 150§ C 875 mW 4.5 VDC to 6.0 VDC TMIN s TA s TMAX b 40§ C s TA s a 85§ C 0§ C s TA s a 70§ C b 40§ C s TA s a 85§ C Electrical Characteristics The following specifications apply for VCC e 5V, VREF e 5V, w2 CLK e 2.097 MHz unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ e 25§ C. Parameter Conditions Typical (Note 6) Tested Limit (Note 7) Design Limit (Note 8) Units g (/2 g1 g (/2 g1 LSB LSB 5 kX 11 11 kX VCC a 0.05 VCC a 0.05 V GNDb0.05 GNDb0.05 V 400 1000 nA b 400 b 1000 nA b 400 b 1000 nA 400 1000 nA CONVERTER AND MULTIPLEXER CHARACTERISTICS Maximum Total Unadjusted Error ADC0819BCV, BCN ADC0819CCV, CIN VREF e 5.00 VDC (Note 4) Minimum Reference Input Resistance 8 Maximum Reference Input Resistance 8 Maximum Analog Input Range (Note 5) Minimum Analog Input Range On Channel Leakage Current (Note 9) On Channel e 5V Off Channel e 0V On Channel e 0V Off Channel e 5V (Note 9) Off Channel Leakage Current (Note 9) On Channel e 5V Off Channel e 0V On Channel e 0V Off Channel e 5V (Note 9) Minimum VTEST Internal Test Voltage VREF e VCC, CH 19 Selected 125 125 (Note 10) Counts Maximum VTEST Internal Test Voltage VREF e VCC, CH 19 Selected 130 130 (Note 10) Counts VIN(1), Logical ‘‘1’’ Input Voltage (Min) VCC e 5.25V 2.0 2.0 V VIN(0), Logical ‘‘0’’ Input Voltage (Max) VCC e 4.75V 0.8 0.8 V IIN(1), Logical ‘‘1’’ Input Current (Max) VIN e 5.0V 2.5 2.5 mA IIN(0), Logical ‘‘0’’ Input Current (Max) VIN e 0V b 2.5 b 2.5 mA DIGITAL AND DC CHARACTERISTICS 0.005 b 0.005 2 Electrical Characteristics (Continued) The following specifications apply for VCC e 5V, VREF e 5V, w2 CLK e 2.097 MHz unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ e 25§ C. Parameter Typical (Note 6) Conditions Tested Limit (Note 7) Design Limit (Note 8) Units DIGITAL AND DC CHARACTERISTICS (Continued) VOUT(1), Logical ‘‘1’’ Output Voltage (Min) VCC e 4.75V IOUT eb360 mA IOUT eb10 mA 2.4 4.5 2.4 4.5 V V VOUT(0), Logical ‘‘0’’ Output Voltage (Max) VCC e 5.25V IOUT e 1.6 mA 0.4 0.4 V IOUT, TRI-STATE Output Current (Max) VOUT e 0V VOUT e 5V b 0.01 b3 b3 0.01 3 3 mA mA ISOURCE, Output Source Current (Min) VOUT e 0V b 14 b 6.5 b 6.5 mA ISINK, Output Sink Current (Min) VOUT e VCC 16 8.0 8.0 mA ICC, Supply Current (Max) CS e 1, VREF Open 1 2.5 2.5 mA IREF (Max) VREF e 5V 0.7 1 1 mA AC CHARACTERISTICS Parameter w2 CLK, w2 Clock Frequency SCLK, Serial Data Clock Frequency TC, Conversion Process Time tACC, Access Time Delay From CS Falling Edge to DO Data Valid Conditions Tested Typical Limit (Note 6) (Note 7) MIN 0.70 MAX 4.0 2.0 2.1 1.0 MAX 1000 525 525 MIN 26 26 32 32 MIN Not Including MUX Addressing and MAX Analog Input Sampling Times MIN 1 MAX 3 4/w2CLK a tHCS, CS Hold Time After the Falling Edge of SCLK KHz w2 cycles w2 cycles 1 2 SCLK sec 0 ns MIN tset-up a 8/SCLK sec MAX t CS(min) a 26/w2CLK sec 0 ns 10 ns 400 ns tHDI, Minimum DI Hold Time from SCLK Rising Edge tHDO, Minimum DO Hold Time from SCLK Falling Edge Units MHz 5.0 tSET-UP, Minimum Set-up Time of CS Falling Edge to SCLK Rising Edge t CS, Total CS Low Time Design Limit (Note 8) 0 RL e 30k, CL e 100 pF tSDI, Minimum DI Set-up Time to SCLK Rising Edge 200 tDDO, Maximum Delay From SCLK Falling Edge to DO Data Valid RL e 30k, CL e 100 pF 180 200 250 ns tTRI, Maximum DO Hold Time, (CS Rising edge to DO TRI-STATE) RL e 3k, CL e 100 pF 90 150 150 ns 3 Electrical Characteristics The following specifications apply for VCC e 5V, tr e tf e 20 ns, VREF e 5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ e 25§ C. Parameter Typical (Note 6) Conditions Tested Limit (Note 7) Design Limit (Note 8) Units 3/SCLK a 1 ms sec AC CHARACTERISTICS (Continued) tCA, Analog Sampling Time After Address Is Latched CS e Low tRDO, Maximum DO RL e 30 kX, ‘‘TRI-STATE’’ to ‘‘HIGH’’ State 75 150 150 Rise Time CL e 100 pf ‘‘LOW’’ to ‘‘HIGH’’ State 150 300 300 tFDO, Maximum DO RL e 30 kX, ‘‘TRI-STATE’’ to ‘‘LOW’’ State 75 150 150 Fall Time CL e 100 pf ‘‘HIGH’’ to ‘‘LOW’’ State 150 300 300 CIN, Maximum Input Analog Inputs, ANO–AN10 and VREF 11 55 Capacitance All Others 5 15 ns ns pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to ground. Note 3: Under over voltage conditions (VIN k 0V and VIN l VCC) the maximum input current at any one pin is g 5 mA. If the voltage at more than one pin exceeds VCC a .3V the total package current must be limited to 20 mA. For example the maximum number of pins that can be over driven at the maximum current level of g 5 mA is four. Note 4: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors. Note 5: Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 6: Typicals are at 25§ C and represent most likely parametric norm. Note 7: Tested Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Design Limits are guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels. Note 9: Channel leakage current is measured after the channel selection. Note 10: 1 count e VREF/256. Note 11: Human body model; 100 pF discharged through a 1.5 kX resistor. Test Circuits D0 Except ‘‘TRI-STATE’’ Leakage Current TL/H/9287 – 4 TL/H/9287–3 tTRI ‘‘TRI-STATE’’ Timing Diagrams D0 ‘‘TRI-STATE’’ Rise & Fall Times TL/H/9287 – 6 TL/H/9287–5 4 Timing Diagrams (Continued) D0 Low to High State D0 High to Low State TL/H/9287 – 7 TL/H/9287 – 8 Data Input and Output Timing TL/H/9287 – 9 Timing with a continuous SCLK TL/H/9287 – 10 *Strobing CS High and Low will abort the present conversion and initiate a new serial I/O exchange. Timing with a gated SCLK and CS Continuously Low TL/H/9287 – 11 Using CS To TRI-STATE D0 TL/H/9287 – 12 Note: Strobing CS Low during this time interval will abort the conversion in process. 5 Timing Diagrams (Continued) CS High During Conversion TL/H/9287 – 13 CS Low During Conversion TL/H/9287 – 14 Channel Addressing Table TABLE I. ADC 0819 Channel Addressing MUX ADDRESS A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X ANALOG CHANNEL SELECTED CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 VTEST No Channel Select No Channel Select No Channel Select No Channel Select Logic Test Mode* *Analog channel inputs CH0 thru CH4 are logic outputs 6 TL/H/9287 – 15 Functional Block Diagram 7 Functional Description 1.0 DIGITAL INTERFACE this mux address/sample cycle, data from the last conversion is also clocked out on DO. Since D7 was clocked out on the falling edge of CS only data bits D6 – D0 remain to be received. The following seven falling edges of SCLK shift out this data on DO. The 8th SCLK falling edge initiates the beginning of the A/D’s actual conversion process which takes between 26 and 32 w2 cycles (TC). During this time CS can go high to TRISTATE DO and disable the SCLK input or it can remain low. If CS is held low a new I/O exchange will not start until the conversion sequence has been completed, however once the conversion ends serial I/O will immediately begin. Since there is an ambiguity in the conversion time (TC) synchronizing the data exchange is impossible. Therefore CS should go high before the 26th w2 clock has elasped and return low after the 32nd w2 to synchronize serial communication. A conversion or I/O operation can be aborted at any time by strobing CS. If CS is high or low less than one w2 clock it will be ignored by the A/D. If the CS is strobed high or low between 1 to 3 w2 clocks the A/D may or may not respond. Therefore CS must be strobed high or low greater than 3 w2 clocks to ensure recognition. If a conversion or I/O exchange is aborted while in process the consequent data output will be erroneous until a complete conversion sequence has been implemented. The ADC0819 uses five input/output pins to implement the serial interface. Taking chip select (CS) low enables the I/O data lines (DO and DI) and the serial clock input (SCLK). The result of the last conversion is transmitted by the A/D on the DO line, while simultaneously the DI line receives the address data that selects the mux channel for the next conversion. The mux address is shifted in on the rising edge of SCLK and the conversion data is shifted out on the falling edge. It takes eight SCLK cycles to complete the serial I/O. A second clock (w2) controls the SAR during the conversion process and must be continuously enabled. 1.1 CONTINUOUS SCLK With a continuous SCLK input CS must be used to synchronize the serial data exchange (see Figure 1 ). The ADC0819 recognizes a valid CS one to three w2 clock periods after the actual falling edge of CS. This is implemented to ensure noise immunity of the CS signal. Any spikes on CS less than one w2 clock period will be ignored. CS must remain low during the complete I/O exchange which takes eight SCLK cycles. Although CS is not immediately acknowledged for the purpose of starting a new conversion, the falling edge of CS immediately enables DO to output the MSB (D7) of the previous conversion. The first SCLK rising edge will be acknowledged after a setup time (tset-up) has elapsed from the falling edge of CS. This and the following seven SCLK rising edges will shift in the channel address for the analog multiplexer. Since there are 19 channels only five address bits are utilized. The first five SCLK cycles clock in the mux address, during the next three SCLK cycles the analog input is selected and sampled. During 1.2 DISCONTINUOUS SCLK Another way to accomplish synchronous serial communication is to tie CS low continuously and disable SCLK after its 8th falling edge (see Figure 2 ). SCLK must remain low for TL/H/9287 – 16 FIGURE 1 TL/H/9287 – 17 FIGURE 2 8 Functional Description (Continued) at least 32 w2 clocks to ensure that the A/D has completed its conversion. If SCLK is enabled sooner, synchronizing to the data output on DO is not possible since an end of conversion signal from the A/D is not available and the actual conversion time is not known. With CS low during the conversion time (32 w2 max) DO will go high or low after the eighth falling edge of SCLK until the conversion is completed. Once the conversion is through DO will transmit the MSB. The rest of the data will be shifted out once SCLK is enabled as discussed previously. If CS goes high during the conversion sequence DO is tristated, and the result is not affected so long as CS remains high until the end of the conversion. eighth SCLK falling edge. The hold mode is initiated with the start of the conversion process. An acquisition window of 3tSCLK a 1 msec is therefore available to allow the ladder capacitance to settle to the analog input voltage. Any change in the analog voltage before or after the acquisition window will not effect the A/D conversion result. In the most simple case, the ladder’s acquisition time is determined by the Ron (3K) of the multiplexer switches and the total ladder capacitance (90pf). These values yield an acquisition time of about 2 msec for a full scale reading. Therefore the analog input must be stable for at least 2 msec before and 1 msec after the eighth SCLK falling edge to ensure a proper conversion. External input source resistance and capacitance will lengthen the acquisition time and should be accounted for. Other conventional sample and hold error specifications are included in the error and timing specs of the A/D. The hold step and gain error sample/hold specs are taken into account in the ADC0819’s total unadjusted error, while the hold settling time is included in the A/D’s max conversion time of 32 w2 clock periods. The hold droop rate can be thought of as being zero since an unlimited amount of time can pass between a conversion and the reading of data. However, once the data is read it is lost and another conversion is started. 1.2 MULTIPLEXER ADDRESSING The five bit mux address is shifted, MSB first, into DI. Input data corresponds to the channel selected as shown in table 1. Care should be taken not to send an address greater than or equal to twenty four (11XXX) as this puts the A/D in a digital testing mode. In this mode the analog inputs CH0 thru CH4 become digital outputs, for our use in production testing. 2.0 ANALOG INPUT 2.1 THE INPUT SAMPLE AND HOLD The ADC0819’s sample/hold capacitor is implemented in its capacitive ladder structure. After the channel address is received, the ladder is switched to sample the proper analog input. This sampling mode is maintained for 1 msec after the Typical Applications ADC0819-INS8048 INTERFACE TL/H/9287 – 18 9 ADC0819 FUNCTIONAL CIRCUIT TL/H/9287 – 19 Ordering Information Temperature Range Total Unadjusted Error g (/2 LSB 0§ C to a 70§ C ADC0819BCN g 1 LSB Package Outline N28B 10 b 40§ C to a 85§ C ADC0819BCV ADC0819CCV ADC0819CIN V28A N28B Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number ADC0819BCN or ADC0819CIN NS Package Number N28B 11 ADC0819 8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer Physical Dimensions inches (millimeters) (Continued) Molded Chip Carrier (V) Order Number ADC0819BCV, CCV NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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