MOTOROLA MC74HCT14AN

SEMICONDUCTOR TECHNICAL DATA
$ " # ! High–Performance Silicon–Gate CMOS
The MC54/74HCT14A may be used as a level converter for interfacing
TTL or NMOS outputs to high–speed CMOS inputs.
The HCT14A is identical in pinout to the LS14.
The HCT14A is useful to “square up” slow input rise and fall times. Due to
the hysteresis voltage of the Schmitt trigger, the HCT14A finds applications
in noisy environments.
14
•
•
•
•
•
•
14
Output Drive Capability: 10 LSTTL Loads
TTL/NMOS–Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
1
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
ORDERING INFORMATION
MC54HCTXXAJ
MC74HCTXXAN
MC74HCTXXAD
Ceramic
Plastic
SOIC
LOGIC DIAGRAM
A1
A2
A3
1
3
5
2
4
6
PIN ASSIGNMENT
Y1
Y2
Y3
Y=A
A4
A5
A6
9
8
11
10
13
12
1
14
VCC
Y1
2
13
A6
A2
3
12
Y6
Y2
4
11
A5
A3
5
10
Y5
Y3
6
9
A4
GND
7
8
Y4
Y4
FUNCTION TABLE
Y5
Y6
PIN 14 = VCC
PIN 7 = GND
10/95
 Motorola, Inc. 1995
A1
3–1
REV 6
Input
A
Output
Y
L
H
H
L
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MC54/74HCT14A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
_C
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
—
*
ns
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
* No Limit when Vin
50% VCC, ICC > 1 mA.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Temperature Limit
VCC
Volts
Test Conditions
– 55 to
25_C
85_C
125_C
Symbol
Parameter
VT+ max
Maximum Positive–Going
Input Threshold Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
VT+ min
Minimum Positive–Going
Input Threshold Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
VT– max
Maximum Positive–Going
Input Threshold Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
VT– min
Minimum Positive–Going
Input Threshold Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
VH max
Maximum Hysteresis
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
VH min
Minimum Hysteresis
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
0.4
0.4
0.4
0.4
0.4
04
VOH
Minimum High–Level
Output Voltage
Vin < VT–min
|Iout|
20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
Vin < VT–min
|Iout|
4.0 mA
4.5
3.98
3.84
3.7
Min
Max
Min
1.9
2.1
1.2
1.4
Max
1.2
1.4
1.2
1.4
0.5
0.6
Min
1.9
2.1
Unit
1.9
2.1
V
1.2
1.4
1.2
1.4
0.5
0.6
1.4
1.5
Max
V
1.2
1.4
0.5
0.6
1.4
1.5
1.4
1.5
V
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
(continued)
MOTOROLA
3–2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HCT14A
DC CHARACTERISTICS (Voltages Referenced to GND) – continued
Temperature Limit
Symbol
VOL
Iin
ICC
∆ICC
Parameter
VCC
Volts
Test Conditions
Maximum Low–Level
Output Voltage
– 55 to
25_C
Min
85_C
Max
Min
125_C
Max
Min
Max
Unit
V
Vin < VT–min
|Iout|
20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin < VT–min
IIoutI
4.0 mA
4.5
0.26
0.33
0.4
Maximum Input
Leakage Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent
Supply Current
(per package)
Vin = VCC or GND
Iout = 0 µA
5.5
1.0
10
40
µA
Additional Quiescent
Supply Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 µA
≥ – 55_C
25_C to
125_C
2.9
2.4
5.5
mA
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to
25_C
Symbol
Parameter
Test Conditions
tPLH,
tPHL
Maximum Propagation Delay,
Input A to Output Y (L to H)
VCC = 5.0 V ± 10%
CL = 50 pF, Input tr = tf = 6.0 ns
Fig.
1&2
32
tTLH,
tTHL
Maximum Output Transition
Time. Any Output
VCC = 5.0 V ± 10%
CL = 50 pF, Input tr = tf = 6.0 ns
Fig.
1&2
15
Min
Max
85_C
Min
125_C
Max
Unit
40
48
ns
19
22
ns
Max
Min
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Inverter)*
pF
32
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
tf
2.7 V
INPUT A 1.3 V
0.3 V
tr
TEST POINT
3V
OUTPUT
GND
tPLH
DEVICE
UNDER
TEST
tPHL
90%
1.3 V
10%
OUTPUT Y
tTLH
CL*
tTHL
* Includes all probe and jig capacitance
Figure 1. Switching Waveforms
High–Speed CMOS Logic Data
DL129 — Rev 6
Figure 2. Test Circuit
3–3
MOTOROLA
MC54/74HCT14A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
-A14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMESNION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
-B-
C
-T-
L
DIM
A
B
C
D
F
G
J
K
L
M
N
K
SEATING
PLANE
F
G
D 14 PL
0.25 (0.010)
M
N
T A
M
J 14 PL
0.25 (0.010)
S
M
T
B
S
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
14
B
7
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
D
SEATING
PLANE
K
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
–A–
14
1
P 7 PL
0.25 (0.010)
7
G
D
0.25 (0.010)
MOTOROLA
M
T
B
S
M
F
M
K
14 PL
B
R X 45°
C
SEATING
PLANE
M
A
S
3–4
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
8
–B–
MILLIMETERS
MIN
MAX
19.05 19.94
6.23
7.11
3.94
5.08
0.39
0.50
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0°
15°
0.51
1.01
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
8
1
INCHES
MIN
MAX
0.750 0.785
0.245 0.280
0.155 0.200
0.015 0.020
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
0°
15°
0.020 0.040
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.228 0.244
0.010 0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT14A
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
*MC54/74HCT14A/D*
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