19-0297; Rev 1; 9/95 NUAL KIT MA ATION SHEET A EVALU T A D WS FOLLO 300Msps, 12-Bit DAC with Complementary Voltage Outputs ________________________Applications Direct Digital Synthesis Arbitrary Waveform Generation HDTV/High-Resolution Graphics Instrumentation Communications Local Oscillators Automated Tester Applications ____________________________Features ♦ 12-Bit Resolution ♦ ±1/2LSB Integral and Differential Nonlinearity ♦ Capable of 300Msps Min Update Rate ♦ Complementary 50Ω Outputs ♦ Multiplying Reference Input ♦ Low Glitch Energy (5.6pVs) ♦ Single -5.2V Power Supply ♦ On-Chip Data Registers ♦ ECL-Compatible Inputs with Differential Clock ______________Ordering Information PART MAX555CQK TEMP. RANGE PIN-PACKAGE 0°C to +70°C 68 Thermally Enhanced PLCC Pin Configuration appears at end of data sheet. ___________________________________________________Simplified Block Diagram CLK CLK 800Ω VREF 12-BIT ECL LINES LEVEL-SENSITIVE TRANSPARENT LATCH MAX555 800Ω ROFFSET VOUT DECODED BIT LINES VOUT 50Ω 50Ω -20mA LGND AVEE BYPASS ________________________________________________________________ Maxim Integrated Products Call toll free 1-800-998-8800 for literature. 1 MAX555 _______________General Description The MAX555 is an advanced, monolithic, 12-bit digitalto-analog converter (DAC) with complementary 50Ω outputs. Fabricated using an oxide-isolated bipolar process, the MAX555 is designed for signal-reconstruction applications at an output update rate of 300Msps. It incorporates an analog multiplying function with 10MHz useable input bandwidth. The voltage-output DAC uses precision laser trimming to achieve 12-bit accuracy with ±1/2LSB integral and differential linearity (±0.012% FS). Absolute gain error is a low 1% of full scale. Full-scale transitions occur in less than 0.5ns. Internal registers and a unique decoder reduce glitching and allow the MAX555 to achieve precise RF performance with over 73dBc of spurious-free dynamic range at 50Msps with fOUT = 3.1MHz, or 62dBc at 300Msps with fOUT = 18.6MHz. The MAX555 operates from a single -5.2V supply and dissipates 980mW (nominal). It comes in a 68-pin thermally enhanced PLCC package capable of accepting a heatsink. MAX555 300Msps, 12-Bit DAC with Complementary Voltage Outputs ABSOLUTE MAXIMUM RATINGS Analog Supply Voltage (AVEE) .................................-7V to +0.3V Digital Supply Voltage (DVEE) ..................................-7V to +0.3V Digital Input Voltage (D0–D11) ...................................-5.5V to 0V Reference Input Voltage (VIN) .................................0V to +1.25V Reference Input Current....................................0mA to +1.56mA Output Compliance Voltage (VOC)......................-1.25V to +1.0V Output Common-Mode Voltage (VCM) ................-0.25V to +1.0V Note 1: Typical thermal resistance, junction-to-case RθJC = 28°C/W. Continuous Power Dissipation (TA = +70°C) (without additional heatsink) ..............................................1.3W Operating Temperature Range...............................0°C to +70°C Junction Temperature Range (Note 1) .................0°C to +150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C See Package Information. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVEE = DVEE = -5.2V, VREF = 1.000V, TMIN to TMAX = 0°C to +70°C, unless otherwise noted.) (Note 2.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS % Full Scale DC ACCURACY Differential Linearity Error Integral Linearity Error Absolute Gain Error DLE1 DLE2 ILE1 ILE2 VREF = 1.000V, current out, into virtual ground, end-point linearity VOUT -0.012 ±0.003 0.012 VOUT -0.05 ±0.01 0.05 VREF = 1.000V, current out, into virtual ground, end-point linearity VOUT -0.012 ±0.006 0.012 VOUT -0.05 ±0.01 0.05 -1.0 ±0.2 1.0 % Full Scale % Full Scale EG VREF = 1.000V, voltage out, VOUT/VIN (Note 3) IOS D0–D11 = logic 1, VREF = 1.000V, measured at VOUT 40 100 µA D0–D11 = logic 0, VREF = 0V, measured at VOUT 3 50 µA 90% to 10%, TA = +25°C 10% to 90%, TA = +25°C Major carry, TA = +25°C ±0.1% FSR ±0.024% FSR, 1LSB change 510 450 5.6 4 15 Spurious-Free Dynamic Range fOUT = 5MHz, fCLK = 50MHz fOUT = 10MHz, fCLK = 50MHz fOUT = 20MHz, fCLK = 100MHz fOUT = 30MHz, fCLK = 100MHz fOUT = 30MHz, fCLK = 200MHz fOUT = 40MHz, fCLK = 200MHz fOUT = 40MHz, fCLK = 250MHz fOUT = 50MHz, fCLK = 250MHz fOUT = 40MHz, fCLK = 300MHz fOUT = 50MHz, fCLK = 300MHz 70 70 65 60 56 53 52 51 52 51 dBc Output Noise Bits 0–11 high, TA = +25°C 10.6 nV √Hz 12-Bit Monotonicity Output Offset Current Output Leakage Current Guaranteed ILEAK TIME-DOMAIN PERFORMANCE (Note 4) Fall Time tFALL Rise Time tRISE Glitch Energy Settling Time ps ps pVs ns DYNAMIC PERFORMANCE (Notes 4, 5) 2 _______________________________________________________________________________________ 300Msps, 12-Bit DAC with Complementary Voltage Outputs (AVEE = DVEE = -5.2V, VREF = 1.000V, TMIN to TMAX = 0°C to +70°C, unless otherwise noted.) (Note 2.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS Input Current, Logic High IIH VIH = -0.75V 10 200 µA Input Current, Logic Low IIL VIL = -1.95V 1 2 µA Logic "1" Voltage VIH -1.1 -0.75 0 V Logic "0" Voltage VIL -2.0 -1.95 -1.48 V DIGITAL TIMING Data Update Rate fD Minimum data rate = DC (Note 6) Data-to-Clock Setup Time tSU Bypass = 0, clocked mode (Notes 4, 7) 1 ps Data-to-Clock Hold Time tHOLD Bypass = 0, clocked mode (Notes 4, 7) 1.8 ns tPD3 Bypass = 0, clocked mode (Notes 4, 7) 2.0 ns tPD2 Bypass = 1, transparent mode (Notes 4, 7) 1.5 ns tPD1 Bypass = 1, transparent mode (Notes 4, 7) 2.1 ns tDD Bypass = 1, transparent mode (Notes 4, 7) 600 ps Clock-to-VOUT Propagation Delay LSBs Data-to-VOUT Propagation Delay MSBs Data-to-VOUT Propagation Delay MSBs Decode Delay CONTROL AMPLIFIER Amplifier Input Resistance Multiplying Input Bandwidth Open-Loop Gain Input Offset Voltage OUTPUT PERFORMANCE Full-Scale Output Current Output Resistance Output Capacitance POWER SUPPLIES Analog Power-Supply Current Digital Power-Supply Current Power Dissipation Package Thermal Resistance, Junction to Ambient RIN BW AVOL VOS VREF = 1.000V -3dB TA = +25°C TA = +25°C IOUT ROUT VREF = 1.000V, RL = 0Ω VOUT, VOUT COUT VOUT, VOUT AIEE DIEE PD AVEE = DVEE = -5.2V AVEE = DVEE = -5.2V TJA 300 MHz 3 -250 800 10 20 0 250 Ω MHz kV/V µV 19.0 49.5 20.0 50.0 21.0 50.5 mA Ω 775 825 15 30 110 46 150 0.98 pF 60 190 1.3 28 mA mA W °C/W Note 2: All devices are 100% production tested at +25°C and are guaranteed by design for TA = TMIN to TMAX as specified. Note 3: The gain-error method of calculation is shown below: Definition: [VMEASURE(FS) - VIDEAL(FS)] x 100 EG(%) = –––––––––––––––––––––––––––––––––– VIDEAL(FS) where FS indicates full-scale measurements. EG Method: EG = [(4096 / 4095) VMEASURE - 16(VREF / RIN) (ROUT)] x 100 –––––––––––––––––––––––––––––––––––––––––––––––––– % 16(VREF / RIN) (ROUT) = [(4096 / 4095) VMEASURE - 1] x 100 ––––––––––––––––––––––––––––––––- % 1 where: VREF = 1.000V, RIN = 800Ω, ROUT = 50Ω, VMEASURE = VOUT (FS). Note 4: Dynamic and timing specifications are obtained from device characterization and simulation testing and are not production tested. Note 5: Spurious-free dynamic range is measured from the fundamental frequency to any harmonic or non-harmonic spurs within the bandwidth fCLK/2, unless otherwise specified. Note 6: Guaranteed by design. Note 7: Timing definitions are detailed in Figure 2. _______________________________________________________________________________________ 3 MAX555 ELECTRICAL CHARACTERISTICS (continued) __________________________________________Typical Operating Characteristics (VREF = 0.75V, TA = +25°C, unless otherwise noted.) SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 50MHz) SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 150MHz) SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 100MHz) 70 70 68 68 MAX555-03 68 MAX555-02 72 MAX555-01 72 66 66 SFDR (dBc) SFDR (dBc) SFDR (dBc) 64 66 64 64 62 62 60 60 62 60 58 56 2 6 4 8 10 12 14 16 18 20 52 0 5 10 20 15 25 35 30 SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 200MHz) SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 250MHz) SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 300MHz) 66 64 62 64 60 SFDR (dBc) 60 58 SFDR (dBc) 62 62 60 58 56 5 10 15 20 25 35 30 56 54 50 52 52 58 52 54 54 50 48 48 46 40 0 5 10 15 20 25 30 35 40 45 50 0 10 20 30 40 50 fOUT (MHz) fOUT (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. fCLK (fOUT ~ 1/16 fCLK) 3RD HARMONIC DISTORTION vs. VREF VOLTAGE (fOUT ~ 1/5 fCLK) 2ND HARMONIC DISTORTION vs. VREF VOLTAGE (fOUT ~ 1/5 fCLK) MAX555-08 72 -52 3RD HARMONIC (dBc) 70 68 66 64 62 60 58 fCLK = 300MHz -54 -56 -58 -60 -62 -64 fCLK = 200MHz -66 -68 -70 fCLK = 100MHz 150 200 250 300 CLOCK FREQUENCY (MHz) 350 -52 -54 -56 fCLK = 300MHz fCLK = 200MHz -58 -60 -62 -64 -66 -68 -70 fCLK = 100MHz -72 -72 100 -48 -50 3RD HARMONIC (dBc) MAX555-07 -48 -50 60 MAX555-09 fOUT (MHz) 74 40 MAX555-06 MAX555-04 68 56 4 20 fOUT (MHz) 64 50 15 10 fOUT (MHz) 66 0 5 0 25 fOUT (MHz) 68 SFDR (dBc) 54 MAX555-05 0 SFDR (dB) MAX555 300Msps, 12-Bit DAC with Complementary Voltage Outputs 0.5 0.6 0.7 0.8 VREF VOLTAGE (V) 0.9 1.0 0.5 0.6 0.7 0.8 VREF VOLTAGE (V) _______________________________________________________________________________________ 0.9 1.0 300Msps, 12-Bit DAC with Complementary Voltage Outputs PIN NAME FUNCTION Disables latching of data when high (ECL input) 1 BYPASS 2 CLK Data Clock (ECL input) 3 CLK Data Clock Not (ECL input) 4, 56, 57, 63, 66 5, 55 10, 11, 12, 21–25, 27, 31, 36, 37, 40, 41, 43, 45, 46, 61 13, 14 15, 16 DGND Digital Signal Grounds DVEE -5.2V Digital Power Supplies N.C. No Connection VOUT LGND DAC Outputs Ladder Grounds DAC Output Complements 17, 18 VOUT 19, 49, 51, 52, 53, 68 TN 20, 29, 30, 48 AGND 26, 44 HS 28 ALTCOMPIB PTAT-IB Reference Compensation Output (connect bypass capacitor to AVEE) 32 LOOPCRNT Test node—must connect to AGND 33, 34 AVEE -5.2V Analog Power Supplies 35 VREF/2 Analog Reference Voltage Center-Tap Input 38, 39 VREF Analog Reference Voltage Inputs (Kelvin connection) 42 ROFFSET Offset Compensation Input 47 ALTCOMPC Control-Amplifier PTAT Reference Compensation Input (connect bypass capacitor to AVEE) 50 LBIAS Ladder-Bias Alternate Compensation Output (connect bypass capacitor to AVEE) 54, 58, 59, 60, 62, 64, 65, 67, 6, 7, 8, 9 D11(MSB)– D0(LSB) Test Node—internal test point, do not connect Analog Signal Grounds Heatspreader Connections— bypass with 0.1µF to AVEE Data Words (ECL inputs) _______________Detailed Description Figure 1’s functional diagram shows the MAX555’s three major divisions: a digital section, a control-amplifier section, and a resistor-divider network. The digital section consists of a master/slave register, decoding logic, and current switches. The control-amplifier section includes a control amplifier and an array of 23 current sources divided into three groups. The resistor divider scales the currents from these groups to achieve the correct binary weighting at the output. The output of the resistor-divider network is laser trimmed to 50Ω, a key feature for driving into controlled impedance transmission lines. The first group of current sources comprises the six MSBs, D11–D6 (resulting in 15 identical, plus two binary weighted currents), which are applied directly to the output of the resistor-divider network. The second group, bits D5–D3 (three binary weighted currents), is applied to the middle of the divider network. The middle of the network divides the current seen at the output by 8. The third group, bits D2–D0 (three additional binary weighted current sources), is applied to the input of the resistive network, dividing the current seen at the output by 64. Glitching is reduced by decoding the four MSBs into 15 identical current sources and synchronizing data with a master/slave register at every current switch. Data bits are transferred to the output on the positive-going edge of the clock, with the BYPASS input asserted low. In the asynchronous mode with the BYPASS input asserted high, the latches are transparent and data is transferred to the output regardless of the clock state. All digital inputs are ECL compatible. The clock input is differential. The control amplifier forces a reference current, which is replicated in the current sources. This reference current is nominally 1.25mA. It can be supplied by an external current source, or by an external voltage source of 1.000V applied to the VREF input. A reference input of VREF = 1.000V will produce a fullscale output voltage of VFS = -1.000V, where: VFS = 4096 / 4095 x VOUT (code 0) for the VOUT output. The output coding is summarized in Table 1. The DAC’s control amplifier has a typical open-loop voltage gain of 85dB, and its gain-magnitude bandwidth is flat up to 10MHz. When the control amplifier is not being used for high-speed multiplying applications, it is recommended that a 0.4µF capacitor be connected from LBIAS to AVEE to increase control-amplifier stability and reduce current-source noise. _______________________________________________________________________________________ 5 MAX555 _____________________Pin Description MAX555 300Msps, 12-Bit DAC with Complementary Voltage Outputs RESISTOR-DIVIDER NETWORK DIGITAL SECTION I1 3 CURRENT I2 SOURCES AND I3 SWITCHING NETWORK 3 17 I3 17 I2 3 I1 3 LSB (D0) MASTER REGISTER SLAVE REGISTER 8 8 12 INPUTS 4 MSB (D11) CLK 4 TO 15 15 DECODER 15 ÷8 ÷8 IO 50Ω LGND 2 50Ω ÷8 ÷8 IO MAX555 CLK BYPASS LOOPCRNT ALTCOMPC I = VIN/RIN VREF/2 400Ω 400Ω VREF 1V FS ALTCOMPIB 800Ω ROFFSET 800Ω CONTROL AMPLIFIER AVEE LBIAS DVEE AVEE AGND Figure 1. Functional Diagram 6 VOUT _______________________________________________________________________________________ DGND VOUT 300Msps, 12-Bit DAC with Complementary Voltage Outputs DIGITAL CODE (D11–D0) VOUT (V) VOUT (V) 000000000000 000000000001 011111111111 100000000000 111111111111 -0.999756 -0.999512 -0.500000 -0.499756 0 0 -0.000244 -0.499756 -0.500000 -0.999756 Timing Information The MAX555 features a differential ECL clock input with selective transparent operation (BYPASS = 1). It is possible to drive the MAX555 clock single-ended if desired by tying the CLK input to an external voltage of -1.3V (ECL VBB). However, using a differential clock provides greater noise immunity and improved dynamic performance. In the clocked mode (BYPASS = 0), when the clock line is low, the slave register is locked out and information on the digital inputs is permitted to enter the master register. The clock transition from low to high locks the master register in its present state and ignores further changes on the digital inputs. This transition simultaneously transfers the contents of the master register to the slave register, causing the DAC output to change. Figure 2’s timing diagram illustrates the importance of operating the MAX555 in the clocked mode. In the transparent mode (BYPASS = 1), both the master and slave registers are transparent, and changes in input data rip- ple directly to the output. Because the four MSBs are decoded into 15 identical currents, there is a decode delay for these bits that is longer than for the eight LSBs. For the full-scale transition case shown, an intermediate output of 1/16 full-scale occurs until the four MSBs are properly decoded. This decode delay seriously degrades the device’s spurious performance. In addition, skew in the timing of the input data also directly appears at the DAC output, further degrading high-speed performance. MAX555 operation in the clocked mode (BYPASS = 0) with a differential clock precludes both of these potential problems and is required for high-speed operation. Since input data can only enter the master register when the clock is low (while the slave register is locked out), data-bus timing skew and the internal MSB decode delay will not appear at the DAC output. The DAC currents are switched only when the clock transitions from low to high, after the internal data stabilizes. Layout and Power Supplies The MAX555 has separate pins for analog and digital supplies. AVEE and DVEE are connected to each other through the substrate of the IC. These potentials should be derived from the same supply to minimize voltage mismatch, which would cause substrate current flow and possible latchup. Appropriate decoupling is needed to prevent digital-section current spikes from affecting the analog section (Figure 4). It is recommended that a multilayer PC board be used, containing a solid ground and power planes. All analog CLOCKED MODE BYPASS = 0 TRANSPARENT MODE BYPASS = 1 D0 D11 D0 D11 tSU tHOLD tPD1 VOUT tPD2 15 16 F.S. 1 16 F.S. CLK tPD3 VOUT tDD VOUT VOUT Figure 2. Timing Diagram _______________________________________________________________________________________ 7 MAX555 Table 1. Output Coding MAX555 300Msps, 12-Bit DAC with Complementary Voltage Outputs and digital ground pins must be connected directly to the analog ground plane at the MAX555, preferably with a “star connection” at the LGND pins (15 and 16). High-speed ECL inputs, as well as the output from the MAX555, should employ good transmission-line techniques, with terminations close to the device pins. Separate power-supply buses for analog and digital power supplies are recommended as good general practice. Best results will be achieved by bypassing the device pins with high-quality ceramic chip capacitors connected physically close to the pins. __________Applications Information Reference Input The MAX555 uses an internal op-amp circuit to buffer the reference current. The input to the op amp may be driven with a 1.25mA external current source or a 1V external voltage reference. The reference input is the VREF pin. The input impedance to the op amp is 800Ω. As shown in Figure 1, VREF/2 is brought out externally with 400Ω of impedance to the op amp. These reference inputs can be used to vary the full-scale output for high-speed multiplying applications. ROFFSET must be connected to analog ground. In addition, a 0.1µF capacitor should be connected from VREF/2 to analog ground to reduce reference current noise. Outputs The analog outputs are laser trimmed to 50Ω. They can be used either as a voltage drive with 50Ω impedance, or to drive into a virtual null using a transimpedance amplifier. Greater speed is achieved driving into 50Ω loads. The differential outputs of the MAX555 may be used to drive a balun for conversion to a single-ended output, while at the same time greatly reducing the second-harmonic content of the output. Dynamic Performance The Typical Operating Characteristics graphs show the MAX555’s performance when used in direct digital synthesis (DDS) applications for generating RF sine waves. The first six graphs show the MAX555’s spurious-free dynamic range (SFDR) for clock frequencies of 50MHz to 300MHz at various output frequencies. The seventh graph shows the SFDR for clock frequencies from 50MHz to 350MHz while producing an output frequency of about 1/16 the clock frequency. The last two graphs show the MAX555’s third and second harmonic distortion while producing an output frequency of about 1/5 fCLK for clock frequencies from 100MHz to 300MHz as a function of the reference voltage. The third harmonic content of the output can be reduced at clock frequencies below about 200MHz by 8 reducing the reference voltage from its 1.000V nominal value. At clock frequencies above about 200MHz, the output’s third harmonic content is dominated by coupling from the high-speed digital inputs to the output. Reducing the reference voltage at these high clock rates actually increases the third harmonic distortion in the output, since the carrier amplitude drops but the third harmonic level remains relatively constant. The second harmonic distortion of the outputs is shown as a function of clock frequency and reference voltage. It is relatively constant for clock frequencies below about 200MHz at different VREF values. As with the third harmonic distortion, however, the second harmonic distortion also increases at clock frequencies over 200MHz for lower VREF values. Minimize these effects by bypassing the MAX555 heatspreader (pins 26 and 44) to V EE with a good-quality RF chip capacitor. Reducing the swing of the input logic levels and/or decreasing the rise time of the digital signals can also improve the output’s harmonic content. Combining these techniques achieves the best results. Some experimentation may be required to optimize the MAX555’s performance for a particular application. Figure 3 shows the spectrum analyzer plots of the MAX555 when used in DDS applications. These plots show the MAX555’s output spectrum at clock frequencies from 50MHz to 300MHz while producing various output frequencies. Observing the output spectrum while adjusting the reference voltage or varying the logic levels is a sensitive method of optimizing MAX555 performance. The plots shown were obtained with a +0.75V reference voltage with 500mV ECL logic swings. Typical Application Figure 4 shows a typical connection. With VOUT used to drive a 50Ω line, the unused complementary output, VOUT, should also be terminated to 50Ω. A 1V reference voltage at VREF gives a -0.5V full-scale voltage at VOUT (when doubly terminated with 50Ω on the output). Because some loads may represent a complex impedance, be sure to match the output impedance with the load. Mismatching the impedances can cause reflections that will affect AC-performance parameters. In all applications, the LOOPCRNT pin is always connected to AGND, and compensation capacitors are connected to pins ALTCOMPC, ALTCOMPIB, and LBIAS. The LBIAS compensation is recommended for non-multiplying applications. AC grounding the heat spreader on the package (with pins 26 and 44) reduces digital noise feedthrough and improves the MAX555’s spurious performance at high data rates. _______________________________________________________________________________________ 300Msps, 12-Bit DAC with Complementary Voltage Outputs -1 -1 -11 -21 -21 -31 -31 dBM dBM OUTPUT SPECTRUM (fOUT = 24MHz, fCLK = 100MHz) -11 -41 -51 -61 -61 -71 -71 -81 2.3MHz/div 4.5MHz/div OUTPUT SPECTRUM (fOUT = 9.3MHz, fCLK = 150MHz) OUTPUT SPECTRUM (fOUT = 30MHz, fCLK = 200MHz) -1 -1 -11 -11 -21 -21 -31 -31 dBM dBM -41 -51 -81 -41 -41 -51 -51 -61 -61 -71 -71 -81 -81 7MHz/div 9.5MHz/div OUTPUT SPECTRUM (fOUT = 20MHz, fCLK = 250MHz) OUTPUT SPECTRUM (fOUT = 55MHz, fCLK = 300MHz) -1 -1 -11 -11 -21 -21 -31 -31 dBM dBM MAX555 OUTPUT SPECTRUM (fOUT = 5MHz, fCLK = 50MHz) -41 -41 -51 -51 -61 -61 -71 -71 -81 -81 12MHz/div 15MHz/div Measurement Conditions: 10dB/div vertical display, 300Hz video filter, TEK2755AP spectrum analyzer VREF = 0.75V, TA = +25°C, unless otherwise noted. Figure 3. Spectrum Analyzer Plots _______________________________________________________________________________________ 9 MAX555 300Msps, 12-Bit DAC with Complementary Voltage Outputs VREF 1.000V POWER SUPPLY -5.2V 0.1µF IREF 1.25mA 0.1µF 0.1µF 0.1µF 0.1µF 50Ω LINES 35 42 VREF/2 ROFFSET 38, 39 VREF 54 -2V 58 -2V 59 -2V 60 32 33, 34 LOOPCRNT AVEE 5 55 DVEE DVEE D11 (MSB) D10 D9 50Ω LINES D8 -2V 62 17, 18 12-BIT ECL DATA WORD D7 -2V 64 -2V 65 VOUT D6 50Ω D5 -2V 67 -2V 6 D4 MAX555 LGND D3 -2V 7 -2V 8 15, 16 D2 50Ω D1 -2V 9 D0 (LSB) DIFFERENTIAL ECL CLOCK -2V VOUT TERMINATE UNUSED OUTPUT 2 CLK -2V 13, 14 3 CLK -2V -2V 1 BYPASS HS 50Ω PULL-DOWNS ALTCOMPC ALTCOMPIB LBIAS 26, 44 47 28 50 0.1µF 0.1µF 0.1µF 0.4µF AGND 20, 29, 30, 48 DGND 4, 56, 57, 63, 66 = ANALOG GROUND = DIGITAL GROUND AVEE (-5.2V ANALOG) Figure 4. Typical Application 10 ______________________________________________________________________________________ 300Msps, 12-Bit DAC with Complementary Voltage Outputs 2 1 N.C. D7 3 DGND CLK 4 D6 DGND 5 DGND DVEE 6 D5 D3 7 TN D2 8 D4 D1 9 CLK BYPASS D0 (LSB) TOP VIEW 68 67 66 65 64 63 62 61 N.C. 10 60 N.C. 11 59 D9 N.C. 12 58 D10 D8 VOUT 13 57 DGND VOUT 14 56 DGND LGND 15 55 DVEE LGND 16 54 D11 (MSB) VOUT 17 53 TN VOUT 18 (TN) 19 AGND 20 50 LBIAS N.C. 21 49 TN N.C. 22 48 AGND N.C. 23 47 ALTCOMPC N.C. 24 46 N.C. MAX555 52 TN 51 TN 45 N.C. 26 44 HS N.C. ROFFSET N.C. N.C. VREF VREF N.C. N.C. AVEE VREF/2 AVEE LOOPCRNT N.C. AGND 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 AGND 27 N.C. 25 HS ALTCOMPIB N.C. PLCC ______________________________________________________________________________________ 11 MAX555 ____________________________________________________________Pin Configuration MAX555 300Msps, 12-Bit DAC with Complementary Voltage Outputs ________________________________________________________Package Information DIM A2 e C B1 D4 B D2 A A1 A2 A3 B B1 C e INCHES MAX MIN 0.180 0.165 0.120 0.090 0.156 0.145 – 0.020 0.021 0.013 0.032 0.026 0.011 0.009 0.050 DIM PINS A3 D3 D1 D A1 A Q PACKAGE PLASTIC LEADED CHIP CARRIER NOTES: 1. D1 DOES NOT INCLUDE MOLD FLASH 2. MOLD FLASH OR THE PROTRUSIONS NOT TO EXCEED .20mm (.008") PER SIDE 3. LEADS TO BE COPLANAR WITHIN .102mm (.004") 4. CONTROLLING DIMENSION: MILLIMETER 5. MEETS JEDEC MO047-XX AS SHOWN IN TABLE 6. N = NUMBER OF PINS 7. D4 APPLIES TO THERMALLY ENHANCED PACKAGES ONLY. 12 D D1 D2 D3 D D1 D2 D3 D4 D D1 D2 D3 D4 D D1 D2 D3 D4 20 28 44 68 INCHES MIN MAX 0.385 0.395 0.350 0.356 0.290 0.330 0.200 REF 0.485 0.495 0.450 0.456 0.390 0.430 0.300 REF 0.300 – 0.685 0.695 0.650 0.656 0.590 0.630 0.500 REF 0.470 – 0.985 0.995 0.950 0.958 0.890 0.930 0.800 REF 0.625 – ______________________________________________________________________________________ MILLIMETERS MIN MAX 4.19 4.57 2.29 3.05 3.68 3.96 0.51 – 0.33 0.53 0.66 0.81 0.23 0.28 1.27 MILLIMETERS MIN MAX 9.78 10.03 8.89 9.04 7.37 8.38 5.08 REF 12.32 12.57 11.43 11.58 9.91 10.92 7.62 REF 7.62 – 17.40 17.65 16.51 16.66 14.99 16.00 12.70 REF 11.94 – 25.02 25.27 24.13 24.33 22.61 23.62 20.32 REF 15.87 –