INTEGRATED CIRCUITS DATA SHEET UMA1020AM Low-voltage dual frequency synthesizer for radio telephones Product specification Supersedes data of November 1994 File under Integrated Circuits, IC03 1995 Jul 06 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM The principal synthesizer operates at RF input frequencies up to 1.7 GHz the auxiliary synthesizer operates at 300 MHz. The auxiliary loop is intended for the first IF or to transmit offset loop-frequency settings. Each synthesizer has a fully programmable reference divider. All divider ratios are supplied via a 3-wire serial programming bus. FEATURES • Low current from 3 V supply • Fully programmable RF divider • 3-line serial interface bus • Second synthesizer to control first IF or offset loop frequency Separate power and ground pins are provided to the analog and digital circuits. The ground leads should be externally short-circuited to prevent large currents flowing across the die and thus causing damage. Digital supplies VDD1 and VDD2 must also be at the same potential. VCC must be equal to or greater than VDD (i.e. VDD = 3 V and VCC = 5 V for wider tuning range). • Independent fully programmable reference dividers for each loop, driven from external crystal oscillator • Dual phase detector outputs to allow fast frequency switching • Dual power-down modes. The principal synthesizer phase detector uses two charge pumps, one provides normal loop feedback, while the other is only active during fast mode to speed-up switching. The auxiliary loop has a separate phase detector. All charge pump currents (gain) are fixed by an external resistance at pin ISET (pin 14). Only passive loop filters are used; the charge-pumps function within a wide voltage compliance range to improve the overall system performance. APPLICATIONS • 1 to 1.7 GHz mobile telephones • Portable battery-powered radio equipment. GENERAL DESCRIPTION The UMA1020AM BICMOS device integrates prescalers, programmable dividers, and phase comparators to implement two phase-locked loops. The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 5 V supplies. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. VCC, VDD supply voltage VCC ≥ VDD ICC + IDD principal synthesizer supply current auxiliary synthesizer in − power-down mode principal and auxiliary synthesizer supply current principal and auxiliary synthesizers ON TYP. MAX. UNIT − 5.5 V 9.4 − mA − 12.1 − mA 12 − µA 2.7 ICCPD, IDDPD current in power-down mode per supply − fVCO principal input frequency 1000 1500 1700 MHz fAI auxiliary input frequency 20 − 300 MHz fXTAL crystal reference input frequency 3 − 40 MHz fPPC principal phase comparator frequency − 200 − kHz fAPC auxiliary phase comparator frequency − 200 − kHz Tamb operating ambient temperature −30 − +85 °C ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UMA1020AM SSOP20 1995 Jul 06 DESCRIPTION plastic shrink small outline package; 20 leads; body width 4.4 mm 2 VERSION SOT266-1 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM BLOCK DIAGRAM Fig.1 Block diagram. 1995 Jul 06 3 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM PINNING SYMBOL PIN DESCRIPTION FAST 1 control input to speed-up main synthesizer CPPF 2 principal synthesizer speed-up charge-pump output CPP 3 principal synthesizer normal charge-pump output VDD1 4 digital power supply 1 VDD2 5 digital power supply 2 PRI 6 1.7 GHz principal synthesizer frequency input DGND 7 digital ground fXTAL 8 common crystal frequency input from TCXO POFF 9 principal synthesizer power-down input n.c. 10 not connected CLK 11 programming bus clock input DATA 12 programming bus data input E 13 programming bus enable input (active LOW) ISET 14 regulator pin to set the charge-pump currents AUX 15 auxiliary synthesizer frequency input AGND 16 analog ground CPA 17 auxiliary synthesizer charge-pump output VCC 18 supply for charge-pump AOFF 19 auxiliary synthesizer power-down input LOCK 20 in-lock detect output (main PLL); test mode output Fig.2 Pin configuration. The PRI input (pin 6) drives a preamplifier to provide the clock to the first divider stage. The preamplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from 100 mV to 500 mV (RMS), and at frequencies up to 1.7 GHz. The high frequency divider circuits use bipolar transistors, slower bits are CMOS. Divider ratios (512 to 131071) allow up to 2 MHz phase comparison frequency. FUNCTIONAL DESCRIPTION Principal synthesizer Programmable reference and main dividers drive the principal PLL phase detector. Two charge pumps produce phase error current pulses for integration in an external loop filter. A hardwired power-down input POFF (pin 9) ensures that the dividers and phase comparator circuits can be disabled. 1995 Jul 06 4 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM The reference and main divider outputs are connected to a phase/frequency detector that controls two charge pumps. The two pumps have a common bias-setting current that is set by an external resistance. The ratio between currents in fast and normal operating modes can be programmed via the 3-wire serial bus. The low current pump remains active except in power-down. The high current pump is enabled via the control input FAST (pin 1). By appropriate connection to the loop filter, dual bandwidth loops are provided: short time constant during frequency switching (FAST mode) to speed-up channel changes and low bandwidth in the settled state (on-frequency) to reduce noise and breakthrough levels. Serial programming bus A simple 3-line unidirectional serial bus is used to program the circuit. The 3 lines are DATA, CLK and E (enable). The data sent to the device is loaded in bursts framed by E. Programming clock edges and their appropriate data bits are ignored until E goes active LOW. The programmed information is loaded into the addressed latch when E returns inactive HIGH. Only the last 21 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new programmed data even during power-down of main and auxiliary loops. The principal synthesizer speed-up charge pump (CPPF) is controlled by the FAST input in synchronization with phase detector operation in such a way that potential disturbances are minimized. The dead zone (caused by finite time taken to switch the current sources on or off) is cancelled by feedback from the normal pump output to the phase detector thereby improving linearity. However when either principal synthesizer or auxiliary synthesizer or both are powered-on, the presence of a TCXO signal is required at pin 8 (fXTAL) for correct programming. Data format An open drain transistor drives the output pin LOCK (pin 20). It is recommended that the pull-up resistor from this pin to VDD is chosen such that the value is high enough to keep the sink current in the LOW state below 400 µA. The circuit can be programmed to output either the phase error in the principal or auxiliary phase detectors or the combination from both detectors (OR function). The resultant output will be a current pulse with the duration of the selected phase error. By appropriate external filtering and threshold comparison, an out-of-lock or an in-lock flag is generated. Data is entered with the most significant bit first. The leading bits make up the data field, while the trailing four bits are an address field. The UMA1020AM uses 5 of the 16 available addresses. The data format is shown in Table 1. The first entered bit is p1, the last bit is p21. The trailing address bits are decoded on the inactive edge of E. This produces an internal load pulse to store the data in one of the addressed latches. To ensure that the data is correctly loaded on first power-up, E should be held LOW and only taken HIGH after having programmed an appropriate register. To avoid erroneous divider ratios, the pulse is not allowed during data reads by the frequency dividers. Auxiliary synthesizer The auxiliary synthesizer has a 14-bit main divider and an 11-bit reference divider. A separate power-down input AOFF (pin 19), disables currents in the auxiliary dividers, phase detector, and charge pump. The auxiliary input signal is amplified and fed to the main divider. The input buffer presents a high impedance, dominated by pin and pad capacitance. First divider stages use bipolar technology operating at input frequencies up to 300 MHz; the slower bits are CMOS. The auxiliary loop phase detector and charge pump use similar circuits to the main loop low-current phase comparator, including dead-zone compensation feedback. This condition is guaranteed by respecting a minimum E pulse width after data transfer. The corresponding relationship between data fields and addresses is given in Table 2. The auxiliary reference divider is clocked on the opposite edge of the principal reference divider to ensure that active edges arrive at the auxiliary and principal phase detectors at different times. This minimizes the potential for interference between the charge pumps of each loop. 1995 Jul 06 5 LAST IN PROGRAMMING REGISTER BIT USAGE FIRST IN p21 p20 p19 p18 p17 p16 ../.. p2 p1 ADD0 ADD1 ADD2 ADD3 DATA0 DATA1 ../.. DATA15 DATA16 LATCH ADDRESS Table 2 LSB DATA COEFFICIENT Bit allocation (note 1) FT REGISTER BIT ALLOCATION p1 p2 p3 p4 p5 dt16 dt15 dt14 dt13 dt12 p6 p7 p8 p9 p10 p11 p12 DATA FIELD LT p13 p14 p15 p16 p17 dt4 dt2 dt1 dt3 X X X OLP OLA X X X X X X X X X AM13 X X X X PM16 CR1 CR0 X X sPOFF sAOFF X X X X PRINCIPAL MAIN DIVIDER COEFFICIENT PR10 PRINCIPAL REFERENCE DIVIDER COEFFICIENT AUXILIARY MAIN DIVIDER COEFFICIENT X X AR10 AUXILIARY REFERENCE DIVIDER COEFFICIENT p18 p19 dt0 TEST BITS(2) X MSB X p20 p21 ADDRESS 0 0 0 0 0 0 0 1 PM0 0 1 0 0 PR0 0 1 0 1 AM0 0 1 1 0 AR0 0 1 1 1 Philips Semiconductors Format of programmed data Low-voltage dual frequency synthesizer for radio telephones 1995 Jul 06 Table 1 6 Notes 1. FT = first, LT = last; sPOFF = software power-down for principal synthesizer (1 = OFF); sAOFF = software power-down for auxiliary synthesizer (1 = OFF). 2. The test register should not be programmed with any other value except all zeros for normal operation. Table 3 Out-of-lock select OLA OUT-OF-LOCK ON PIN 20 0 0 output disabled 0 1 auxiliary phase error 1 0 principal phase error 1 1 both auxiliary and principal Product specification UMA1020AM OLP Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones Table 4 UMA1020AM Fast and normal charge pumps current ratio (note 1) CR1 CR0 ICPA ICPP ICPPF ICPPF : ICPP 0 0 4 × ISET 4 × ISET 16 × ISET 4:1 0 1 4 × ISET 4 × ISET 32 × ISET 8:1 1 0 4 × ISET 2 × ISET 24 × ISET 12 : 1 1 1 4 × ISET 2 × ISET 32 × ISET 16 : 1 Note V 14 1. ISET = ----------- ; common bias current for charge pumps. R ext Table 5 Power-down modes AOFF POFF FAST PRINCIPAL DIVIDERS AUXILIARY DIVIDERS PUMP CPA PUMP CPP PUMP CPPF 1 1 X OFF OFF OFF OFF OFF 1 0 0 ON OFF OFF ON OFF 1 0 1 ON OFF OFF ON ON 0 1 X OFF ON ON OFF OFF 0 0 0 ON ON ON ON OFF 0 0 1 ON ON ON ON ON When either synthesizer is reactivated after power-down the main and reference dividers of that synthesizer are synchronized to avoid the possibility of random phase errors on power-up. Power-down modes The action of the control inputs on the state of internal blocks is defined by Table 5. Note that in Table 5, POFF and AOFF can be either the software or hardware power-down signals. The dividers are ON when both hardware and software power-down signals are at logic 0. 1995 Jul 06 7 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD digital supply voltage −0.3 +5.5 V VCC analog supply voltage −0.3 +5.5 V ∆VCC−DD difference in voltage between VCC and VDD −0.3 +5.5 V Vn voltage at pins 1, 6, 8 to 15, 19 and 20 −0.3 VDD + 0.3 V V2, 3, 17 voltage at pins 2, 3 and 17 −0.3 VCC + 0.3 V ∆VGND difference in voltage between AGND and DGND (these pins should be connected together) −0.3 +0.3 V Ptot total power dissipation − 150 mW Tstg storage temperature −55 +125 °C Tamb operating ambient temperature −30 +85 °C Tj maximum junction temperature − 95 °C HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1995 Jul 06 PARAMETER thermal resistance from junction to ambient in free air 8 VALUE UNIT 120 K/W Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM CHARACTERISTICS VDD1 = VDD2 = 2.7 to 5.5 V; VCC = 2.7 to 5.5 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply; pins 4, 5 and 18 VDD digital supply voltage VDD1 = VDD2 2.7 − 5.5 V VCC analog supply voltage VCC ≥ VDD 2.7 − 5.5 V IDD principal synthesizer digital supply current VDD = 5.5 V − 9 11 mA auxiliary synthesizer digital supply current VDD = 5.5 V − 2.7 4.0 mA charge pumps supply current VCC = 5.5 V; Rext =12 kΩ − 0.4 1.0 mA logic levels 0 or VDD − 12 50 µA 1000 1500 1700 MHz ICC ICCPD, IDDPD current in power-down mode per supply RF principal main divider input; pin 6 fVCO RF input frequency V6(rms) AC-coupled input signal level (RMS value) Rs = 50 Ω 100 − 500 mV ZI input impedance (real part) fVCO = 1.7 GHz − 300 − Ω CI typical pin input capacitance indicative, not tested − 2 − pF Rpm principal main divider ratio 512 − 131071 fPPCmax maximum principal phase comparator frequency − 2000 − kHz fPPCmin minimum principal phase comparator frequency − 10 − kHz 20 − 300 MHz Rs = 50 Ω; 2.7 V < VDD < 3.5 V 50 − 500 mV Rs = 50 Ω; 3.5 V < VDD < 5.5 V 100 − 500 mV Auxiliary main divider input; pin 15 fAI input frequency V15(rms) AC-coupled input signal level (RMS value) ZI input impedance (real part) fAI = 100 MHz − 1 − kΩ CI typical pin input capacitance indicative, not tested − 2 − pF Ram auxiliary main divider ratio 64 − 16383 fAPCmax maximum auxiliary loop comparison frequency − 2000 − kHz fAPCmin minimum auxiliary loop comparison frequency − 10 − kHz 1995 Jul 06 9 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones SYMBOL UMA1020AM PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Crystal reference dividers input; pin 8 fXTAL crystal reference input frequency V8(rms) sinusoidal input signal level (RMS value) − 40 MHz 5 MHz < fXTAL < 40 MHz 50 − 500 mV 3 MHz < fXTAL < 40 MHz 100 − 500 mV 3 ZI input impedance (real part) fXTAL = 30 MHz − 2 − kΩ CI typical pin input capacitance indicative, not tested − 2 − pF Rpr principal reference divider ratio 8 − 2047 Rar auxiliary reference divider ratio 8 − 2047 12 − 60 kΩ − 1.15 − V −25 − +25 % Charge pump current setting resistor input; pin 14 Rext external resistor from pin 14 to ground V14 regulated voltage at pin 14 Rext = 12 kΩ Charge pump outputs; pins 17, 3 and 2; Rext = 12 kΩ IOcp charge pump output current error Imatch sink-to-source current matching Vcp in range − ±5 − % ILcp charge pump off leakage current Vcp = 1⁄2VCC −5 ±1 +5 nA Vcp charge pump voltage compliance 0.4 − VCC − 0.4 V Interface logic input signal levels; pins 13, 12, 11 and 1 VIH HIGH level input voltage 0.7VDD − VDD + 0.3 V VIL LOW level input voltage −0.3 − 0.3VDD Ibias input bias current logic 1 or logic 0 −5 − +5 µA CI input capacitance indicative, not tested − 2 − pF − − 0.4 V V Lock detect output signal; pin 20 open-drain output VOL 1995 Jul 06 LOW level output voltage Isink = 0.4 mA 10 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM SERIAL BUS TIMING CHARACTERISTICS VDD = VCC = 3 V; Tamb = 25 °C unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT Serial programming clock; CLK tr input rise time − 10 40 ns tf input fall time − 10 40 ns Tcy clock period 100 − − ns Enable programming; E tSTART delay to rising clock edge 40 − − ns tEND delay from last falling clock edge −20 − − ns tW minimum inactive pulse width 4000(1) − − ns tSU;E enable set-up time to next clock edge 20 − − ns Register serial input data; DATA tSU;DAT input data to clock set-up time 20 − − ns tHD;DAT input data to clock hold time 20 − − ns Note 1. The minimum pulse width (tW) can be smaller than 4 µs provided all the following conditions are satisfied: 512 a) Principal main divider input frequency f VCO > ---------tW 32 b) Auxiliary main divider input frequency f AI > -----tW 3 c) Reference dividers input frequency f XTAL > -----tW Fig.3 Serial bus timing diagram. 1995 Jul 06 11 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM APPLICATION INFORMATION Fig.4 Typical application block diagram. 1995 Jul 06 12 BBBBBBBBBBBBBBB BBBBBBBBBBBBB BB B B B B B B B B B BBBBBBBBB B B B B B B B B B B B B BBBBBBBBB B B B B B B B B B B BBBBBBBBBB B BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB B BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB B B B B B B B B B B B B B B B B B B BBBBBBBBBBBBBBBBBBBB BB B BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB B BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB B 13 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBB BBBBBBBBB BBBBBBBBBBBBB BB B BB BB BBBBBBBBB B B BBB BB BB BB B BBBBBBBBB B B B BB B B B B BB BB BB BB BB B BBBBBBBBBBBBB B BBBBBB B Philips Semiconductors Low-voltage dual frequency synthesizer for radio telephones 1995 Jul 06 Product specification UMA1020AM Fig.5 Typical test and application diagram. Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM PACKAGE OUTLINE SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm D SOT266-1 E A X c y HE v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0 1.4 1.2 0.25 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 90-04-05 95-02-25 SOT266-1 1995 Jul 06 EUROPEAN PROJECTION 14 o Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM SOLDERING SO or SSOP SSOP Introduction Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these cases reflow soldering is often used. If wave soldering cannot be avoided, the following conditions must be observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Reflow soldering Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. METHOD (SO OR SSOP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering SO Repairing soldered joints Wave soldering techniques can be used for all SO packages if the following conditions are observed: Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds at 270 to 320 °C. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. 1995 Jul 06 15 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1995 Jul 06 16 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM NOTES 1995 Jul 06 17 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM NOTES 1995 Jul 06 18 Philips Semiconductors Product specification Low-voltage dual frequency synthesizer for radio telephones UMA1020AM NOTES 1995 Jul 06 19 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. 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(0212)282 67 07 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601 Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 (from 10-10-1995: +31-40-2724825) SCD41 © Philips Electronics N.V. 1995 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 413061/1500/02/pp20 Document order number: Date of release: 1995 Jul 06 9397 750 00194