MAXIM MAX1117EKA

19-1857; Rev 0; 11/00
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
The full-scale analog input range is determined by the
internal reference of +2.048V (MAX1117) or +4.096V
(MAX1119), or by an externally applied reference ranging from +1V to VDD (MAX1118). All devices feature an
automatic shutdown mode that reduces supply current
to <1µA when the device is not in use. The 3-wire serial
interface directly connects to SPI™, QSPI™, and
MICROWIRE™ devices without external logic.
Conversions up to 100ksps are performed using an
internal clock.
The MAX1117/MAX1118/MAX1119 are available in an
8-pin SOT23 package with a footprint that is only 11%
of an 8-pin plastic DIP.
Features
♦ Single Supply
+2.7V to +3.6V (MAX1117)
+2.7V to +5.5V (MAX1118)
+4.5V to +5.5V (MAX1119)
♦ Internal Track/Hold: 100kHz Sampling Rate
♦ Internal Reference
+2.048V (MAX1117)
+4.096V (MAX1119)
♦ Reference Input Range: 0 to VDD (MAX1118)
♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface
♦ Small 8-Pin SOT23 Package
♦ Automatic Power-Down
♦ Analog Input Range: 0 to VREF
♦ Low Power
175µA at 100ksps (typ) (MAX1117/MAX1119)
135µA at 100ksps (typ) (MAX1118)
18µA at 10ksps (typ)
1µA (typ) in Power-Down Mode
________________________Applications
Ordering Information
Low-Power, Handheld Portable Devices
PART
TEMP. RANGE
PINPACKAGE
TOP
MARK
Battery-Powered Test Equipment
MA X1 11 7EKA
-40°C to +85°C
8 SOT23
AADW
Solar-Powered Remote Systems
MA X1 11 8EKA
-40°C to +85°C
8 SOT23
AADX
Receive Signal Strength Indicators
MA X1 11 9EKA
-40°C to +85°C
8 SOT23
AADY
System Diagnostics
4mA to 20mA Powered Remote Data Acquisition
Systems
Pin Configuration
TOP VIEW
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor, Corp.
VDD 1
CHO
2
CH1
3
GND
4
MAX1117
MAX1118
MAX1119
8
SCLK
7
DOUT
6
CNVST
5
(REF) I.C
Functional Diagram appears at end of data sheet.
SOT23
( ) ARE FOR MAX1118 ONLY
________________________________________________________________ Maxim Integrated Products
1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1117/MAX1118/MAX1119
General Description
The MAX1117/MAX1118/MAX1119 low-power, 8-bit,
dual-channel, analog-to-digital converters (ADCs) feature an internal track/hold (T/H) voltage reference
(MAX1117/MAX1119), clock, and serial interface. The
MAX1118 is specified from +2.7V to +5.5V and consumes only 135µA at 100ksps. The MAX1117 is specified from +2.7V to +3.6V, and the MAX1119 is specified
from +4.5V to +5.5V, each consumes only 175µA at
100ksps.
MAX1117/MAX1118/MAX1119
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +6.0V
CH0,CH1, REF to GND...............................-0.3V to (VDD + 0.3V)
Digital Output to GND ................................-0.3V to (VDD + 0.3V)
Digital Input to GND ..............................................-0.3V to +6.0V
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin SOT23 (derate 8.9mW/°C above +70°C)............714mW
Operating Temperature Range
MAX1117EKA ..................................................-40°C to + 85°C
MAX1118EKA ..................................................-40°C to + 85°C
MAX1119EKA ..................................................-40°C to + 85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX1117), VDD = +4.5V to +5.5V (MAX1119), VDD = REF = +2.7V to +5.5V (MAX1118),TA = TMIN to TMAX,
unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±1
LSB
±1
LSB
DC ACCURACY
8
Resolution
Relative Accuracy (Note 1)
INL
Differential Nonlinearity
DNL
Bits
±0.5
LSB
MAX1118, REF = VDD
±1
LSB
MAX1117/MAX1119
±5
%FSR
Offset Error
Gain Error
Gain Temperature Coefficient
Total Unadjusted Error
TUE
MAX1118
±5
MAX1117/MAX1119
±90
MAX1118
±0.5
Channel-to-Channnel Offset
Matching
ppm/°C
±1
±0.1
LSB
LSB
DYNAMIC PERFORMANCE (25kHz sinewave input, VIN = VREF(pp), fSCLK = 5MHz, fsample = 100ksps, RIN = 100Ω)
48
Signal-to-Noise Plus Distortion
SINAD
dB
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
-69
Spurious-Free Dynamic Range
SFDR
66
dB
Small Signal Bandwidth
f-3dB
4
MHz
dB
ANALOG INPUT
Input Voltage Range
0
Input Leakage
Current
Input Capacitance
VCH_ = 0 or VDD
±0.7
18
CIN
VREF
V
±10
µA
pF
INTERNAL REFERENCE
Voltage
2
VREF
MAX1117
2.048
MAX1119
4.096
_______________________________________________________________________________________
V
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
(VDD = +2.7V to +3.6V (MAX1117), VDD = +4.5V to +5.5V (MAX1119), VDD = REF = +2.7V to +5.5V (MAX1118),TA = TMIN to TMAX,
unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
10
VDD
20
µA
MAX1117
2.7
2.7
5.5
5.5
V
MAX1119
4.5
5.5
EXTERNAL REFERENCE (MAX1118 ONLY)
Input Voltage Range
1.0
Input Current
Ave, VDD = REF = +5.5V at 100ksps
POWER REQUIREMENTS
MAX1118
Supply Voltage
VDD
Supply Current (Note 2)
Supply Rejection Ratio
IDD
PSRR
MAX1119, fSAMPLE = 100ksps,
zero-scale input
182
230
MAX1117/MAX1118, fSAMPLE = 100ksps,
zero-scale input
135
190
MAX1119, fSAMPLE = 10ksps,
zero-scale input
19
25
MAX1117/MAX1118, fSAMPLE = 10ksps,
zero-scale input
14
21
Shutdown
0.8
10
Full-scale or 0 input
±0.5
±1
µA
LSB/V
DIGITAL INPUTS (CNVST AND SCLK)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hystersis
2
V
0.8
0.2
VHYST
V
Input Current High
IIH
±10
Input Current Low
IIL
±10
Input Capacitance
DIGITAL OUTPUT (DOUT)
CIN
Output High Voltage
VOH
Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
VOL
2
ISOURCE = 2mA
V
µA
µA
pF
VDD - 0.5
V
ISINK = 2mA
0.4
ISINK = 4mA
0.8
V
±10
µA
IL
±0.01
COUT
4
V
pF
TIMING CHARACTERISTICS (Figures 6a–6d)
CNVST High Time
tcsh
100
ns
CNVST Low Time
tcsi
100
ns
Conversion Time
tconv
7.5
µs
Serial Clock High Time
tch
75
ns
Serial Clock Low Time
tcl
75
ns
Serial Clock Period
tcp
200
Falling of CNVST to DOUT Active
tcsd
CLOAD = 100pF, Figure 1
ns
100
ns
_______________________________________________________________________________________
3
MAX1117/MAX1118/MAX1119
ELECTRICAL CHARACTERISTICS (continued)
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX1117), VDD = +4.5V to +5.5V (MAX1119), VDD = REF = +2.7V to +5.5V (MAX1118),TA = TMIN to TMAX,
unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Serial Clock Falling Edge to
DOUT
tcd
CLOAD = 100pF
Serial Clock Rising Edge to
DOUT High-Z
tchz
CLOAD = 100pF, Figure 2
Last Serial Clock to Next CNVST
(Successive Conversions on
CH0)
tccs
MIN
TYP
MAX
10
100
100
500
UNITS
ns
ns
50
ns
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated.
Note 2: Input = 0, with logic input levels of 0 and VDD.
Typical Operating Characteristics
(VDD = +3V (MAX1117), VDD = +5V (MAX1119), VDD = VREF = +3V (MAX1118), fSCLK = 5MHz, fSAMPLE = 100ksps, CLOAD = 100pF,
TA = +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
vs.OUTPUT CODE
0.4
0.6
0.4
DNL (LSB)
0.2
0.8
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
0.6
0
50
100
150
200
250
0.4
0.3
0.2
0
0
300
0.5
0.1
-1.0
-1.0
50
100
150
200
250
300
OUTPUT CODE
OUTPUT CODE
3.5
4.5
SUPPLY VOLTAGE (V)
MAX1118
SUPPLY CURRENT vs. CONVERSION RATE
MAX1118
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1118 SUPPLY CURRENT
vs. TEMPERATURE
VDD = +5V
VDD = +3V
1.0
120
110
80
60
40
0.01
0.1
1
10
CONVERSION (ksps)
100
VDD = +5V
100
VDD = +3V
50
DOUT = 00000000
VDD = VREF = VDIGITAL INPUTS
0
0.1
150
DOUT = 00000000
VDD = VREF = VDIGITAL INPUTS
20
5.5
MAX1117/18/19 toc06
140
2.5
SUPPLY CURRENT (µA)
10.0
160
MAX1117/18/19 toc05
VDD = VREF = VDIGITAL
SUPPLY CURRENT (µA)
MAX1117/18/19 toc04
100.0
4
0.7
MAX1117/18/19 toc03
0.6
MAX1117/18/19 toc02
0.8
INL (LSB)
1.0
MAX1117/18/19 toc01
1.0
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT (µA)
INTEGRAL NONLINEARITY
vs.OUTPUT CODE
SUPPLY CURRENT (µA)
MAX1117/MAX1118/MAX1119
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
0
2.5
3.5
4.5
SUPPLY VOLTAGE (V)
5.5
-40
-15
10
35
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
MAX1117/MAX1119 SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1117
VDD = +3V
10
3.5
4.5
CONVERSION (ksps)
SUPPLY VOLTAGE (V)
CONVERSION TIME
vs. SUPPLY VOLTAGE
CONVERSION TIME
vs. TEMPERATURE
5.2
5.5
VDD = +3V
4.5
MAX1117/18/19 toc09
85
5.3
5.2
40k
50k
-40
-60
-80
VDD = +5V
-100
5.5
-120
-40
-15
10
35
60
0
85
10k
20k
30k
TEMPERATURE (°C)
ANALOG INPUT FREQUENCY (Hz)
MAX1118
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1118
GAIN ERROR vs. TEMPERATURE
MAX1118
GAIN ERROR vs. REFERENCE VOLTAGE
0.3
0
0.2
0.1
0
-0.1
VDD = +5.5V
-0.2
GAIN ERROR (LSB)
GAIN ERROR (LSB)
0.2
VDD = +3V
VREF = 2.048V
0.4
0
MAX1117/18/19 toc15
MAX1117/18/19 toc14
0.5
MAX1117/18/19 toc16
SUPPLY VOLTAGE (V)
VREF = 2.048V
0.4
60
-20
5.0
3.5
35
0
5.1
2.5
10
FFT PLOT
5.4
5.0
-15
TEMPERATURE (V)
5.5
5.1
DOUT = 00000000
VDD = VDIGITAL INPUTS
-40
AMPLITUDE (dB)
MAX1117/18/19 toc11
5.3
MAX1117
VDD = +3V
100
0
2.5
100
MAX1119
VDD = +5V
150
50
DOUT = 00000000
VDD = VDIGITAL INPUTS
MAX1117/18/19 toc12
1
5.4
CONVERSION TIME (µs)
MAX1117
0
0.1
5.5
GAIN ERROR (LSB)
100
50
CONVERSION TIME (µs)
0.1
0.01
MAX1119
MAX1117/18/19 toc13
1.0
150
200
SUPPLY CURRENT (µA)
MAX1119
VDD = +5V
10.0
200
SUPPLY CURRENT (µA)
MAX1117/18/19 toc07
SUPPLY CURRENT (µA)
100.0
MAX1117/MAX1119
SUPPLY CURRENT vs. TEMPERATURE
MAX1117/18/19 toc08
MAX1117/MAX1119
SUPPLY CURRENT vs. CONVERSION RATE
-0.4
-0.6
-0.2
-0.2
-0.8
-0.3
-0.4
-0.4
-1.0
-0.5
2.5
3.5
4.5
SUPPLY VOLTAGE (V)
5.5
-40
-15
10
35
TEMPERATURE (°C)
60
85
1
2
3
4
5
REFERENCE VOLTAGE (V)
_______________________________________________________________________________________
5
MAX1117/MAX1118/MAX1119
Typical Operating Characteristics (continued)
(VDD = +3V (MAX1117), VDD = +5V (MAX1119), VDD = VREF = +3V (MAX1118), fSCLK = 5MHz, fSAMPLE = 100ksps, CLOAD = 100pF,
TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = +3V (MAX1117), VDD = +5V (MAX1119), VDD = VREF = +3V (MAX1118), fSCLK = 5MHz, fSAMPLE = 100ksps, CLOAD = 100pF,
TA = +25°C, unless otherwise noted.)
-0.1
-0.2
0.1
0
-0.1
-0.2
0.2
0.1
0
-0.1
-0.2
-0.3
-0.3
-0.3
-0.4
-0.4
-0.4
-0.5
-0.5
3.0
3.5
4.0
4.5
5.0
-15
10
35
60
TEMPERATURE (°C)
MAX1117/MAX1119
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1117/MAX1119
GAIN ERROR vs. TEMPERATURE
MAX1117
VDD = +3V
MAX1119
VDD = +5V
0.8
0.6
0.4
MAX1116
VDD = +5V
1.5
1.0
3
4
5
FFT PLOT
0
fSAMPLE = 100kHz
fIN = 25.1kHz
AIN = 0.9 x VREFp-p
-20
0.5
MAX1117
VDD = +3V
0
2
REFERENCE VOLTAGE (V)
AMPLITUDE (dB)
MAX1117/18/19 toc20
1.2
2.0
1
85
SUPPLY VOLTAGE (V)
1.4
1.0
-0.5
-40
5.5
MAX1117/18/19 toc21
2.5
-0.5
-40
-60
-80
-1.0
0.2
-100
-1.5
0
-120
-2.0
3.5
4.5
5.5
-40
-15
10
SUPPLY VOLTAGE (V)
35
60
OFFSET ERROR (LSB)
MAX1117
VDD = +3V
MAX1119
VDD = +5V
0.1
0
-0.1
-0.2
0.5
0.4
0.3
OFFSET ERROR (LSB)
0.4
20k
MAX1117/MAX1119
OFFSET ERROR vs. TEMPERATURE
MAX1117/18/19 toc23
0.5
0.2
10k
MAX1117
VDD = +3V
0.2
0.1
0
-0.1
-0.2
-0.3
-0.3
-0.4
-0.4
MAX1119
VDD = +5V
-0.5
-0.5
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
-40
30k
40k
ANALOG INPUT FREQUENCY (Hz)
TEMPERATURE (°C)
MAX1117/MAX1119
OFFSET ERROR vs. SUPPLY VOLTAGE
0.3
0
85
MAX1117/18/19 toc24
2.5
6
0.3
MAX1117/18/19 toc22
0
0.2
VDD = 5.5V
0.4
OFFSET ERROR (LSB)
0.3
0.1
0.5
MAX1117/18/19 toc18
0.2
GAIN ERROR (%FSR)
OFFSET ERROR (LSB)
0.3
VDD = +3V
VREF = 2.048V
0.4
OFFSET ERROR (LSB)
VREF = 2.048V
0.4
0.5
MAX1117/18/19 toc17
0.5
MAX1118
OFFSET ERROR vs. REFERENCE VOLTAGE
MAX1117/18/19 toc19
MAX1118
OFFSET ERROR vs. TEMPERATURE
MAX1118
OFFSET ERROR vs. SUPPLY VOLTAGE
GAIN ERROR (%FSR)
MAX1117/MAX1118/MAX1119
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
50k
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
REFERENCE VOLTAGE vs.
NUMBER OF PIECES
REFERENCE VOLTAGE vs.
NUMBER OF PIECES
17.5%
21.0%
17.5%
14.0%
14.0%
10.5%
10.5%
7.0%
7.0%
3.5%
3.5%
0
3.980
4.020
4.060
4.100
4.140
4.180
MAX1117/18/19 toc26
MAX1115 toc25
21.0%
0
1.982
2.008
2.034
2.060
2.086
2.112
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
Pin Description
PIN
NAME
1
VDD
Positive Supply Voltage
FUNCTION
2
CH0
CH0 Analog Voltage Input
3
CH1
CH1 Analog Voltage Input
4
GND
Ground
5
I.C.(REF)
6
CNVST
Convert/Start Input. CNVST initiates a power-up and starts a conversion on its falling edge.
7
DOUT
Serial Data Output. Data is clocked out on the falling edge of SCLK. DOUT goes low at the start of a
conversion and presents the MSB at the completion of a conversion. DOUT goes high impedance
once data has been fully clocked out.
8
SCLK
Serial Clock. Used for clocking out data on DOUT.
Internally Connected. Connect to ground. (Reference Input, MAX1118 only.)
_______________________________________________________________________________________
7
MAX1117/MAX1118/MAX1119
Typical Operating Characteristics (continued)
(VDD = +3V (MAX1117), VDD = +5V (MAX1119), VDD = VREF = +3V (MAX1118), fSCLK = 5MHz, fSAMPLE = 100ksps, CLOAD = 100pF,
TA = +25°C, unless otherwise noted.)
MAX1117/MAX1118/MAX1119
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
VDD
VDD
3kΩ
DOUT
DOUT
3kΩ
GND
GND
VDD
1µF
GND
CPU
MAX1117
MAX1118
MAX1119
REF*
CAPACITIVE DAC
VDD
VDD
ANALOG
INPUTS
b) VOL TO HIGH-Z
Figure 2. Load Circuits for Disable Time
Figure 1. Load Circuits for Enable Time
0.1µF
GND
a) VOH TO HIGH-Z
b) HIGH-Z to VOL AND VOH to VOL
CH0
CLOAD
CLOAD
GND
GND
a) VOL TO VOH
DOUT
3kΩ
CLOAD
CLOAD
CH1
3kΩ
DOUT
CH0
CHOLD
16pF
COMPARATOR
CH1
CNVST
SCLK
RIN
6.5kΩ
I/O
SCK (SK)
1µF
DOUT
HOLD
TRACK
MISO (SI)
GND
AUTOZERO
RAIL
* MAX1118 ONLY
Figure 3. Typical Operating Circuit
Detailed Description
The MAX1117/MAX1118/MAX1119 ADCs use a successive-approximation conversion technique and input
T/H circuitry to convert an analog signal to an 8-bit digital output. The SPI/QSPI/MICROWIRE compatible interface directly connects to microprocessors (µPs) without
additional circuity (Figure 3).
Track/Hold
The input architecture of the ADC is illustrated in Figure
4’s equivalent-input circuit and is composed of the T/H,
the input multiplexer, the input comparator, the
switched capacitor DAC, and the auto-zero rail.
The acquisition interval begins with the falling edge of
CNVST. During the acquisition interval, the analog
8
Figure 4. Equivalent Input Circuit
inputs (CH0, CH1) are connected to the holding capacitor (CHOLD). Once the acquisition has completed, the
T/H switch opens and CHOLD is connected to GND,
retaining the charge on CHOLD as a sample of the signal at the analog input.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance <1.5kΩ is
recommended for accurate sample settling. A 100pF
capacitor at the ADC inputs will also improve the accuracy of an input sample.
Conversion Process
The MAX1117/MAX1118/MAX1119 conversion process
is internally timed. The total acquisition and conversion
process takes <7.5µs. Once an input sample has been
acquired, the comparator’s negative input is then con-
_______________________________________________________________________________________
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
Input Voltage Range
Internal protection diodes that clamp the analog input
to VDD and GND allow the input pins (CH0, CH1) to
swing from (GND - 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions, the inputs
must not exceed (VDD + 50mV) or be less than (GND 50mV).
be brought high for at least 50ns, then brought low to
initiate a conversion. To select CH1 for conversion, the
CNVST pin must be brought high and low for a second
time (Figures 6c and 6d).
After CNVST is brought low, allow 7.5µs for the conversion to be completed. While the internal conversion is in
progress, DOUT is low. The MSB is present at the
DOUT pin immediately after conversion is completed.
The conversion result is clocked out at the DOUT pin
and is coded in straight binary (Figure 7). Data is
clocked out at SCLK’s falling edge in MSB-first format
at rates up to 5MHz. Once all data bits are clocked
out, DOUT goes high impedance (100ns to 500ns after
the rising edge) of the eighth SCLK pulse.
Input Bandwidth
The ADC’s input tracking circuitry has a 4MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
I/O
CNVST
SCK
SCLK
MISO
DOUT
+3V
SS
Serial Interface
The MAX1117/MAX1118/MAX1119 have a 3-wire serial
interface. The CNVST and SCLK inputs are used to
control the device, while the three-state DOUT pin is
used to access the conversion results.
The serial interface provides connection to microcontrollers (µCs) with SPI, QSPI, and MICROWIRE serial
interfaces at clock rates up to 5MHz. The interface supports either an idle high or low SCLK format. For SPI
and QSPI, set CPOL = CPHA = 0 or CPOL = CPHA = 1
in the SPI control registers of the µC. Figure 5 shows
the MAX1117/MAX1118/MAX1119 common serial-interface connections. See Figures 6a–6d for details on the
serial interface timing and protocol.
a) SPI
CS
CNVST
SCK
SCLK
MISO
DOUT
+3V
SS
MAX1117
MAX1118
MAX1119
b) QSPI
Digital Inputs and Outputs
The MAX1117/MAX1118/MAX1119 perform conversions using an internal clock. This frees the µP from the
burden of running the SAR conversion clock and allows
the conversion results to be read back at the µP’s convenience at any clock rate up to 5MHz.
The acquisition interval begins with the falling edge of
CNVST. CNVST can idle between conversions in either
a high or low state. If idled in a low state, CNVST must
MAX1117
MAX1118
MAX1119
I/O
CNVST
SK
SCLK
SI
DOUT
MAX1117
MAX1118
MAX1119
c) MICROWIRE
Figure 5. Common Serial-Interface Connections
_______________________________________________________________________________________
9
MAX1117/MAX1118/MAX1119
nected to an autozero supply. Since the device
requires only a single supply, the negative input of the
comparator is set to equal VDD/2. The capacitive DAC
restores the positive input to VDD/2 within the limits of 8bit resolution. This action is equivalent to transferring a
charge QIN = 16pF x VIN from CHOLD to the binaryweighted capacitive DAC, which in turn forms a digital
representation of the analog-input signal.
MAX1117/MAX1118/MAX1119
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
ACTIVE
POWER-DOWN MODE
tcsh
CH0
CNVST
CH0
tconv
tch
tcp
tccs
IDLE LOW
SCLK
IDLE LOW
tcd
tcsd
DOUT
D7 (MSB)
tcl
D6
D5
D4
tchz
D3
D2
D1
D0
Figure 6a. Conversion and Interface Timing, Conversion on CH0 with SCLK Idle Low
ACTIVE
POWER-DOWN MODE
tcsh
CH0
CNVST
CH0
tconv
tch
tcp
tccs
SCLK IDLE HIGH
IDLE HIGH
tcsd
DOUT
tcd
D7 (MSB)
tcl
D6
D5
D4
tchz
D3
D2
D1
D0
Figure 6b. Conversion and Interface Timing, Conversion on CH0 with SCLK Idle High
During the conversion process, SCLK is ignored. Only
after a conversion is complete will SCLK cause serial
data to be output. Falling edges on CNVST, during an
active conversion process, interrupt the current conversion and cause the input multiplexer to switch to CH1.
To reinitiate a conversion on CH0, it is necessary to
allow for a conversion to be complete and all of the
data to be read out. Once a conversion has been completed, the MAX1117/MAX1118/MAX1119 will go into
AutoShutdown™ mode (<1µA typ) until the next conversion is initiated.
AutoShutdown is a trademark of Maxim Integrated Products.
10
______________________________________________________________________________________
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
MAX1117/MAX1118/MAX1119
ACTIVE
POWER-DOWN MODE
tcsl
tcsh
CH0
CH1
CH0
CH1
CNVST
tch
tconv
tcp
tccs
IDLE LOW
SCLK
IDLE LOW
tcd
tcsd
DOUT
D7 (MSB)
tcl
D6
D5
D4
tchz
D3
D2
D1
D0
Figure 6c. Conversion and Interface Timing, Conversion on CH1 with SCLK Idle Low
ACTIVE
POWER-DOWN MODE
tcsl
tcsh
CH0
CH1
CH0
CH1
CNVST
tch
tconv
SCLK
tcsd
DOUT
tcp
tccs
IDLE HIGH
IDLE HIGH
tcd
D7 (MSB)
tcl
D6
D5
D4
tchz
D3
D2
D1
D0
Figure 6d. Conversion and Interface Timing, Conversion on CH1 with SCLK Idle High
______________________________________________________________________________________
11
MAX1117/MAX1118/MAX1119
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
OUTPUT CODE
FULL-SCALE
TRANSITION
SYSTEM POWER SUPPLIES
11111111
11111110
GND
+3V/+5V
11111101
FS = VREF
1LSB = VREF
256
1µF
10Ω*
0.1µF
00000011
GND
00000010
00000001
MAX1117
MAX1118
MAX1119
00000000
0
1
2
3
FS
INPUT VOLTAGE (LSB)
FS - 1 1/2 LSB
Figure 7. Input/Output Transfer Function
Applications Information
Power-On Reset
When power is first applied, the MAX1117/MAX1118/
MAX1119 are in AutoShutdown state (<1µA typ). A conversion can be started by toggling CNVST high to low. Powering
up the MAX1117/MAX1118/MAX1119 with CNVST low will
not start a conversion. Conversions initiated prior to the
external reference settling (MAX1118) will result in errors.
Thus, it is necessary to allow the external reference to stabilize prior to initiating a conversion.
AutoShutDown and Supply Current
Requirements
The MAX1117/MAX1118/MAX1119 are designed to
automatically shutdown once a conversion is complete
without any external control. An input sample and conversion process will typically take 5µs to complete, during which time the supply current to the analog
sections of the device is fully on. All analog circuitry is
shutdown after a conversion completes, which results
in a supply current of <1µA (see Shutdown Current vs.
Supply Voltage Plot in the Typical Operating
Characteristics). The digital conversion result is maintained in a static register and is available for access
through the serial interface at any time.
The power consumption consequence of this architecture is dramatic when relatively slow conversion rates
are needed. For example, at a conversion rate of
10ksps, the average supply current for the MAX1117 is
12
VDD
DGND
VDD
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 8. Power-Supply Connections
15µA, while at 1ksps it drops to 1.5µA and at 0.1ksps it
is just 0.3µA, or a miniscule 1µW of power consumption
(see Average Supply Current vs. Conversion Rate Plot
in the Typical Operating Characteristics).
External Voltage Reference (MAX1118)
Connect an external reference between +1V and VDD
at the REF pin. The DC input impedance at REF is
extremely high, consisting of leakage current only
(10nA typ). During a conversion, the reference must be
able to deliver up to 20µA average load current and
have an output impedance of 100Ω or less. If the reference has higher output impedance or is noisy, bypass
it close to the REF pin with a 10nF or larger capacitor.
Transfer Function
Figure 7 depicts the input/output transfer function.
Output coding is binary with a +2.048V reference 1LSB
= 8mV (VREF/256).
Layout, Grounding, Bypassing
For best performance, the board layout should ensure
that digital and analog signal lines are separated from
each other. Do not run analog and digital (especially
clock) lines parallel to one another or run digital lines
underneath the ADC package.
Figure 8 shows the recommended system-ground connections. A single-point analog ground (star-ground
point) should be established at the ADC ground.
Connect all analog grounds to the star ground. The
ground return to the power supply for the star ground
______________________________________________________________________________________
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
SCLK
CNVST
VDD
CONTROL
LOGIC AND
INTERNAL
OCSILLATOR
GND
CH0
INPUT
MULTIPLEXER
CH1
INPUT
TRACK
AND HOLD
INTERNAL
REFERENCE
+2.096V
OR +4.096V
8-BIT
SAR
ADC
OUTPUT
SHIFT
REGISTER
OUT
MAX1117
MAX1119
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the VDD power supply may
affect the comparator in the ADC. Bypass the supply to
the star ground with a 0.1µF capacitor close to the VDD
pin of the MAX1117/MAX1118/MAX1119. Minimize
capacitor lead lengths for best supply-noise rejection. If
the power supply is noisy, a 1µF capacitor in conjunction with a 10Ω series resistor can be connected to
form a lowpass filter.
Chip Information
TRANSISTOR COUNT: 2000
PROCESS: BiCMOS
______________________________________________________________________________________
13
MAX1117/MAX1118/MAX1119
Functional Diagrams
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
SOT23, 8L.EPS
MAX1117/MAX1118/MAX1119
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.