MAXIM MAX1284

19-1687; Rev 1; 7/00
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
____________________________Features
♦ Single-Supply Operation
+4.5V to +5.5V (MAX1284)
+2.7V to +3.6V (MAX1285)
♦ ±1LSB (max) DNL, ±1LSB (max) INL
♦ 400ksps Sampling Rate (MAX1284)
♦ Internal Track/Hold
♦ +2.5V Internal Reference
♦ Low Power: 2.5mA (400ksps)
♦ SPI/QSPI/MICROWIRE 3-Wire Serial-Interface
♦ Pin-Compatible, High-Speed Upgrades to
MAX1240/MAX1241
♦ 8-Pin SO Package
Ordering Information
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
PART
TEMP.
RANGE
PINSUPPLY
PACKAGE VOLTAGE (V)
MAX1284BCSA
0°C to +70°C
8 SO
5
MAX1284BESA* -40°C to +85°C 8 SO
MAX1285BCSA
0°C to +70°C
5
8 SO
2.7 to 3.6
MAX1285BESA -40°C to +85°C 8 SO
*Future product—contact factory for availability.
Pen Digitizers
Process Control
Pin Configuration
2.7 to 3.6
Functional Diagram
VDD
1
TOP VIEW
VDD
1
8
SCLK
AIN
2
7
CS
6
DOUT
5
GND
SHDN 3
MAX1284
MAX1285
REF 4
CS
SCLK
SHDN
SO
AIN
8
3
2
INT
CLOCK
CONTROL
LOGIC
T/H
REF
OUTPUT
SHIFT
REGISTER
6
DOUT
12-BIT
SAR
MAX1284
MAX1285
+2.5V REFERENCE
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
7
4
5
GND
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1284/MAX1285
General Description
The MAX1284/MAX1285 12-bit analog-to-digital converters (ADCs) combine a high-bandwidth track/hold
(T/H), a serial interface with high conversion speed, an
internal +2.5V reference, and low power consumption.
The MAX1284 operates from a single +4.5V to +5.5V
supply. The MAX1285 operates from a single +2.7V to
+3.6V supply.
The 3-wire serial interface connects directly to
SPI™/QSPI™/ MICROWIRE™ devices without external
logic. The devices use an external serial-interface clock
to perform successive-approximation analog-to-digital
conversions.
Low power, ease of use, and small package size make
these converters ideal for remote-sensor and data-acquisition applications or for other circuits with demanding
power consumption and space requirements. The
MAX1284/MAX1285 are available in 8-pin SO packages.
These devices are pin-compatible, higher-speed versions of the MAX1240/MAX1241. Refer to the respective data sheets for more information.
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (VDD + 0.3V)
REF to GND ...............................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (VDD + 0.3V)
DOUT Current ..................................................................±25mA
Continuous Power Dissipation (TA = +70°C)
8-Pin SO (derate 5.88mW/°C above +70°C) ..............471mW
Operating Temperature Ranges
MAX1284BCSA/MAX1285BCSA .......................0°C to +70°C
MAX1284BESA/MAX1285BESA .....................-40°C to +85°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX1284
(VDD = +4.5V to +5.5V; fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
12
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
Bits
±1.0
LSB
±1.0
LSB
Offset Error
±6.0
LSB
Gain Error (Note 3)
±6.0
LSB
No missing codes over temperature
Gain Error Temperature
Coefficient
±0.8
ppm/°C
70
dB
-80
dB
80
dB
DYNAMIC SPECIFICATIONS (100kHz sine wave, 2.5Vp-p, clock = 6.4MHz)
Signal-to-Noise Plus Distortion
Ratio
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Intermodulation Distortion
IMD
Up to the 5th harmonic
fIN1 = 99Hz, fIN2 = 102Hz
76
dB
Full-Power Bandwidth
-3dB point
6
MHz
Full-Linear Bandwidth
SINAD > 68dB
350
kHz
CONVERSION RATE
Conversion Time (Note 4)
tCONV
Track/Hold Acquisition Time
tACQ
2.5
µs
468
ns
Aperture Delay
10
ns
Aperture Jitter
<50
ps
Serial Clock Frequency
tSCLK
Duty Cycle
0.5
6.4
MHz
40
60
%
ANALOG INPUT (AIN)
Input Voltage Range
Input Capacitance
2
VAIN
0
2.5
18
_______________________________________________________________________________________
V
pF
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
(VDD = +4.5V to +5.5V; fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
2.48
2.50
2.52
UNITS
INTERNAL REFERENCE
REF Output Voltage
VREF
REF Short-Circuit Current
REF Output Tempco
TA = +25°C
TC VREF
Load Regulation (Note 5)
0 to 1mA output load
Capacitive Bypass at REF
V
30
mA
±15
ppm/°C
0.1
4.7
2.0
mV/mA
10
µF
DIGITAL INPUTS (SCLK, CS, SHDN)
Input High Voltage
Input Low Voltage
VINH
3.0
V
VINL
Input Hysteresis
VHYST
Input Leakage
IIN
Input Capacitance
CIN
DIGITAL OUTPUT (DOUT)
Output Voltage Low
VOL
ISINK = 5mA
Output Voltage High
VOH
ISOURCE = 1mA
Three-State Leakage Current
Three-State Output Capacitance
0.8
V
±1
µA
0.2
VIN = 0 or VDD
V
15
IL
CS = +5V
COUT
CS = +5V
pF
0.4
V
±10
µA
4
V
15
pF
POWER SUPPLY
Positive Supply Voltage (Note 6)
VDD
Positive Supply Current (Note 7)
IDD
Shutdown Supply Current
Power-Supply Rejection
ISHDN
PSR
4.5
VDD = +5.5V
2.5
SCLK = VDD, SHDN = GND
VDD = +5V ±10%, midscale input
5.5
V
4.0
mA
2
10
µA
±0.5
±2.0
mV
ELECTRICAL CHARACTERISTICS—MAX1285
(VDD = +2.7V to +3.6V; fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±1.0
LSB
±1.0
LSB
Offset Error
±6.0
LSB
Gain Error (Note 3)
±6.0
LSB
DC ACCURACY (Note 1)
Resolution
12
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
Gain Error Temperature
Coefficient
Bits
No missing codes over temperature
±1.6
ppm/°C
________________________________________________________________________________________
3
MAX1284/MAX1285
ELECTRICAL CHARACTERISTICS—MAX1284 (continued)
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1285 (continued)
(VDD = +2.7V to +3.0V; fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC SPECIFICATIONS (75kHz sine wave, 2.5Vp-p, fSAMPLE = 300ksps, fSCLK = 4.8MHz)
Signal-to-Noise Plus Distortion
Ratio
SINAD
70
dB
Total Harmonic Distortion
THD
Up to the 5th harmonic
-80
dB
Spurious-Free Dynamic Range
Intermodulation Distortion
SFDR
IMD
fIN1 = 73kHz, fIN2 = 77kHz
80
76
dB
dB
3
MHz
250
kHz
Full-Power Bandwidth
-3dB point
Full-Linear Bandwidth
SINAD > 68dB
CONVERSION RATE
Conversion Time (Note 4)
tCONV
Track/Hold Acquisition Time
tACQ
3.3
Aperture Delay
Aperture Jitter
Serial Clock Frequency
µs
625
10
<50
tSCLK
Duty Cycle
ns
ns
0.5
4.8
ps
MHz
40
60
%
2.5
V
pF
2.52
V
ANALOG INPUT (AIN)
Input Voltage Range
Input Capacitance
VAIN
0
18
INTERNAL REFERENCE
REF Output Voltage
REF Short-Circuit Current
REF Output Tempco
VREF
2.48
TA = +25°C
0 to 0.75mA output load
Capacitive Bypass at REF
Input Hysteresis
0.1
4.7
DIGITAL INPUTS (SCLK, CS, SHDN)
Input High Voltage
VINH
Input Low Voltage
15
±15
TC VREF
Load Regulation (Note 5)
2.50
mA
ppm/°C
2.0
mV/mA
10
µF
2.0
V
VINL
0.8
VHYST
0.2
Input Leakage
Input Capacitance
IIN
CIN
VIN = 0 or VDD
DIGITAL OUTPUT (DOUT)
Output Voltage Low
VOL
ISINK = 5mA
Output Voltage High
Three-State Leakage Current
VOH
IL
ISOURCE = 0.5mA
CS = +3V
Three-State Output Capacitance
COUT
CS = +3V
Positive Supply Voltage (Note 6)
Positive Supply Current (Note 7)
VDD
IDD
VDD = +3.6V
Shutdown Supply Current
ISHDN
V
V
±1
µA
pF
0.4
V
±10
V
µA
15
4
15
pF
POWER SUPPLY
Power-Supply Rejection
4
PSR
2.7
SCLK = VDD, SHDN = GND
VDD = +2.7V to 3.6V, midscale input
2.5
3.6
3.5
V
mA
2
10
µA
±0.5
±2.0
mV
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
(VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Period
tCP
156
ns
SCLK Pulse Width High
tCH
62
ns
SCLK Pulse Width Low
tCL
62
ns
CS Fall to SCLK Rise Setup
tCSS
35
ns
SCLK Rise to CS Rise Hold
tCSH
0
ns
SCLK Rise to CS Fall Ignore
tCSO
35
ns
35
ns
CS Rise to SCLK Rise Ignore
tCS1
SCLK Rise to DOUT Hold
tDOH
CLOAD = 20pF
SCLK Rise to DOUT Valid
tDOV
CLOAD = 20pF
CS Rise to DOUT Disable
tDOD
CLOAD = 20pF
CS Fall to DOUT Enable
tDOE
CLOAD = 20pF
CS Pulse Width High
tCSW
10
ns
10
80
ns
65
ns
65
ns
100
ns
TIMING CHARACTERISTICS—MAX1285 (Figures 1, 2, 8, 9)
(VDD = +2.7V to +3.6V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Period
tCP
208
ns
SCLK Pulse Width High
tCH
83
ns
SCLK Pulse Width Low
tCL
83
ns
CS Fall to SCLK Rise Setup
tCSS
45
ns
SCLK Rise to CS Rise Hold
tCSH
0
ns
SCLK Rise to CS Fall Ignore
tCSO
45
ns
CS Rise to SCLK Rise Ignore
tCS1
45
ns
SCLK Rise to DOUT Hold
tDOH
CLOAD = 20pF
SCLK Rise to DOUT Valid
tDOV
CLOAD = 20pF
CS Rise to DOUT Disable
tDOD
CLOAD = 20pF
CS Fall to DOUT Enable
tDOE
CLOAD = 20pF
CS Pulse Width High
tCSW
13
13
100
ns
100
ns
85
ns
85
ns
ns
Note 1: Tested at VDD = VDD(MIN).
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Internal reference, offset, and reference errors nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA due to
production test limitations.
Note 6: Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX). For operations beyond this range, see Typical
Operating Characteristics.
Note 7: MAX1284 tested with 20pF on DOUT and fSCLK = 6.4MHz, 0 to 5V. MAX1285 tested with same loads, fSCLK = 4.8MHz,
0 to 3V. DOUT = full scale.
_______________________________________________________________________________________
5
MAX1284/MAX1285
TIMING CHARACTERISTICS—MAX1284 (Figures 1, 2, 8, 9)
__________________________________________Typical Operating Characteristics
(MAX1284: VDD = +5.0V, fSCLK = 6.4MHz, MAX1285: VDD = +3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor at REF,
TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DNL (LSB)
0
0.2
0.1
0
-0.1
-0.1
-0.2
-0.2
-0.3
0.5
0
-0.5
-0.3
-0.4
-1.0
-0.4
0
1k
2k
4k
3k
0
5k
1k
2k
3k
4k
2.5
5k
OFFSET ERROR vs. TEMPERATURE
0.8
0.6
1.2
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.6
0.2
-0.8
0
40
60
80
100
3.0
3.5
4.0
4.5
5.0
-0.5
-1.0
-40
5.5
-20
0
40
60
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.504
2.502
2.500
2.498
2.496
MAX1284/5 toc08
2.510
2.508
REFERENCE VOLTAGE (V)
MAX1284/5 toc07
2.506
20
TEMPERATURE (°C)
VDD (V)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
REFERENCE VOLTAGE (V)
0
-2.5
TEMPERATURE (°C)
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.494
2.492
2.492
2.490
2.490
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
6.0
-2.0
2.5
2.510
5.5
-1.5
-1.0
20
5.0
0.5
-0.4
0.4
4.5
1.0
GAIN ERROR (LSB)
GAIN ERROR (LSB)
1.4
0
4.0
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1284/5 toc05
1.6
-20
3.5
VDD (V)
1.0
MAX1284/5 toc04
1.8
-40
3.0
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
6
1.0
MAX1284/5 toc06
INL (LSB)
0.3
0.1
1.5
OFFSET ERROR (LSB)
0.4
MAX1284/5 toc03
0.5
0.2
2.0
MAX1284/5 toc02
0.3
OFFSET ERROR vs. SUPPLY VOLTAGE
0.6
MAX1284/5 toc01
0.4
OFFSET ERROR (LSB)
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
5.5
-40
-20
0
20
40
60
TEMPERATURE (°C)
_______________________________________________________________________________________
80
100
80
100
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
SUPPLY CURRENT vs. SUPPLY VOLTAGE
CONVERTING
SCLK = 6.4MHz
2.50
2.25
CONVERTING
SCLK = 4.8MHz
2.00
1.75
VDD = 5V, CONVERTING
2.7
2.4
VDD = 3V, CONVERTING
2.1
1.8
STATIC
1.50
MAX1284/5 toc10
CODE = 1111 1111 1111
RL = ∞
CL = 10pF
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
2.75
SUPPLY CURRENT vs. TEMPERATURE
3.0
MAX1284/5 toc09
3.00
VDD = 5V, STATIC
VDD = 3V, STATIC
1.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
SUPPLY VOLTAGE (V)
-20
0
20
40
60
80
100
TEMPERATURE (°C)
Pin Description
PIN
NAME
FUNCTION
1
VDD
Positive Supply Voltage
2
AIN
Sampling Analog Input, 0 to VREF range
3
SHDN
Active-Low Shutdown Input. Pulling SHDN low shuts down the device and reduces the supply current
to 2µA (typ).
4
REF
Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output. Bypass with 4.7µF
capacitor.
5
GND
Analog and Digital Ground
6
DOUT
Serial Data Output DOUT changes state at SCLK’s rising edge High impedance when CS is high.
7
CS
Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is high
impedance.
8
SCLK
Serial Clock Input. SCLK drives the conversion process and clocks data out at rates up to 6.4MHz
(MAX1284) or 4.8MHz (MAX1285).
_______________________________________________________________________________________
7
MAX1284/MAX1285
Typical Operating Characteristics (continued)
(MAX1284: VDD = +5.0V, fSCLK = 6.4MHz, MAX1285: VDD = +3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor at REF,
TA = +25°C, unless otherwise noted.)
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
VDD
6kΩ
DOUT
DOUT
6kΩ
CLOAD = 20pF
CLOAD = 20pF
DGND
DGND
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for DOUT Enable Time
VDD
6kΩ
DOUT
DOUT
6kΩ
CLOAD = 20pF
CLOAD = 20pF
DGND
DGND
a) VOH to High-Z
b) VOL to High-Z
Figure 2. Load Circuits for DOUT Disable Time
Detailed Description
Converter Operation
The MAX1284/MAX1285 use an input T/H and successive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. Figure
3 shows the MAX1284/MAX1285 in its simplest configuration. The internal reference is trimmed to +2.5V. The
serial interface requires only three digital lines (SCLK,
CS, and DOUT) and provides an easy interface to
microprocessors (µPs).
The MAX1284/MAX1285 have two modes: normal and
shutdown. Pulling SHDN low shuts the device down and
reduces supply current to below 2µA (typ), while pulling
SHDN high puts the device into operational mode. Pulling
CS low initiates a conversion that is driven by SCLK. The
conversion result is available at DOUT in unipolar serial
format. The serial data stream consists of three zeros,
followed by the data bits (MSB first). All transitions on
DOUT occur 20ns after the rising edge of SCLK. Figures
8 and 9 show the interface timing information.
8
Analog Input
Figure 4 illustrates the sampling architecture of the
ADC’s comparator. The full-scale input voltage is set by
the internal reference (VREF = +2.5V).
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input (AIN) charges
capacitor CHOLD. Bringing CS low, ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLD to GND. The retained charge on CHOLD represents a sample of the input, unbalancing node ZERO
at the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0 within the limits of 12bit resolution. This action is equivalent to transferring a
charge from CHOLD to the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
10µF
0.1µF
1
ANALOG INPUT
0 TO VREF
2
SHUTDOWN
INPUT
3
4
VDD
SCLK
AIN MAX1284 CS
MAX1285
DOUT
SHDN
GND
REF
8
7
SERIAL
INTERFACE
6
5
4.7µF
Input Bandwidth
The ADCs’ input tracking circuitry has a 6MHz
(MAX1284) or 3MHz (MAX1285) small-signal bandwidth, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate, by using undersampling techniques. To avoid aliasing of unwanted
high-frequency signals into the frequency band of interest, anti-alias filtering is recommended.
Figure 3. Typical Operating Circuit
GND
CAPACITIVE DAC
REF
CHOLD
12pF
AIN
ZERO
COMPARATOR
RIN
800Ω
CSWITCH*
6pF
HOLD
TRACK
AUTOZERO
RAIL
*INCLUDES ALL INPUT PARASITICS
Figure 4. Equivalent Input Circuit
side of C HOLD switches back to AIN, and C HOLD
charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and GND, allow the input to swing from
GND - 0.3V to VDD + 0.3V without damage.
If the analog input exceeds 50mV beyond the supplies, limit the input current to 2mA.
Internal Reference
The MAX1284/MAX1285 have an on-chip voltage reference trimmed to 2.5V. The internal reference output is
connected to REF and also drives the internal capacitive DAC. The output can be used as a reference voltage source for other components and can source up to
800µA. Bypass REF with a 4.7µF capacitor. Larger
capacitors increase wake-up time when exiting shutdown (see the Using SHDN to Reduce Supply Current
section). The internal reference is disabled in shutdown
(SHDN = 0).
Serial Interface
Initialization after Power-Up and
Starting a Conversion
When power is first applied, and if SHDN is not pulled
low, it takes the fully discharged 4.7µF reference
bypass capacitor up to 2ms to provide adequate
charge for specified accuracy. No conversions should
be performed during this time.
_______________________________________________________________________________________
9
MAX1284/MAX1285
+5V OR +3V
signal to be acquired. Acquisition time is calculated by:
tACQ = 9(RS + RIN) x 12pF,
where R IN = 800Ω, R S = the input signal’s source
impedance, and t ACQ is never less than 468ns
(MAX1284) or 625ns (MAX1285). Source impedances
below 2kΩ do not significantly affect the ADCs AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the analog input. Note that
the input capacitor forms an RC filter with the input
source impedance, limiting the ADCs input signal
bandwidth.
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiated. Data can then be shifted out serially with the external clock.
Using SHDN to Reduce Supply Current
Power consumption can be reduced significantly by
shutting down the MAX1284/MAX1285 between conversions. Figure 5 shows a plot of average supply current versus conversion rate. The wake-up time (tWAKE)
is the time from when SHDN is deasserted to the time
when a conversion may be initiated (Figure 6). This
time depends on the time in shutdown (Figure 7)
because the external 4.7µF reference bypass capacitor
loses charge slowly during shutdown and can be as
long as 2ms.
10k
VDD = 3V
DOUT = FS
RL = ∞
CL = 10pF
1k
SUPPLY CURRENT (µA)
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
100
10
Timing and Control
Conversion-start and data-read operations are controlled by the CS and SCLK digital inputs. The timing diagrams of Figures 8 and 9 outline serial-interface
operation.
A CS falling edge initiates a conversion sequence: the
T/H stage holds the input voltage, the ADC begins to
convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of conversion
is determined.
SCLK begins shifting out the data after the rising edge
of the third SCLK pulse. DOUT transitions 20ns after
each SCLK rising edge. The third rising clock edge
produces the MSB of the conversion at DOUT, followed
by the remaining bits. Since there are twelve data bits
and three leading zeros, at least fifteen rising clock
edges are needed to shift out these bits. Extra clock
pulses occurring after the conversion result has been
clocked out, and prior to a rising edge of CS, produce
trailing zeros at DOUT and have no effect on converter
operation.
Pull CS high after reading the conversion’s LSB. For
maximum throughout, CS can be pulled low again to
initiate the next conversion immediately after the specified minimum time (tCS).
1
Output Coding and Transfer Function
The data output from the MAX1284/MAX1285 is binary,
and Figure 10 depicts the nominal transfer function.
Code transitions occur halfway between successiveinteger LSB value VREF = +2.5V, and 1LSB = 610µV or
2.5V/4096.
0.1
0.1
1
10
100
1k
10k
100k
CONVERSION RATE (ksps)
Figure 5. Supply Current vs. Conversion Rate
COMPLETE CONVERSION SEQUENCE
CS
tWAKE
SHDN
DOUT
CONVERSION 0
POWERED-UP
CONVERSION 1
POWERED-DOWN
POWERED-UP
Figure 6. Shutdown Sequence
10
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
REFERENCE POWER-UP DELAY (ms)
Connection to Standard Interfaces
CREF = 4.7µF
The MAX1284/MAX1285 serial interface is fully compatible with SPI/QSPI and MICROWIRE (Figure 11).
If a serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 6.4MHz (MAX1284) or
4.8MHz (MAX1285).
1) Use a general-purpose I/O line on the CPU to pull CS
low. Keep SCLK low.
2) Activate SCLK for a minimum of fifteen clock cycles.
The first two clocks produce zeros at DOUT. DOUT
output data transitions 20ns after the third SCLK rising
edge and is available in MSB-first format. Observe the
1.25
1.00
0.75
0.50
0.25
0
0.0001
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (s)
Figure 7. Reference Power-Up vs. Time in Shutdown
CS
1
3
4
8
12
15
SCLK
HIGH-Z
DOUT HIGH-Z
A/D STATE
D11 D10 D9
D8
D7
D6
HOLD/CONVERT
D5
D4
D3
D2
D1
D0
ACQUISITION
ACQ
Figure 8. Interface Timing Sequence
CS
tCSW
ttCSO
CSO
tCL
tCSS
tCH
tCSH
tCSI
SCLK
tCP
tDOH
tDOE
tDOV
tDOD
DOUT
Figure 9. Detailed Serial-Interface Timing
______________________________________________________________________________________
11
MAX1284/MAX1285
Applications Information
1.50
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
OUTPUT CODE
11…111
FULL-SCALE
TRANSITION
I/O
CS
SCK
11…110
SCLK
MISO
11…101
DOUT
+3V TO +5V
MAX1284
MAX1285
FS = VREF - 1LSB
1LSB = VREF
4096
SS
a) SPI
00…011
CS
00…010
SCK
CS
SCLK
MISO
00…001
DOUT
+3V TO +5V
00…000
0
1
2
3
INPUT VOLTAGE (LSBs)
Figure 10. Unipolar Transfer Function, Full Scale (FS) =
VREF - 1LSB, Zero Scale (ZS) = GND
SS
b) QSPI
SCLK to DOUT valid timing characteristic. Data can be
clocked into the µP on SCLK rising edge.
3) Pull CS high at or after the 15th rising clock edge. If CS
remains low, trailing zeros are clocked out after the
LSB.
4) With CS = high, wait the minimum specified time, tCS,
before initiating a new conversion by pulling CS low. If
a conversion is aborted by pulling CS high before the
conversion completes, wait for the minimum acquisition
time, tACQ, before starting a new conversion.
CS must be held low until all data bits are clocked out.
Data can be output in two bytes or continuously, as
shown in Figure 8. The bytes contain the result of the
conversion padded with three leading zeros and three
trailing zeros.
SPI and MICROWIRE
When using SPI or MICROWIRE, set CPOL = 0 and
CPHA = 0. Conversion begins with a CS falling edge.
DOUT goes low, indicating a conversion in progress. Two
consecutive 1-byte reads are required to get the full
twelve bits from the ADC. DOUT output data transitions
on SCLK’s rising edge and is clocked into the following
µP on the rising edge.
The first byte contains three leading zeros, and five bits of
conversion result. The second byte contains the remaining
seven bits and one trailing zero. See Figure 11 for connections and Figure 12 for timing.
12
MAX1284
MAX1285
FS
FS - 3/2LSB
I/O
CS
SK
SCLK
SI
DOUT
MAX1284
MAX1285
c) MICROWIRE
Figure 11. Common Serial-Interface Connections to the
MAX1284/MAX1285
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the
data. The MAX1284/MAX1285 require 15 clock cycles
from the µP to clock out the 12 bits of data. Figure 13
shows a transfer using CPOL = 0 and CPHA = 1. The
conversion result contains two zeros followed by the 12
bits of data in MSB-first formatted.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap boards
are not recommended. Board layout should ensure that
digital and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
lines parallel to one another, or digital lines underneath
the ADC package.
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1284/MAX1285 are measured using the endpoints method.
High-frequency noise in the VDD power supply may affect
the ADC’s high-speed comparator. Bypass this supply to
the single-point analog ground with 0.1µF and 10µF
bypass capacitors. Minimize capacitor lead lengths for
best supply noise rejection. To reduce the effects of supply noise, a 10Ω resistor can be connected as a lowpass
filter to attenuate supply noise (Figure 14).
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A DNL
error specification of 1LSB or less guarantees no missing
codes and a monotonic transfer function.
CS
8
1
9
16
SCLK
DOUT
HIGH-Z
HIGH-Z
D11
D10
D9
D8
D7
D5
D6
D4
FIRST BYTE READ
D3
D2
D1
D0
SECOND BYTE READ
Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
CS
1
SCLK
HIGH-Z
DOUT
14
3
HIGH-Z
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 13. QSPI Serial Interface Timing (CPOL = 0, CPHA = 1)
______________________________________________________________________________________
13
MAX1284/MAX1285
Figure 14 shows the recommended system ground connections. Establish a single-point analog ground (“star”
ground point) at GND, separate from the logic ground.
Connect all other analog grounds and DGND to this star
ground point for further noise reduction. No other digital
system ground should be connected to this single-point
analog ground. The ground return to the power supply for
this ground should be low impedance and as short as
possible for noise-free operation.
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
MAX1284/MAX1285
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SUPPLIES
VDD
VDD
GND
SINAD (dB) = 20 x log (SignalRMS/NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale
range of the ADC, calculate the effective number of bits
as follows:
R* = 10Ω
4.7µF
0.1µF
VDD
GND
VDD
DGND
DIGITAL
CIRCUITRY
MAX1284
MAX1285
ENOB = (SINAD − 1.76)
6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
*OPTIONAL
Figure 14. Power-Supply Grounding Condition
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of CS and the instant when an actual sample
is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The theoretical minimum analog-to-digital
noise is caused by quantization error, and results directly
from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.
14


V22 + V32 + V42 + V52


THD = 20 x log


V1




where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion
component.
___________________Chip Information
TRANSISTOR COUNT: 4286
PROCESS: BiCMOS
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
DIM
E
A
A1
B
C
D
E
e
H
h
L
α
H
INCHES
MAX
MIN
0.069
0.053
0.010
0.004
0.019
0.014
0.010
0.007
0.344
0.337
0.157
0.150
0.050 BSC
0.244
0.228
0.020
0.010
0.050
0.016
8˚
0˚
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.27
0˚
8˚
21-331A
h x 45˚
D
α
A
0.127mm
0.004in.
e
B
A1
C
L
14-PIN PLASTIC
SMALL-OUTLINE
PACKAGE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________15
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX1284/MAX1285
________________________________________________________________Package Information