19-5122; Rev 1; 4/10 TION KIT EVALUA BLE A IL A V A Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer Features The MAX5392 dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer offers three end-to-end resistance values of 10kI, 50kI, and 100kI. Operating from a single +1.7V to +5.5V power supply, the device provides a low 35ppm/NC end-to-end temperature coefficient. The device features an I2C interface. S Dual, 256-Tap Linear Taper Positions The small package size, low supply operating voltage, low supply current, and automotive temperature range of the MAX5392 makes the device uniquely suited for the portable consumer market, battery-backup industrial applications, and the automotive market. S Wiper Set to Midscale on Power-Up S Single +1.7V to +5.5V Supply Operation S Low 12µA Quiescent Supply Current S 10kI, 50kI, 100kI End-to-End Resistance Values S I2C-Compatible Interface S -40NC to +125NC Operating Temperature Range The MAX5392 is specified over the automotive -40NC to +125NC temperature range and is available in a 16-pin TSSOP package. Applications Low-Voltage Battery Applications Portable Electronics Mechanical Potentiometer Replacement Ordering Information PART PIN-PACKAGE END-TO-END RESISTANCE (kI) MAX5392LAUE+ 16 TSSOP MAX5392MAUE+ 16 TSSOP 10 50 MAX5392NAUE+ 16 TSSOP 100 Note: All devices are specified over the -40°C to +125NC operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. Offset and Gain Control Adjustable Voltage References/Linear Regulators Functional Diagram Automotive Electronics VDD BYP HA WA LA CHARGE PUMP SCL LATCH 256 DECODER SDA A0 HB I2C POR MAX5392 A1 A2 LATCH 256 DECODER WB LB GND ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX5392 General Description MAX5392 Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70NC) 16-Pin TSSOP (derate 11.1mW/NC above +70NC)....888.9mW Operating Temperature Range . ...................... -40NC to +125NC Junction Temperature .....................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC VDD to GND ............................................................-0.3V to +6V H_, W_, L_ to GND.......................................-0.3V to the lower of (VDD + 0.3V) and +6V All Other Pins to GND..............................................-0.3V to +6V Continuous Current in to H_, W_, and L_ MAX5392L...................................................................... Q5mA MAX5392M..................................................................... Q2mA MAX5392N...................................................................... Q1mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = GND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V, TA = +25NC.) (Note 1) PARAMETER Resolution SYMBOL CONDITIONS N MIN TYP MAX 256 UNITS Tap DC PERFORMANCE (Voltage Divider Mode) Integral Nonlinearity INL (Note 2) -0.5 +0.5 LSB Differential Nonlinearity DNL (Note 2) -0.5 +0.5 LSB Dual Code Matching Register A = Register B -0.5 +0.5 Ratiometric Resistor Tempco (DVW/VW)/DT, no load Full-Scale Error Code = FFh 5 MAX5392L -3 -2.2 MAX5392M -1 -0.6 MAX5392N -0.5 -0.3 MAX5392L Zero-Scale Error Code = 00h LSB ppm/NC LSB 2.2 3 MAX5392M 0.6 1.0 MAX5392N 0.3 0.5 LSB DC PERFORMANCE (Variable Resistor Mode) Integral Nonlinearity R-INL Differential Nonlinearity R-DNL MAX5392L (Note 3) MAX5392M (Note 3) MAX5392N (Note 3) (Note 3) -1.5 -0.75 -0.5 -0.5 +1.5 +0.75 +0.5 +0.5 LSB LSB DC PERFORMANCE (Resistor Characteristics) Wiper Resistance RWL (Note 4) 200 I CH_, CL_ Measured to GND 10 pF CW_ Measured to GND 50 pF End-to-End Resistor Tempco TCR No load End-to-End Resistor Tolerance DRHL Wiper not connected Terminal Capacitance Wiper Capacitance 35 -25 2 _______________________________________________________________________________________ ppm/NC +25 % Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer (VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = GND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V, TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AC PERFORMANCE Crosstalk (Note 5) -3dB Bandwidth Code = 80H, 10pF load, VDD = 1.8V BW Total Harmonic Distortion Plus Noise Wiper Settling Time Charge-Pump Feedthrough at W_ THD+N tS VRW -90 MAX5392L 600 MAX5392M 100 MAX5392N 50 Measured at W, VH_ = 1VRMS at 1kHz (Note 6) dB kHz 0.02 MAX5392L 400 MAX5392M 1200 MAX5392N 2200 fCLK = 600kHz, CBYP = 0nF % ns 600 nVP-P 5.5 V POWER SUPPLIES Supply Voltage Range 1.7 VDD Standby Current VDD = 5.5V 27 VDD = 1.7V 12 FA DIGITAL INPUTS Minimum Input High Voltage VIH Maximum Input Low Voltage VIL VDD = 2.6V to 5.5V 70 VDD = 1.7V to 2.6V 75 % x VDD VDD = 2.6V to 5.5V 30 VDD = 1.7V to 2.6V 25 Input Leakage Current -1 Input Capacitance +1 5 % x VDD FA pF TIMING CHARACTERISTICS—I2C (Notes 7 and 8) Maximum SCL Frequency 400 fSCL kHz Setup Time for START Condition tSU:STA 0.6 Fs Hold Time for START Condition tHD:STA 0.6 Fs SCL High Time tHIGH 0.6 Fs SCL Low Time tLOW 1.3 Fs _______________________________________________________________________________________ 3 MAX5392 ELECTRICAL CHARACTERISTICS (continued) MAX5392 Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer ELECTRICAL CHARACTERISTICS (continued) (VDD = +1.7V to +5.5V, VH_ = VDD, VL_ = GND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +1.8V, TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN Data Setup Time tSU:DAT 100 Data Hold Time tHD:DAT 0 TYP MAX ns Fs SDA, SCL Rise Time tR 0.3 SDA, SCL Fall tF 0.3 Setup Time for STOP Condition Bus Free Time Between STOP and START Condition tSU:STO tBUF Pulse Suppressed Spike Width tSP Capacitive Load for Each Bus CB Minimum power-up rate = 0.2V/Fs UNITS Fs Fs 0.6 Fs 1.3 Fs (Note 9) 50 ns 400 pF Note 1: All devices are 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design and characterization. Note 2: DNL and INL are measured with the potentiometer configured as a voltage-divider (Figure 1) with H_ = VDD and L_ = GND. The wiper terminal is unloaded and measured with a high-input-impedance voltmeter. Note 3: R-DNL and R-INL are measured with the potentiometer configured as a variable resistor (Figure 1). DNL and INL are measured with the potentiometer configured as a variable resistor. H_ is unconnected and L_ = GND. For VDD = +5V, the wiper terminal is driven with a source current of 400FA for the 10kI configuration, 80FA for the 50kI configuration, and 40FA for the 100kI configuration. For VDD = +1.7V, the wiper terminal is driven with a source current of 150FA for the 10kI configuration, 30FA for the 50kI configuration, and 15FA for the 100kI configuration. Note 4: The wiper resistance is the worst value measured by injecting the currents given in Note 3 to W_ with L_ = GND. RW_ = (VW_ - VH_)/IW_. Note 5: Drive HA with a 1kHz GND to VDD amplitude tone. LA = LB = GND. No load. WB is at midscale with a 10pF load. Measure WB. Note 6: The wiper-settling time is the worst-case 0 to 50% rise time, measured between tap 0 and tap 127. H_ = VDD, L_ = GND, and the wiper terminal is loaded with 10pF capacitance to ground. Note 7: Digital timing is guaranteed by design and characterization, not production tested. Note 8: The SCL clock period includes rise and fall times (tR = tF). All digital input signals are specified with tR = tF = 2ns and timed from a voltage level of (VIL + VIH)/2. Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. For I2C-bus specification information from NXP Semiconductor (formerly Philips Semiconductor), refer to the UM10204: I2C-Bus Specification and User Manual. H N.C. W L W L Figure 1. Voltage-Divider and Variable Resistor Configurations 4 _______________________________________________________________________________________ Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer SUPPLY CURRENT vs. TEMPERATURE VDD = 2.6V 10 VDD = 1.8V 100 25 VDD = 2.6V 10 20 15 VDD = 1.8V 0 10 1 -40 -20 -10 5 20 35 50 65 80 95 110 125 0 2.7 3.2 3.7 4.2 4.7 VDD (V) RESISTANCE (W_-TO-L_) vs. TAP POSITION (10kI) RESISTANCE (W_-TO-L_) vs. TAP POSITION (50kI) RESISTANCE (W_-TO-L_) vs. TAP POSITION (100kI) 6 5 4 3 2 35 30 25 20 15 10 5 0 0 102 153 204 255 100 90 80 70 60 50 40 30 20 10 0 0 51 102 153 204 0 255 51 102 153 204 TAP POSITION TAP POSITION WIPER RESISTANCE vs. WIPER VOLTAGE (10kI) END-TO-END RESISTANCE PERCENTAGE CHANGE vs. TEMPERATURE VARIABLE RESISTOR DNL vs. TAP POSITION (10kI) 100 VDD = 5V 80 VDD = 1.8V VDD = 2.6V 60 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 WIPER VOLTAGE (V) 0.03 0 0.08 0.06 0.04 0.02 0.01 255 MAX5392 toc09 100kI MAX5392 toc08 0.04 0.10 DNL (LSB) 120 0.05 END-TO-END RESISTANCE % CHANGE MAX5392 toc07 TAP POSITION 140 5.2 MAX5392 toc06 40 1 51 MAX5392 toc05 45 W_-TO-L_ RESISTANCE (kI) 7 50 W_-TO-L_ RESISTANCE (kI) MAX5392 toc04 8 0 2.2 DIGITAL INPUT VOLTAGE (V) 9 0 1.7 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE (°C) 10 W_-TO-L_ RESISTANCE (kI) MAX5392 toc03 MAX5392 toc02 VDD = 5V 5 WIPER RESISTANCE (I) 30 IDD (µA) VDD = 5V 15 1000 SUPPLY CURRENT (µA) 25 SUPPLY CURRENT (µA) 10,000 MAX5392 toc01 30 20 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE 50kI 10kI -0.01 0.02 0 -0.02 -0.04 -0.06 -0.02 -0.08 -0.03 -0.10 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) IWIPER = 150µA 0 51 102 153 204 255 TAP POSITION _______________________________________________________________________________________ 5 MAX5392 Typical Operating Characteristics (VDD = 1.8V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 1.8V, TA = +25°C, unless otherwise noted.) VARIABLE RESISTOR DNL vs. TAP POSITION (50kI) 0.06 0.08 0.06 0.8 0.6 0.4 0.02 0.02 0.2 0 -0.02 INL (LSB) 0.04 DNL (LSB) 0.04 0 -0.02 0 -0.2 -0.04 -0.04 -0.4 -0.06 -0.06 -0.6 -0.08 -0.08 IWIPER = 30µA -0.10 -0.8 IWIPER = 15µA -0.10 51 102 153 204 255 0 51 102 153 204 255 0 102 153 204 TAP POSITION TAP POSITION VARIABLE RESISTOR INL vs. TAP POSITION (50kI) VARIABLE RESISTOR INL vs. TAP POSITION (100kI) VOLTAGE-DIVIDER DNL vs. TAP POSITION (10kI) 0.3 0.4 0.10 0.3 0.08 0.06 0.04 0.1 0.1 0.02 0 -0.1 DNL (LSB) 0.2 INL (LSB) 0.2 0 -0.1 0 -0.02 -0.2 -0.2 -0.04 -0.3 -0.3 -0.06 -0.4 -0.4 IWIPER = 30µA -0.5 -0.08 IWIPER = 15µA -0.5 51 102 153 204 255 -0.10 0 51 102 153 204 255 0 51 102 153 204 TAP POSITION TAP POSITION TAP POSITION VOLTAGE-DIVIDER DNL vs. TAP POSITION (50kI) VOLTAGE-DIVIDER DNL vs. TAP POSITION (100kI) VOLTAGE-DIVIDER INL vs. TAP POSITION (10kI) 0.06 0.08 0.5 0.06 0.4 0.3 0.2 0.02 0.02 0.1 0 -0.02 INL (LSB) 0.04 DNL (LSB) 0.04 0 -0.02 0 -0.1 -0.04 -0.04 -0.2 -0.06 -0.06 -0.3 -0.08 -0.08 -0.4 -0.10 -0.10 51 102 153 TAP POSITION 204 255 255 MAX5392 toc18 0.08 MAX5392 toc17 0.10 MAX5392 toc16 0.10 255 MAX5392 toc15 0.5 MAX5392 toc13 0.4 0 51 TAP POSITION 0.5 0 IWIPER = 150µA -1.0 MAX5392 toc14 0 INL (LSB) 1.0 MAX5392 toc12 0.10 VARIABLE RESISTOR INL vs. TAP POSITION (10kI) MAX5392 toc11 0.08 DNL (LSB) VARIABLE RESISTOR DNL vs. TAP POSITION (100kI) MAX5392 toc10 0.10 DNL (LSB) MAX5392 Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer -0.5 0 51 102 153 TAP POSITION 204 255 0 51 102 153 TAP POSITION 6 _______________________________________________________________________________________ 204 255 Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer VOLTAGE-DIVIDER INL vs. TAP POSITION (100kI) VOLTAGE-DIVIDER INL vs. TAP POSITION (50kI) 0.3 MAX5392 toc20 0.4 0.4 0.3 0.2 0.2 0.1 0.1 INL (LSB) INL (LSB) 0.5 MAX5392 toc19 0.5 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.5 0 51 102 153 204 0 255 51 102 153 204 255 TAP POSITION TAP POSITION TAP-TO-TAP SWITCHING TRANSIENT (CODE 127 TO 128) 10kI TAP-TO-TAP SWITCHING TRANSIENT (CODE 127 TO 128) 50kI MAX5392 toc22 MAX5392 toc21 VDD = 5V VDD = 5V VW_-L_ 20mV/div VW_-L_ 20mV/div SCL 5V/div SCL 5V/div 1µs/div 400ns/div TAP-TO-TAP SWITCHING TRANSIENT (CODE 127 TO 128) 100kI P0WER-ON TRANSIENT (50kI) MAX5392 toc24 MAX5392 toc23 VDD = 5V VW_-L_ 1V/div VW_-L_ 20mV/div VCC 5V/div SCL 5V/div 1µs/div 2µs/div _______________________________________________________________________________________ 7 MAX5392 Typical Operating Characteristics (continued) (VDD = 1.8V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 1.8V, TA = +25°C, unless otherwise noted.) VDD = 5V 0 GAIN (dB) GAIN (dB) 0 -10 VDD = 5V 0 VDD = 1.8V -10 10 GAIN (dB) VDD = 5V 10 MAX5392 toc25 10 MIDSCALE FREQUENCY RESPONSE (100kI) -10 VDD = 1.8V VDD = 1.8V -20 -20 -20 VIN = 1VP-P CW = 10pF VIN = 1VP-P CW = 10pF VIN = 1VP-P CW = 10pF -30 0.1 1 10 100 1000 10,000 -30 0.01 0.1 1 10 1000 10,000 100 FREQUENCY (kHz) FREQUENCY (kHz) CROSSTALK vs. FREQUENCY TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX5392 toc28 0 -20 -40 0.18 0.16 -100 10 100 1000 10,000 BYP RAMP TIME vs. CBYP 100 RAMP TIME (ms) THD+N (%) 50kI -80 100kI 0.12 1 120 10kI 0.14 -60 0.1 FREQUENCY (kHz) 0.20 100kI 0.01 MAX5392 toc29 0.01 0.10 0.08 MAX5392 toc30 -30 MAX5392 toc27 MIDSCALE FREQUENCY RESPONSE (50kI) MAX5392 toc26 MIDSCALE FREQUENCY RESPONSE (10kI) 80 60 40 0.06 0.04 -120 10kI 0.02 -140 0.01 0.1 1 10 100 0 0 1000 0.1 0.01 FREQUENCY (kHz) 1 10 0 100 0.02 600 0.05 CHARGE-PUMP FEEDTHROUGH AT W_ vs. FREQUENCY 1.0 MAX5392 toc31 700 0.04 BYP CAPACITANCE (µF) FREQUENCY (kHz) CHARGE-PUMP FEEDTHROUGH AT W_ vs. CBYP 500 0.9 0.8 AMPLITUDE (µVRMS) VOLTAGE (nVRMS) 20 50kI 400 300 200 MAX5392 toc32 CROSSTALK (dB) MAX5392 Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer 0.7 0.6 0.5 0.4 0.3 0.2 100 0.1 0 0 0 200 400 CAPACITANCE (pF) 600 800 300 400 500 600 700 800 FREQUENCY (kHz) 8 _______________________________________________________________________________________ 900 0.08 0.10 Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer TOP VIEW HA 1 + 16 VDD WA 2 15 N.C. LA 3 14 SCL HB 4 WB 5 13 SDA MAX5392 12 A0 LB 6 11 A1 BYP 7 10 A2 I.C. 8 9 GND TSSOP Pin Description PIN NAME FUNCTION 1 HA Resistor A High Terminal. The voltage at HA can be higher or lower than the voltage at LA. Current can flow into or out of HA. 2 WA Resistor A Wiper Terminal 3 LA Resistor A Low Terminal. The voltage at LA can be higher or lower than the voltage at HA. Current can flow into or out of LA. 4 HB Resistor B High Terminal. The voltage at HB can be higher or lower than the voltage at LB. Current can flow into or out of HB. 5 WB Resistor B Wiper Terminal 6 LB Resistor B Low Terminal. The voltage at LB can be higher or lower than the voltage at HB. Current can flow into or out of LB. 7 BYP Internal Power-Supply Bypass. For additional charge-pump filtering, bypass to GND with a capacitor close to the device. 8 I.C. Internally Connected. Connect to GND. 9 GND 10 A2 Address Input 2. Connect to VDD or GND. 11 A1 Address Input 1. Connect to VDD or GND. 12 A0 13 SDA Address Input 0. Connect to VDD or GND. I2C-Compatible Serial-Data Input/Output. A pullup resistor is required. 14 SCL I2C-Compatible Serial-Clock Input. A pullup resistor is required. 15 N.C. No Connection. Not internally connected. 16 VDD Power-Supply Input. Bypass VDD to GND with a 0.1FF capacitor close to the device. Ground _______________________________________________________________________________________ 9 MAX5392 Pin Configuration MAX5392 Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer Detailed Description The MAX5392 dual, 256-tap, volatile, low-voltage linear taper digital potentiometer offers three end-to-end resistance values of 10kI, 50kI, and 100kI. The potentiometer consists of 255 fixed resistors in series between terminals H_ and L_. The potentiometer wiper, W_, is programmable to access any one of the 256 tap points on the resistor string. The potentiometers are programmable independently of each other. The MAX5392 features an I2C interface. Charge Pump TThe MAX5392 contains an internal charge pump that guarantees the maximum wiper resistance, RWL, to be less than 200Ω for supply voltages down to 1.7V. Pins H_, W_, and L_ are still required to be less than VDD + 0.3V. A bypass input, BYP, is provided to allow additional filtering of the charge-pump output, further reducing clock feedthrough that can occur on H_, W_, or L_. The nominal clock rate of the charge pump is 600kHz. BYP should remain resistively unloaded as any additional load would increase clock feedthrough. See the Charge-Pump Feedthrough at W_ vs. CBYP graph in the Typical Operating Characteristics for CBYP sizing guidelines with respect to clock feedthrough to the wiper. The value of CBYP does affect the startup time of the charge pump; however, CBYP does not impact the ability to communicate with the device, nor is there a minimum CBYP requirement. The maximum wiper impedance specification is not guaranteed until the charge pump is fully settled. See the BYP Ramp Time vs. CBYP graph in the Typical Operating Characteristics for CBYP impact on charge-pump settling time. I2C Digital Interface I2C The interface contains a shift register that decodes the command and address bytes, routing the data to the appropriate control registers. Data written to a control register immediately updates the wiper position. The wipers A and B power up in midposition, D[7:0] = 80h. Serial Addressing The MAX5392 operates as a slave device that receives data through an I2C/SMBusK-compatible 2-wire serial interface. The interface uses a serial-data access line (SDA) and a serial-clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master, typically a microcontroller, initiates all data transfers to the port and generates the SCL clock that synchronizes the data transfer. See Figure 2. Connect a pullup resistor, typically 4.7kI, between each of the SDA and SCL lines to a voltage between VDD and 5.5V. tHD:STA SDA tSU:STD tSU:DTA tSU:DAT tBUF tHD:DAT tLOW SCL tHIGH tHD:STA tR tF START CONDITION (S) REPEATD START CONDITION (Sr) ACKNOWLEDGE (A) STOP CONDITION START CONDITION (P) (S) Figure 2. I2C Serial-Interface Timing Diagram SMBus is a trademark of Intel Corp. 10 ������������������������������������������������������������������������������������� Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer START and STOP Conditions SCL and SDA remain high when the interface is inactive. A master controller signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. The master controller issues a STOP condition by transitioning the SDA from low to high while SCL is high, after finishing communicating with the slave. The bus is then free for another transmission. See Figure 2. Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable while SCL is high. See Figure 5. Acknowledge The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data. See Figure 6. Each byte transferred requires a total of 9 bits. The master controller generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, so the SDA line remains stable low during the high period of the clock pulse. SDA SCL P S START CONDITION STOP CONDITION Figure 3. START and STOP Conditions SDA 0 1 0 1 A2 MSB START A1 A0 NOP/W ACK LSB SCL Figure 4. Slave Address SDA CHANGE OF DATA ALLOWED DATA STABLE, DATA VALID SCL Figure 5. Bit Transfer ______________________________________________________________________________________ 11 MAX5392 Each transmission consists of a START (S) condition sent by a master, followed by a 7-bit slave address plus a NOP/W bit. See Figures 3, 4, and 7. MAX5392 Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL 1 2 8 9 NOT ACKNOWLEDGE SDA ACKNOWLEDGE Figure 6. Acknowledge ACKNOWLEDGE HOW CONTROL BYTE AND DATA BYTE MAP INTO DEVICE REGISTERS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ACKNOWLEDGE S 0 A SLAVE ADDRESS A A COMMAND BYTE P 1 DATA BYTE NOP/W Figure 7. Command and Single Data Byte Received Slave Address The MAX5392 includes a 7-bit slave address (Figure 4). The 8th bit following the 7th bit of the slave address is the NOP/W bit. Set the NOP/W bit low for a write command and high for a no-operation command. The device does not support readback. The device provides three address inputs (A0, A1, and A2), allowing up to eight devices to share a common bus (Table 1). The first 4 bits (MSBs) of the factory-set slave addresses are always 0101. A2, A1, and A0 set the next 3 bits of the slave address. Connect each address input to VDD or GND. Each device must have a unique address to share a common bus. Message Format for Writing Write to the devices by transmitting the device’s slave address with NOP/W (8th bit) set to zero, followed by at least 2 bytes of information. The first byte of informa- tion is the command byte. The second byte is the data byte. The data byte goes into the internal register of the device as selected by the command byte (Figure 7 and Table 2). Table 1. Slave Addresses ADDRESS INPUTS SLAVE ADDRESS A2 A1 A0 GND GND GND 0101000 GND GND VDD 0101001 GND VDD GND 0101010 GND VDD VDD 0101011 VDD GND GND 0101100 0101101 VDD GND VDD VDD VDD GND 0101110 VDD VDD VDD 0101111 12 ������������������������������������������������������������������������������������� Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer CYCLE NUMBER COMMAND BYTE 2 3 4 5 6 7 8 A6 A5 A4 A3 A2 A1 A0 W 9 ACK (A) DATA BYTE 10 11 12 13 14 15 16 17 R7 R6 R5 R4 R3 R2 R1 R0 18 ACK (A) 19 20 21 22 23 24 25 26 D7 D6 D5 D4 D3 D2 D1 D0 REG A 0 1 0 1 A2 A1 A0 0 0 0 0 1 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 REG B 0 1 0 1 A2 A1 A0 0 0 0 0 1 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 REG A AND B 0 1 0 1 A2 A1 A0 0 0 0 0 1 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Command Byte Use the command byte to select the destination of the wiper data. See Table 2. Command Descriptions REG A: The data byte writes to register A and the wiper of potentiometer A moves to the appropriate position. D[7:0] indicates the position of the wiper. D[7:0] = 00h moves the wiper to the position closest to LA. D[7:0] = FFh moves the wiper closest to HA. D[7:0] is 80h following power-on. Variable Gain Amplifier Adjustable Dual Regulator Figure 10 shows an adjustable dual linear regulator using a dual potentiometer as two variable resistors. H L W VIN VOUT Figure 9. Variable Gain Inverting Amplifier VOUT1 VOUT2 OUT2 VIN VOUT MAX8866 V+ W IN H H L L W SET1 H (A) Figure 8 shows a potentiometer adjusting the gain of a noninverting amplifier. Figure 9 shows a potentiometer adjusting the gain of an inverting amplifier. OUT1 L ACK Applications Information REG B: The data byte writes to register B and the wiper of potentiometer B moves to the appropriate position. D[7:0] indicates the position of the wiper. D[7:0] = 00h moves the wiper to the position closest to LB. D[7:0] = FFh moves the wiper to the position closest to HB. D[7:0] is 80h following power-on. REG A and B: The data byte writes to registers A and B and the wipers of potentiometers A and B move to the appropriate position. D[7:0] indicates the position of the wiper. D[7:0] = 00h moves the wipers to the position closest to L_. D[7:0] = FFh moves the wipers to the position closest to H_. D[7:0] is 80h following power-on. 27 STOP (P) SCL START (S) ADDRESS BYTE 1 W SET2 Figure 8. Variable Gain Noninverting Amplifier Figure 10. Adjustable Dual Linear Regulator ______________________________________________________________________________________ 13 MAX5392 Table 2. I2C Command Byte Summary MAX5392 Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer Adjustable Voltage Reference Figure 11 shows an adjustable voltage reference circuit using a potentiometer as a voltage-divider. Variable Gain Current to Voltage Converter Figure 12 shows a variable gain current to voltage converter using a potentiometer as a variable resistor. Programmable Filter Figure 15 shows a programmable filter using a dual potentiometer. Offset Voltage Adjustment Circuit Figure 16 shows an offset voltage adjustment circuit using a dual potentiometer. LCD Bias Control Figure 13 shows a positive LCD bias control circuit using a potentiometer as a voltage-divider. Chip Information PROCESS: BiCMOS Figure 14 shows a positive LCD bias control circuit using a potentiometer as a variable resistor. +2.5V 1.8V IN VREF OUT MAX6037 H H W W VOUT L L GND Figure 11. Adjustable Voltage Reference Figure 13. Positive LCD Bias Control Using a Voltage Divider 1.8V R3 H W IS R1 R2 H W L VOUT VOUT L VOUT = IS x ((R3 x (1 + R2/R1)) + R2) Figure 12. Variable Gain I-to-V Converter Figure 14. Positive LCD Bias Control Using a Variable Resistor 14 ������������������������������������������������������������������������������������� Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer WA WB VIN LA HA LB HB VOUT R3 VOUT R1 HA HB R2 WA LA WB LB Figure 15. Programmable Filter Figure 16. Offset Voltage Adjustment Circuit Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE Document No. 16 TSSOP U16+2 21-0066 ______________________________________________________________________________________ 15 MAX5392 1.8V MAX5392 Dual, 256-Tap, Volatile, Low-Voltage, Linear Taper Digital Potentiometer Revision History REVISION NUMBER REVISION DATE 0 1/10 Initial release 1 4/10 Added Soldering Temperature in Absolute Maximum Ratings; corrected code in Conditions of -3dB Bandwidth specification in Electrical Characteristics DESCRIPTION PAGES CHANGED — 2, 3 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 © 2010 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.