128-Position I2C Compatible Digital Resistor AD5246 FUNCTIONAL BLOCK DIAGRAM 128-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Ultracompact SC70-6 (2 mm × 2.1 mm) package I2C® compatible interface Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/°C Low power, IDD = 3 µA typical Wide operating temperature –40°C to +125°C Evaluation board available VDD SCL SDA I2C INTERFACE A W WIPER REGISTER B 03875-0-001 FEATURES GND Figure 1. APPLICATIONS Mechanical potentiometer replacement in new designs Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment 1 Note: The terms digital potentiometer, VR, and RDAC are used interchangeably in this document. GENERAL OVERVIEW The AD5246 provides a compact 2 mm × 2.1 mm packaged solution for 128-position adjustment applications. This device performs the same electronic adjustment function as a variable resistor. Available in four different end-to-end resistance values (5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ), these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments. The wiper settings are controllable through the I2C compatible digital interface, which can also be used to read back the present wiper register control word. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC1 latch. Operating from a 2.7 V to 5.5 V power supply and consuming 3 µA allows for usage in portable battery-operated applications. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD5246 TABLE OF CONTENTS Electrical Characteristics—5 kΩ Version ...................................... 3 ESD Protection ........................................................................... 13 Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4 Terminal Voltage Operating Range.......................................... 14 Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions 5 Maximum Operating Current .................................................. 14 Absolute Maximum Ratings............................................................ 6 Power-Up Sequence ................................................................... 14 Typical Performance Characteristics ............................................. 7 Layout and Power Supply Bypassing ....................................... 14 Test Circuits..................................................................................... 10 Constant Bias to Retain Resistance Setting............................. 15 I2C Interface..................................................................................... 11 Evaluation Board ........................................................................ 15 Operation......................................................................................... 12 Pin Configuration and Function Descriptions........................... 16 Programming the Variable Resistor ......................................... 12 Outline Dimensions ....................................................................... 17 I2C Compatible 2-Wire Serial Bus............................................ 13 Ordering Guide .......................................................................... 17 Level Shifting for Bidirectional Interface ................................ 13 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD5246 ELECTRICAL CHARACTERISTICS—5 kΩ VERSION Table 1. VDD = 5 V ±10% or 3 V ± 10%; VA = +VDD; –40°C < TA < +125°C; unless otherwise noted Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient RWB RESISTOR TERMINALS Voltage Range4 Capacitance5 B Capacitance5 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance5 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation6 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 7 Bandwidth –3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Density Symbol Conditions Min Typ1 Max Unit R-DNL R-INL ∆RAB ∆RAB/∆T RWB RWB RWB TA = 25°C Wiper = No Connect Code=0x00, VDD = 5 V Code=0x00, VDD = 2.7 V –1.5 –4 –30 ±0.1 ±0.75 +1.5 +4 +30 LSB LSB % ppm/°C Ω Ω VB, W CB CW ICM VIH VIL VIH VIL IIL CIL 45 75 150 GND f = 1 MHz, Measured to GND, Code = 0x40 f = 1 MHz, Measured to GND, Code = 0x40 VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 150 400 VDD 45 60 1 2.4 0.8 2.1 0.6 ±1 5 VDD RANGE IDD PDISS PSSR VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V ± 10%, Code = Midscale 2.7 3 BW_5K THDW tS eN_WB RAB = 5 kΩ, Code = 0x40 VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 5 V, ±1 LSB Error Band RWB = 2.5 kΩ, RS = 0 Ω 1.2 0.05 1 6 1 ±0.01 5.5 8 40 ±0.02 Typical specifications represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 Code = 0x7F. 4 Resistor terminals A and W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 7 All dynamic characteristics use VDD = 5 V. 2 Rev. 0 | Page 3 of 20 V pF pF nA V V V V µA pF V µA µW %/% MHz % µs nV/√Hz AD5246 ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS Table 2. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient RWB RESISTOR TERMINALS Voltage Range4 Capacitance5 B Capacitance5 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance5 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation6 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 7 Bandwidth –3 dB Total Harmonic Distortion VW Settling Time (10 kΩ/50 kΩ/100 kΩ) Resistor Noise Voltage Density Symbol Conditions Min Typ1 Max Unit R-DNL R-INL ∆RAB ∆RAB/∆T RWB RWB, VA = No Connect RWB, VA = No Connect TA = 25°C Wiper = No Connect Code=0x00, VDD = 5 V Code=0x00, VDD = 2.7 V –1 –2 –20 ±0.1 ±0.25 +1 +2 +20 LSB LSB % ppm/°C Ω Ω VB, W CB CW ICM VIH VIL VIH VIL IIL CIL 45 75 150 GND f = 1 MHz, Measured to GND, Code = 0x40 f = 1 MHz, measured to GND, Code = 0x40 VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 150 400 VDD 45 60 1 2.4 0.8 2.1 0.6 ±1 5 VDD RANGE IDD PDISS PSSR VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V ± 10%, Code = Midscale 2.7 3 BW THDW tS eN_WB RAB = 10 kΩ/50 kΩ/100 kΩ, Code = 0x40 VA =1 V rms, f = 1 kHz, RAB = 10 kΩ VA = 5 V ±1 LSB Error Band RWB = 5 kΩ, RS = 0 600/100/40 0.05 2 9 1 ±0.01 5.5 8 40 ±0.02 Typical specifications represent average readings at +25°C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 Code = 0x7F. 4 Resistor terminals A and W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 7 All dynamic characteristics use VDD = 5 V. 2 Rev. 0 | Page 4 of 20 V pF pF nA V V V V µA pF V µA µW %/% kHz % µs nV/√Hz AD5246 TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS Table 3. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted Parameter I2C INTERFACE TIMING CHARACTERISTICS2, 3 (Specifications Apply to All Parts) SCL Clock Frequency tBUF Bus Free Time between STOP and START tHD;STA Hold Time (Repeated START) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time for Repeated START Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals tR Rise Time of Both SDA and SCL Signals tSU;STO Setup Time for STOP Condition Symbol fSCL t1 t2 Conditions Min Typ1 Max Unit 400 kHz µs 1.3 After this period, the first clock pulse is generated. t3 t4 t5 t6 t7 t8 t9 t10 0.6 1.3 0.6 0.6 50 0.9 100 300 300 0.6 1 Typical specifications represent average readings at 25°C and VDD = 5 V. Guaranteed by design and not subject to production test. 3 See timing diagrams (Figure 25, Figure 26, Figure 27) for locations of measured values. 2 Rev. 0 | Page 5 of 20 µs µs µs µs µs ns ns ns µs AD5246 ABSOLUTE MAXIMUM RATINGS Table 4. TA = 25°C, unless otherwise noted1 Parameter VDD to GND VA, VW to GND Terminal Current, Ax–Bx, Ax–Wx, Bx–Wx Pulsed2 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance3 θJA: SC70-6 Value –0.3 V to +7 V VDD 1 ±20 mA ±5 mA 0 V to VDD + 0.3 V –40°C to +125°C 150°C –65°C to +150°C 300°C 340°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 3 Package power dissipation = (TJMAX – TA)/θJA. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 20 AD5246 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.5 TA = 25°C RAB = 10kΩ RHEOSTAT MODE DNL (LSB) VDD = 2.7V 0.4 0.2 0 VDD = 5.5V –0.2 –0.4 –0.6 03875-0-020 –0.8 0 16 64 80 48 CODE (Decimal) 32 96 112 0.2 TA = –40°C, +25°C, +85°C, +125°C 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 128 0 Figure 2. R-INL vs. Code vs. Supply Voltages RHEOSTAT MODEERROR INL (LSB) FSE, FULL-SCALE (LSB) 0.2 VDD = 2.7V 0.1 0 –0.1 VDD = 5.5V –0.2 –0.3 03875-0-021 RHEOSTAT MODE DNL (LSB) 0.3 –0.4 96 112 128 0 16 32 64 80 48 CODE (Decimal) 96 112 –0.5 VDD = 5.5V, VA = 5.5V –1.0 –1.5 –2.0 VDD = 2.7V, VA = 2.7V –2.5 –3.0 –40 128 Figure 3. R-DNL vs. Code vs. Supply Voltages –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 Figure 6. Full-Scale Error vs. Temperature 1.0 1.50 TA = +85°C 0.6 TA = –40°C 1.25 ZSE, ZERO-SCALE ERROR (LSB) 0.8 0.4 0.2 TA = +25°C 0 TA = +125°C –0.2 –0.4 TA = –40°C TA = +25°C –0.6 TA = +85°C –0.8 TA = +125°C 0 16 32 64 80 48 CODE (Decimal) 96 112 03875-0-022 RHEOSTAT MODE INL (LSB) 48 64 80 CODE (Decimal) 0 TA = 25°C RAB = 10kΩ 0.4 –1.0 32 Figure 5. R-DNL vs. Code vs. Temperature 0.5 –0.5 16 03875-0-024 –1.0 0.3 1.00 VDD = 5.5V, VA = 5.5V 0.75 0.50 0.25 VDD = 2.7V, VA = 2.7V 0 –40 –25 128 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 Figure 7. Zero-Scale Error vs. Temperature Figure 4. R-INL vs. Code vs. Temperature Rev. 0 | Page 7 of 20 03875-0-025 RHEOSTAT MODE INL (LSB) 0.6 VDD = 2.7V RAB = 10kΩ –40°C +25°C +85°C +125°C 0.4 03875-0-023 0.8 110 125 AD5246 100 0 GAIN (dB) 1 VDD = 2.7V 20 35 50 65 TEMPERATURE (°C) 80 95 0x04 –30 0x02 –36 0x01 110 03875-0-029 –48 –54 –60 1k 125 100k FREQUENCY (Hz) 10k 1M 10M Figure 11. Gain vs. Frequency vs. Code, RAB = 10 kΩ Figure 8. Supply Current vs. Temperature 500 0 VDD = 2.7V RAB = 10kΩ 300 0x20 –12 TA = –40°C to +85°C 0x10 –18 GAIN (dB) 100 0 –100 –200 0x08 –24 0x04 –30 0x02 –36 0x01 –42 TA = –40°C to +125°C –48 03875-0-027 –300 –400 0 16 32 48 64 80 CODE (Decimal) 96 112 –54 –60 1k 128 Figure 9. Rheostat Mode Tempco ∆RWB/∆T vs. Code –18 –24 –30 –36 10M 0x40 –6 0x20 0x20 –12 0x10 0x04 0x02 0x01 03875-0-028 1M 0x02 –36 –48 100k 0x04 –30 –48 –54 0x08 –24 –42 10k 0x10 –18 0x08 –42 –60 1k 1M 0 0x40 GAIN (dB) –12 100k FREQUENCY (Hz) Figure 12. Gain vs. Frequency vs. Code, RAB = 50 kΩ 0 –6 10k 0x01 03875-0-031 200 0x40 –6 03875-0-030 400 RHEOSTAT MODE TEMPCO (ppm/°C) 0x08 –24 –42 0.1 5 0x10 –18 VDD = 5.5V 0.01 –40 –25 –10 GAIN (dB) 0x20 –12 10 –500 0x40 –6 03875-0-026 IDD, SUPPLY CURRENT (µA) DIGITAL INPUTS = 0V CODE = 0x40 –54 –60 1k 10M FREQUENCY (Hz) Figure 10. Gain vs. Frequency vs. Code, RAB = 5 kΩ 10k 100k FREQUENCY (Hz) 1M Figure 13. Gain vs. Frequency vs. Code, RAB = 100 kΩ Rev. 0 | Page 8 of 20 10M AD5246 0 –6 –12 10kΩ –18 GAIN (dB) TA = 25°C RAB = 10kΩ FCLK = 100kHz VDD = 5.5V VB = 0V 5kΩ 100kΩ 50kΩ –24 VW –30 –36 5V –42 CLK 0V –54 –60 1k 10k 100k FREQUENCY (Hz) 1M 03875-0-006 03875-0-032 –48 10M 1µs/DIV Figure 14. –3 dB Bandwidth @ Code = 0x80 0.30 VDD = 5.5V VB = 0V CODE 0x40 to 0x3F B - VDD = 5.5V CODE = 0x7F 0.20 C - VDD = 2.7V CODE = 0x55 0.15 D - VDD = 2.7V CODE = 0x7F VW 0.10 A B C D 0 1k 10k 100k FREQUENCY (Hz) 03875-0-007 0.05 1M 200ns/DIV Figure 15. IDD vs. Frequency Figure 18. Midscale Glitch, Code 0x40 to 0x3F 360 TA = 25°C RAB = 50kΩ CODE = 0x00 300 VDD = 5.5V VB = 0V CODE 00H TO 7FH TA = 25°C RAB = 10kΩ IW = 50µA VDD = 2.7V 240 180 VW 120 1 VDD = 5.5V 60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 03875-0-005 0 03875-0-008 RWB (Ω) TA = 25°C RAB = 10kΩ 03875-0-033 IDD (µA) TA = 25°C A - VDD = 5.5V CODE = 0x55 0.25 Figure 17. Digital Feedthrough 5.5 40µs/DIV VBIAS (V) Figure 19. Large Signal Settling Time Figure 16. RWB vs. VBIAS vs. VDD Rev. 0 | Page 9 of 20 AD5246 TEST CIRCUITS Figure 20 to Figure 24 define the test conditions used in the product Specification tables. IW RSW = DUT W CODE = 0x00 W B B 03875-0-004 VMS 0.1V ISW 0.1V ISW 03876-0-029 DUT VDD TO GND Figure 20. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 23. Test Circuit for Incremental ON Resistance W V+ PSS (%/%) = B ∆V MS% DUT ∆V (∆V MS ) DD W ∆V DD% B 03875-0-009 VDD PSRR (dB) = 20 LOG VMS NO CONNECT ICM VCM 03875-0-012 V+ = VDD 10% DUT Figure 21. Test Circuit for Power Supply Sensitivity (PSS, PSSR) Figure 24. Test Circuit for Common-Mode Leakage Current DUT +15V 10kΩ W B 2.5V OP27 VOUT –15V 03875-0-010 VIN 10kΩ Figure 22. Test Circuit for Gain vs. Frequency Rev. 0 | Page 10 of 20 AD5246 I2C INTERFACE Table 5. Write Mode S 0 1 0 1 1 1 0 A W X D6 D5 D4 Slave Address Byte D3 D2 D1 D0 A P D2 D1 D0 A P Data Byte Table 6. Read Mode S 0 1 0 1 1 Slave Address Byte 1 0 R A 0 D6 D5 D4 D3 Data Byte S = Start Condition. W = Write. P = Stop Condition. R = Read. A = Acknowledge. D6, D5, D4, D3, D2, D1, D0 = Data Bits. X = Don’t Care. t8 t2 t9 SCL t6 t2 t3 t7 t4 t5 t10 t9 t8 t1 S S P Figure 25. I2C Interface, Detailed Timing Diagram 1 9 9 1 1 SCL 1 0 1 1 1 0 D6 D4 D5 ACK BY AD5246 FRAME 1 SLAVE ADDRESS BYTE START BY MASTER X R/W D3 D2 D1 D0 ACK BY AD5246 FRAME 2 DATA BYTE STOP BY MASTER 03875-0-014 0 SDA NO ACK BY MASTER STOP BY MASTER 03875-0-013 P Figure 26. Writing to the RDAC Register 1 9 1 9 SCL SDA START BY MASTER 0 1 0 1 1 1 FRAME 1 SLAVE ADDRESS BYTE 0 0 R/W D6 ACK BY AD5246 D5 D4 D2 FRAME 2 RDAC REGISTER Figure 27. Reading from the RDAC Register Rev. 0 | Page 11 of 20 D3 D1 D0 03875-0-019 SDA AD5246 OPERATION The AD5246 is a 128-position, digitally controlled variable resistor (VR) device. An internal power-on preset places the wiper at midscale during power-on, which simplifies the default condition recovery at power-up. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between terminals A and B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two or three digits of the part number determine the nominal resistance value, e.g., 10 kΩ = 10, 50 kΩ = 50. The nominal resistance (RAB) of the VR has 128 contact points accessed by the wiper terminal, plus the B terminal contact. The 7-bit data in the RDAC latch is decoded to select one of the 128 possible settings. Assuming a 10 kΩ part is used, the wiper’s first connection starts at the B terminal for data 0x00. Since there is a 50 Ω wiper contact resistance, such a connection yields a minimum of 100 Ω (2 × 50 Ω) resistance between terminals W and B. The second connection is the first tap point, which corresponds to 178 Ω (RWB = RAB/128 + RW = 78 Ω + 2 × 50 Ω) for data 0x01. The third connection is the next tap point, representing 256 Ω (2 × 78 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 Ω (RAB + 2 × RW). Figure 28 shows a simplified diagram of the equivalent RDAC circuit. Ax D6 D5 D4 D3 D2 D1 D0 The general equation determining the digitally programmed output resistance between W and B is RWB(D) = (1) where D is the decimal equivalent of the binary code loaded in the 7-bit RDAC register, RAB is the end-to-end resistance, and RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 10 kΩ and the A terminal is open-circuited, the output resistance RWB shown in Table 7 will be set for the indicated RDAC latch codes. Table 7. Codes and Corresponding RWB Resistance D (Dec.) 127 64 1 0 RWB (Ω) 10,100 5,100 178 100 Output State Full Scale (RAB + 2 × RW) Midscale 1 LSB Zero Scale (Wiper Contact Resistance) Note that in the zero-scale condition, a finite wiper resistance of 100 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Typical device-to-device matching is process lot dependent and may vary by up to ±30%. Since the resistance element is processed in thin film technology, the change in RAB with temperature has a very low 45 ppm/°C temperature coefficient. RS RS Wx RDAC Bx 03875-0-015 LATCH AND RS DECODER D × RAB + 2 × RW 128 Figure 28. AD5246 Equivalent RDAC Circuit Rev. 0 | Page 12 of 20 AD5246 I2C COMPATIBLE 2-WIRE SERIAL BUS The 2-wire I2C serial bus protocol operates as follows: A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing the part only once. For example, after the RDAC has acknowledged its slave address in write mode, the RDAC output will update on each successive byte. If different instructions are needed, write/read mode has to start again with a new slave address and data byte. Similarly, a repeated read function of the RDAC is also allowed. 1. LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE The first byte of the AD5246 is a slave address byte (see Table 5 and Table 6). It has a 7-bit slave address and a R/W bit. The seven MSBs of the slave address are 0101110 followed by 0 for a write command or 1 to place the device in read mode. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 26). The following byte is the slave address byte, which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. On the other hand, if the R/W bit is low, the master will write to the slave device. While most legacy systems may be operated at one voltage, a new component may be optimized at another. When two systems operate the same signal at two different voltages, proper level shifting is needed. For instance, one can use a 3.3 V E2PROM to interface with a 5 V digital potentiometer. A level shifting scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 29 shows one of the implementations. M1 and M2 can be any N channel signal FETs, or if VDD falls below 2.5 V, M1 and M2 can be low threshold FETs such as the FDV301N. VDD1 = 3.3V VDD2 = 5V RP RP RP RP G 4. In read mode, after acknowledgment of the slave address byte, data is received over the serial bus in sequences of nine clock pulses (a slight difference from the write mode where eight data bits are followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 27). D M1 SCL1 SDA2 G S D SCL2 M2 3.3V 5V AD5246 E2PROM 03875-0-011 S SDA1 Figure 29. Level Shifting for Operation at Different Potentials ESD PROTECTION All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 30 and Figure 31. This applies to the digital input pins SDA and SCL. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition (see Figure 26). In read mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse, which goes high to establish a STOP condition (see Figure 27). 340Ω LOGIC 03875-0-002 3. In write mode, after acknowledgement of the slave address byte, the next byte is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Table 5). GND Figure 30. ESD Protection of Digital Pins B,W GND 03875-0-003 2. Figure 31. ESD Protection of Resistor Terminals Rev. 0 | Page 13 of 20 AD5246 TERMINAL VOLTAGE OPERATING RANGE POWER-UP SEQUENCE The AD5246 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals B and W that exceed VDD or GND will be clamped by the internal forward biased diodes (see Figure 32). Since the ESD protection diodes limit the voltage compliance at terminals B and W (see Figure 32), it is important to power VDD/GND before applying any voltage to terminals B and W; otherwise, the diode will be forward biased such that VDD will be powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VB/VW. The relative order of powering VB and VW and the digital inputs is not important as long as they are powered after VDD/GND. VDD B LAYOUT AND POWER SUPPLY BYPASSING W Figure 32. Maximum Terminal Voltages Set by VDD and GND MAXIMUM OPERATING CURRENT At low code values, the user should be aware that due to low resistance values, the current through the RDAC may exceed the 5 mA limit. In Figure 33, a 5 V supply is placed on the wiper, and the current through terminals W and B is plotted with respect to code. A line is also drawn denoting the 5 mA current limit. Note that at low code values (particularly for the 5 kΩ and 10 kΩ options), the current level increases significantly. Care should be taken to limit the current flow between W and B in this state to a maximum continuous current of 5 mA and a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contacts can occur. Similarly, it is a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 34). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. VDD VDD C1 C3 + 0.1µF 10µF AD5246 GND 100.00 Figure 34. Power Supply Bypassing 5mA CURRENT LIMIT RAB = 5kΩ 1.00 RAB = 10kΩ RAB = 50kΩ 0.10 03875-0-034 IWB CURRENT (mA) 10.00 RAB = 100kΩ 0.01 0 16 32 64 80 48 CODE (Decimal) 96 112 128 Figure 33. Maximum Operating Current Rev. 0 | Page 14 of 20 03875-0-017 03875-0-016 GND It is a good practice to employ a compact, minimum lead-length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. AD5246 CONSTANT BIAS TO RETAIN RESISTANCE SETTING For users who desire nonvolatility but cannot justify the additional cost for the EEMEM, the AD5246 may be considered as a low cost alternative by maintaining a constant bias to retain the wiper setting. The AD5246 was designed specifically with low power in mind, which allows low power consumption even in battery-operated systems. The graph in Figure 35 demonstrates the power consumption from a 3.4 V 450 mAhr Li-ion cell phone battery, which is connected to the AD5246. The measurement over time shows that the device draws approximately 1.3 µA and consumes negligible power. Over a course of 30 days, the battery was depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself. 110% 108% TA = 25°C EVALUATION BOARD An evaluation board, along with all necessary software, is available to program the AD5246 from any PC running Windows® 98, Windows 2000, or Windows XP®. The graphical user interface, as shown in Figure 36 is straightforward and easy to use. More detailed information is available in the user manual, which comes with the board. 104% 102% 100% 98% 96% 94% 03875-0-035 92% 90% 0 5 10 15 DAYS 20 25 30 Figure 35. Battery Operating Life Depletion 03876-0-061 BATTERY LIFE DEPLETED 106% This demonstrates that constantly biasing the pot is not an impractical approach. Most portable devices do not require the removal of batteries for the purpose of charging. Although the resistance setting of the AD5246 will be lost when the battery needs replacement, such events occur rather infrequently such that this inconvenience is justified by the lower cost and smaller size offered by the AD5246. If and when total power is lost, the user should be provided with a means to adjust the setting accordingly. Figure 36. AD5246 Evaluation Board Software Rev. 0 | Page 15 of 20 AD5246 VDD 1 AD5246 6 B GND 2 TOP VIEW 5 W SCL 3 (Not to Scale) 4 SDA 03875-0-018 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 37. Pin Function Descriptions, 6-Lead SC70 Table 8. AD5246 Pin Function Descriptions Pin No. 1 2 3 Mnemonic VDD GND SCL 4 5 6 SDA W B Description Positive Power Supply. Digital Ground. Serial Clock Input. Positive edge triggered. Serial Data Input/Output. W Terminal. B Terminal. Rev. 0 | Page 16 of 20 AD5246 OUTLINE DIMENSIONS 2.00 BSC 6 5 4 1 2 3 2.10 BSC 1.25 BSC PIN 1 0.65 BSC 1.30 BSC 1.00 0.90 0.70 1.10 MAX 0.22 0.08 0.10 MAX 0.30 0.15 8° 4° 0° SEATING PLANE 0.46 0.36 0.26 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203AB Figure 38. 6-Lead Thin Shrink Small Outline Transistor [SC70] (KS-6) Dimensions shown in millimeters ORDERING GUIDE Model AD5246BKS5-R2 AD5246BKS5-RL7 AD5246BKS10-R2 AD5246BKS10-RL7 AD5246BKS50-R2 AD5246BKS50-RL7 AD5246BKS100-R2 AD5246BKS100-RL7 AD5246EVAL 1 RAB (kΩ) 5 5 10 10 50 50 100 100 See Note 1 Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 Evaluation Board Package Option KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options. Rev. 0 | Page 17 of 20 Branding D16 D16 D1D D1D D1C D1C D1A D1A AD5246 NOTES Rev. 0 | Page 18 of 20 AD5246 NOTES Rev. 0 | Page 19 of 20 AD5246 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03875–0–9/03(0) Rev. 0 | Page 20 of 20