19-0659; Rev 1; 1/08 KIT ATION EVALU E L B AVAILA 4V to 72V Input LDOs with Boost Preregulator Features The MAX5092A/MAX5092B/MAX5093A/MAX5093B lowquiescent-current, low-dropout (LDO) regulators contain simple boost preregulators operating at a high frequency. The devices seamlessly provide a preset 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B) LDO output voltage from an automotive cold-crank through load-dump (3.5V to 80V) input voltage conditions. The MAX5092_/MAX5093_ deliver up to 250mA with excellent load and line regulation. During normal operation, when the battery is healthy, the boost preregulator is completely turned off, reducing quiescent current to 65µA (typ). This makes the devices suitable for always-on power supplies. The buck-boost operation achieved by this combination of LDO and boost preregulator offers the advantage of using a single off-the-shelf inductor in place of the multiple-winding custom magnetics needed in typical single-ended primary inductor converter (SEPIC) and transformer-based flyback topologies. The high operating frequency of the boost regulator significantly reduces component size. The MAX5092_ integrates a blocking diode to further reduce the external component count. The boost preregulator output voltage is preset to 7V. Both LDO and boost output voltages are programmable using external resistors. The boost preregulator output voltage is adjustable up to 11V (MAX5092_), or up to 12V (MAX5093_). The LDO output voltage is adjustable from 1.5V to 9V (MAX5092_) or from 1.5V to 10V (MAX5093_). The devices feature a shutdown mode with 5µA (typ) shutdown current, a HOLD input to implement a self-holding circuit, and a power-on-reset output (RESET) with an externally programmable timeout period. Additional features include output overload, short-circuit, and thermal protection. The MAX5092_/MAX5093_ are available in a thermally enhanced, 16-pin 5mm x 5mm thin QFN package and can dissipate up to 2.7W at +70°C on a multilayer PC board (PCB). o Wide Operating Input Voltage Range: 3.5V to 72V with a 4V Startup Voltage o LDO Output Regulates to 5V Seamlessly from an Input Voltage of 3.5V to 72V o Up to 250mA Output Current o Preset 3.3V, 5V, or Externally Programmable LDO Output Voltage from 1.5V to 9V (MAX5092_) or from 1.5V to 10V (MAX5093_) o Preset 7V or Externally Programmable Boost Output Voltage Up to 11V (MAX5092_) or Up to 12V (MAX5093_) o 65µA Quiescent Current in LDO Mode (VIN ≥8V) o 5µA Shutdown Current o Power-On Reset (RESET) with Programmable Timeout Period o Output Short-Circuit and Thermal Protection o TQFN Package Capable of Dissipating Up to 2.7W at +70°C Industrial PKG CODE MAX5092AATE+ -40°C to +125°C 16 TQFN-EP* T1655-3 MAX5092BATE+ -40°C to +125°C 16 TQFN-EP* T1655-3 MAX5093AATE+ -40°C to +125°C 16 TQFN-EP* T1655-3 MAX5093BATE+ -40°C to +125°C 16 TQFN-EP* T1655-3 +Denotes lead-free package. *EP = Exposed pad. LX LX BSOUT TOP VIEW PGND_BST Pin Configuration 12 11 10 9 BSFB 13 VL 14 MAX5092_/ MAX5093_ CT 15 RESET 16 + IN 1 Typical Operating Circuit and Selector Guide appear at end of data sheet. PINPACKAGE 2 3 4 HOLD Automotive—ECU TEMP RANGE SGND Automotive—Body Electronics PART EN Applications Ordering Information 8 OUT 7 OUT_SENSE 6 SET 5 PGND_LDO THIN QFN (5mm x 5mm) ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5092/MAX5093 General Description MAX5092/MAX5093 4V to 72V Input LDOs with Boost Preregulator ABSOLUTE MAXIMUM RATINGS IN, EN, LX, BSOUT to SGND..................................-0.3V to +80V PGND_BST, PGND_LDO to SGND .......................-0.3V to +0.3V RESET, OUT, OUT_SENSE to SGND .....................-0.3V to +12V BSOUT to LX (MAX5092_)......................................-0.3V to +12V VL, SET, BSFB, SGND..............................................-0.3V to +6V HOLD to SGND….....................................-0.3V to (VOUT + 0.3V) CT to SGND.................................................-0.3V to (VVL + 0.3V) OUT Current (IOUT) Short Circuit to PGND_LDO, (VIN ≤ 28V) ..............................................................Continuous Note 1: As per JEDEC Standard 51 (Multilayer Board). RESET Sinking Current .........................................................5mA Continuous Power Dissipation (TA = +70°C) 16-Pin Thin QFN (derate 33.3mW/°C above +70°C)...............................................2666mW (Note 1) Operating Temperature Range .........................-40°C to +125°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = VEN = 14V, IOUT = 1mA, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA = TJ = -40°C to +125°C, unless otherwise noted. See Figures 4–7 as applicable. Typical specifications are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 72 V INPUT SUPPLY Input Voltage Range Internal Input Undervoltage Lockout Supply Current (Boost Converter Off) Supply Current (Boost Converter On) Shutdown Supply Current VIN (Note 3) 4 VUVLOF VIN falling 3.0 3.2 3.4 VUVLOR VIN rising 3.4 3.6 3.8 65 85 LDO mode, IOUT = 250mA 70 100 VIN = 5V 0.4 1.0 mA 6 10 µA IQ IS LDO mode, IOUT = 100µA ISHDN VEN ≤ +0.4V IBSOUT VIN = 4V TJ = -40°C to +125°C (Note 4) TJ = -40°C to +125°C (Note 4) V µA BOOST CONVERTER Minimum BSOUT Output Current 250 mA Boost Converter Enable Threshold VBST_EN VBSOUT – VOUT falling (Note 5) 1.7 2.0 2.3 V Boost Converter Disable Threshold VBST_DIS VBSOUT – VOUT rising (Note 5) 2.2 2.5 2.8 V Boost Converter Disable Hysteresis VBST_HYS BSOUT Output Voltage VBSOUT Maximum BSOUT Output Voltage VBSOUT(MAX) BSFB Regulation Voltage VBSFB BSFB Input Bias Current IBSFB Boost Internal Switch On-Resistance Boost Internal Switch Minimum Off-Time 2 VIN = 4V, BSFB = SGND, VOUT = 5V V 7.00 V MAX5092_ 11 MAX5093_ 12 1.18 RDS(ON) tOFF 0.5 0.80 1.24 V 1.30 V 100 nA 0.5 1.2 Ω 1 1.25 µs _______________________________________________________________________________________ 4V to 72V Input LDOs with Boost Preregulator (VIN = VEN = 14V, IOUT = 1mA, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA = TJ = -40°C to +125°C, unless otherwise noted. See Figures 4–7 as applicable. Typical specifications are at TA = +25°C.) (Note 2) PARAMETER Boost Internal Switch Maximum On-Time Internal Switch Current Limit SYMBOL tON-MAX ILIM Measured in steady-state condition MIN TYP MAX UNITS 1.80 2.25 2.70 µs 3.0 A 5 µs 1.5 Time from VBSOUT falling below regulation to switch on-time Boost Turn-On Response Time Internal Diode Forward Voltage Drop CONDITIONS VF 2 MAX5092_ only, IF = 1A 0.95 V LDO Guaranteed Output Current Output Voltage IOUT VBSOUT - VOUT = 2V (Note 6) Maximum Adjustable Output Voltage mA SET = SGND, MAX5092A/ MAX5093A 3.25 3.3 3.35 100µA ≤ IOUT ≤ 250mA 3.2 3.3 3.4 SET = SGND, MAX5092B/ MAX5093B IOUT = 1mA 4.900 5 5.075 100µA ≤ IOUT ≤ 250mA 4.85 5 5.10 VOUT Minimum Adjustable Output Voltage 250 IOUT = 1mA VADJMIN Boost operation, VIN = 4V, VBSOUT = 7V VADJMAX Boost operation, VIN = 4V 1.5 MAX5092_, VBSOUT = 11V 9 MAX5093_, VBSOUT = 12V 10 VADJ LDO operation, VIN ≥ VBST_DIS (boost converter off) (Note 7) Dropout Voltage ΔVDO IOUT = 250mA (Note 8) 0.9 Rising edge of VBSOUT to the rising edge of VOUT, RL = 500Ω, SET = SGND 200 ΔVOUT / ΔVIN Line Regulation SET Reference Voltage SET Input Bias Current Power-Supply Rejection Ratio Short-Circuit Current 1.5 MAX5092A/MAX5093A MAX5092B/MAX5093B ISET ISC V 1.6 V µs 0.5 mV/V 1.235 1.265 V 0.5 100 nA 0.2 0.6 mV/mA 1.6 1.205 IOUT = 1mA to 250mA f = 100Hz IOUT = 10mA, VBSOUT(AC) = 500mVP-P, VOUT = 5V 80 f = 1MHz IOUT = 10mA, VBSOUT(AC) = 500mVP-P, VOUT = 5V 60 PSRR 10.0 0.4 7V ≤ VIN ≤ 28V, ILOAD = 250mA VSET ΔVOUT / ΔIOUT Load Regulation 7V ≤ VIN ≤ 72V, ILOAD = 10mA V V Adjustable Output Voltage LDO Startup Response Time V dB 255 490 mA _______________________________________________________________________________________ 3 MAX5092/MAX5093 ELECTRICAL CHARACTERISTICS (continued) MAX5092/MAX5093 4V to 72V Input LDOs with Boost Preregulator ELECTRICAL CHARACTERISTICS (continued) (VIN = VEN = 14V, IOUT = 1mA, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA = TJ = -40°C to +125°C, unless otherwise noted. See Figures 4–7 as applicable. Typical specifications are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ENABLE, HOLD and RESET EN High Input Threshold ENH EN Low Input Threshold ENL EN Input Bias Current IEN HOLD Low Input Threshold VIL HOLD Release Voltage VIH 2.4 V 0.25 Regulator on, EN transition from high to low EN = low 0.4 V 2 µA 0.4 V VOUT 0.4 V HOLD Pullup Current IHOLD Internally connected to OUT RESET Voltage Threshold VRESET % of VOUT, VOUT falling RESET Threshold Hysteresis VRHYST % of VOUT RESET Output Low Voltage VRL ISINK = 1mA 0.4 V RESET Output High Leakage Current IRH V R ESET = 5V 1 µA 4 87 90 µA 92 2 % % RESET Output Minimum Timeout Period CCT not connected 25 µs EN to RESET Minimum Timeout Delay CCT not connected 260 µs Delay Comparator Threshold (Rising) VCTTH Delay Comparator Threshold Hysteresis VCTTH-HYS CT Charge Current ICT-CHG CT Discharge Current ICT-DIS Thermal Shutdown Temperature Threshold TJ(SHDN) Thermal Shutdown Temperature Hysteresis TJ(HYST) 1.205 1.24 1.265 100 1.5 Temperature rising 2 V mV 2.5 µA 5 mA 165 °C 20 °C Limits at -40°C are guaranteed by design and characterization; not production tested. Guaranteed minimum operating voltage is 3.5V on VIN falling only. Guaranteed by design and not production tested. The boost converter disable threshold (VBST_DIS) is a static measurement. Internal comparator delay may cause a higher disable level. Note 6: The continuous maximum output current from the LDO is guaranteed according to the maximum power dissipation imposed by the package thermal constraints. Note 7: Maximum output adjustable value is conditioned by the maximum adjustable BSOUT Output Voltage Range minus the maximum dropout across the pass transistor. Note 8: Dropout voltage is defined as (VBSOUT - VOUT) when VOUT is 2% below the value of VOUT for VBSOUT = VOUT + 2V. Note 2: Note 3: Note 4: Note 5: 4 _______________________________________________________________________________________ 4V to 72V Input LDOs with Boost Preregulator INPUT CURRENT (IIN) vs. INPUT VOLTAGE (MAX5092B) INPUT CURRENT (mA) 75 70 65 IOUT = 10mA IOUT = 10mA IOUT = 100μA 1 60 BOOST CONVERTER NOT SWITCHING, QUIESCENT SUPPLY CURRENT = IIN - IOUT 0.1 50 16 24 32 40 48 56 64 IOUT = 10mA 70 60 IOUT = 100μA 50 4.5 5.0 5.5 6.0 7.0 6.5 -40 -15 10 35 60 85 INPUT VOLTAGE (V) TEMPERATURE (°C) QUIESCENT SUPPLY CURRENT vs. TEMPERATURE (MAX5093B) SHUTDOWN SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5092B) SHUTDOWN SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5093B) 80 70 IOUT = 10mA 60 IOUT = 100μA 50 8 6 4 2 10 8 6 4 2 VEN = 0V VEN = 0V 40 0 0 -15 10 35 60 85 110 135 4 TEMPERATURE (°C) 14 24 34 44 54 64 74 4 14 24 34 44 54 64 74 INPUT VOLTAGE (V) INPUT VOLTAGE (V) SWITCHING WAVEFORMS VBSOUT PROGRAMMED < (VOUT + VBST_DIS) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5092B) MAX5092/93 toc08 MAX5092/93 toc07 10 SHUTDOWN SUPPLY CURRENT (μA) 135 MAX5092/93 toc06 10 SHUTDOWN SUPPLY CURRENT (μA) MAX5092/93 toc04 BOOST CONVERTER NOT SWITCHING, QUIESCENT SUPPLY CURRENT = IIN - IOUT -40 110 INPUT VOLTAGE (V) 100 90 80 40 4.0 72 SHUTDOWN SUPPLY CURRENT (μA) 8 BOOST CONVERTER NOT SWITCHING, QUIESCENT SUPPLY CURRENT = IIN - IOUT 90 BOOST CONVERTER SWITCHING MAX5092/93 toc05 55 QUIESCENT SUPPLY CURRENT (μA) 10 100 MAX5092/93 toc03 IOUT = 100μA MAX5092/93 toc02 85 80 100 MAX5092/93 toc01 QUIESCENT SUPPLY CURRENT (μA) 90 QUIESCENT SUPPLY CURRENT vs. TEMPERATURE (MAX5092B) QUIESCENT SUPPLY CURRENT (μA) QUIESCENT SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5092B) 8 5V (AC-COUPLED) VIN 1V/div 8.5V (AC-COUPLED) VBSOUT 2V/div 6 VOUT 100mV/div 4 ILX 2A/div VEN = 0V 2 -40 -15 10 35 60 85 110 VIN = 5V, IOUT = 100mA, VBSOUT PROGRAMMED TO 11V 135 5V (AC-COUPLED) 0 100μs/div TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX5092/MAX5093 Typical Operating Characteristics (VIN = VEN = 14V, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA = +25°C, unless otherwise noted.) (See Figures 4–7 as applicable.) Typical Operating Characteristics (continued) (VIN = VEN = 14V, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA = +25°C, unless otherwise noted.) (See Figures 4–7 as applicable.) LINE-TRANSIENT RESPONSE (VIN STEP FROM 3.5V TO 72V) LINE-TRANSIENT RESPONSE (VIN STEP FROM 4V TO 7V) MAX5092/93 toc09 MAX5092/93 toc10 IOUT = 250mA VOUT 50mV/div IOUT = 5mA VIN 50V/div 5V (AC-COUPLED) 72V 3.5V 7V VOUT 50mV/div VIN 1V/div 5V (AC-COUPLED) 4V 72V VBSOUT 50V/div 7V (AC-COUPLED) VBSOUT 1V/div 7V 200μs/div 40ms/div SWITCHING WAVEFORMS VBSOUT PROGRAMMED < (VOUT + VBST_DIS) LINE-TRANSIENT RESPONSE (VIN STEP FROM 3.5V TO 14V) MAX5092/93 toc12 MAX5092/93 toc11 5V (AC-COUPLED) VIN 1V/div VOUT 100mV/div 7V (AC-COUPLED) VBSOUT 2V/div 5V (AC-COUPLED) 14V VBSOUT 5V/div 5V (AC-COUPLED) VOUT 100mV/div 7V 14V VIN = 5V, IOUT = 100mA, VBSOUT PROGRAMMED TO 7V VIN 5V/div ILX 2A/div 3.5V 0 100μs/div 200μs/div LDO OUTPUT VOLTAGE vs. LDO LOAD CURRENT (MAX5092B) 600 400 200 5.10 5.05 TA = +25°C, VIN = 4V TA = +25°C, VIN = 14V 5.00 TA = -40°C, VIN = 4V TA = -40°C, VIN = 14V 4.95 VIN = 14V, IOUT = 10mA 10dB/div -70 4.90 0 TA = +135°C, VIN = 4V TA = +135°C, VIN = 14V 4.85 0 50 100 150 200 LDO LOAD CURRENT (mA) 6 TA = -40°C: CIN = 10μF, CBSOUT = 4.7μF, COUT = 10μF (CERAMIC) TA = +25°C, +135°C: CIN = 47μF, CBSOUT = 22μF (ELECTROLYTIC), COUT = 10μF (CERAMIC) MAX5092/93 toc15 0 MAX5092/93 toc14 800 5.15 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY PSRR (dB) 1000 LDO OUTPUT VOLTAGE (V) MAX5092/93 toc13 DROPOUT VOLTAGE (VBSOUT - VOUT) vs. LDO LOAD CURRENT DROPOUT VOLTAGE (mV) MAX5092/MAX5093 4V to 72V Input LDOs with Boost Preregulator 250 0 100 200 LDO LOAD CURRENT (mA) 300 100 1k 10k FREQUENCY (Hz) _______________________________________________________________________________________ 100k 1M 4V to 72V Input LDOs with Boost Preregulator POWER-SUPPLY REJECTION RATIO vs. FREQUENCY STARTUP THROUGH INPUT VOLTAGE MAX5092/93 toc17 MAX5092/93 toc16 0 IOUT = 250mA VIN = 8V, IOUT = 10mA VIN 10V/div 0V PSRR (dB) VBSOUT 10V/div 0V 10dB/div ILX 5A/div -70 0A VOUT 5V/div 100 1k 10k 100k 1M 0V 100μs/div FREQUENCY (Hz) SHUTDOWN THROUGH VIN STARTUP THROUGH ENABLE MAX5092/93 toc19 MAX5092/93 toc18 IOUT = 250mA VIN 10V/div 0V VBSOUT 10V/div VIN 10V/div 14V VBSOUT 10V/div 14V VOUT 5V/div 0V 0V ILX 1A/div 0A VOUT 5V/div 0V VEN 2V/div IOUT = 250mA 0V 200μs/div 2ms/div SHUTDOWN THROUGH ENABLE RESET TIMING RESPONSE MAX5092/93 toc20 MAX5092/93 toc21 VIN 10V/div 14V VBSOUT 10V/div 14V VOUT 2V/div IOUT = 250mA CT = 680pF 0V VRESET 2V/div VOUT 5V/div 0V 0V VEN 2V/div VEN 2V/div IOUT = 250mA 0V 0V 200μs/div 200μs/div _______________________________________________________________________________________ 7 MAX5092/MAX5093 Typical Operating Characteristics (continued) (VIN = VEN = 14V, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA = +25°C, unless otherwise noted.) (See Figures 4–7 as applicable.) Typical Operating Characteristics (continued) (VIN = VEN = 14V, CIN = 47µF, CBSOUT = 22µF, COUT = 10µF, CVL = 1µF, TA = +25°C, unless otherwise noted.) (See Figures 4–7 as applicable.) VOUT vs. TEMPERATURE (MAX5092B) VOUT vs. TEMPERATURE MAX5092/93 toc24 MAX5092/93 toc23 3.34 LDO LOAD-TRANSIENT RESPONSE (MAX5092B) 5.10 MAX5092/93 toc22 3.36 5.05 VOUT 50mV/div VOUT (V) VOUT (V) 3.32 3.30 (AC-COUPLED) 5.00 3.28 IOUT 100mA/div 4.95 IOUT = 10mA, R5 = 100kΩ, R4 = 165kΩ, FIGURE 6 4.90 3.24 -40 -15 10 35 60 0mA IOUT = 1mA, VSET = 0V 85 110 -40 135 -15 10 35 60 85 110 TEMPERATURE (°C) TEMPERATURE (°C) INPUT-VOLTAGE STEP RESPONSE ENABLE AND HOLD TIMING MAX5092/93 toc25 135 2ms/div INTERNAL BOOST DIODE FORWARD DROP (MAX5092) MAX5092/93 toc26 1500 MAX5092/93 toc27 3.26 IOUT = 5mA VOUT 20mV/div 5V (AC-COUPLED) V HOLD 5V/div 72V VIN 20V/div 0V 0V VOUT 5V/div DIODE VOLTAGE (mV) 1250 VEN 5V/div 1000 750 500 250 0V 3.5V VIN = 8V, BOOST CONVERTER NOT SWITCHING 0 200ms/div 0 200ms/div 0.5 1.0 1.5 2.0 2.5 3.0 DIODE CURRENT (A) 0.4 TA = +25°C: VIN = 3.5V VIN = 4V VIN = 5V 0.2 MAX5092/93 toc29 VIN = 3.5V 0.4 VIN = 5V 50 100 150 200 IOUT (mA) 250 300 350 30 25 20 15 5 0 0 0 TA = TJ = +125°C TA = TJ = -40°C 35 10 0.2 0 8 VIN = 4V 0.8 0.6 40 NUMBER OF UNITS 0.6 TA = +105°C: VIN = 4V VIN = 5V VIN = 3.5V 1.0 POWER LOSS (W) TA = +105°C: VIN = 3.5V VIN = 4V VIN = 5V 0.8 1.2 MAX5092/93 toc28 1.0 GROUND CURRENT DISTRIBUTION (162 UNITS TESTED) BOOST CONVERTER POWER LOSS (VBSOUT = 11V) 0 50 100 150 200 IOUT (mA) 250 300 350 52 54 56 58 60 62 IGND (μA) _______________________________________________________________________________________ 64 66 68 70 MAX5092/93 toc30 BOOST CONVERTER POWER LOSS (VBSOUT = 7V) POWER LOSS (W) MAX5092/MAX5093 4V to 72V Input LDOs with Boost Preregulator 4V to 72V Input LDOs with Boost Preregulator PIN NAME FUNCTION 1 IN Input Supply Voltage. Bypass IN to the power ground plane with a 47µF (low-ESR) aluminum electrolytic capacitor in parallel with a 1µF ceramic capacitor placed as close to the IC as possible. 2 EN Enable Input. Drive EN high to turn on the IC. Drive EN low to disable the IC. Connect EN directly to IN for always-on operation. 3 SGND Signal Ground. Connect SGND to the signal ground plane and the exposed paddle. Connect the power ground and signal ground plane together at the negative terminal of the input capacitor(s). 4 HOLD Output Hold. When HOLD is forced low, the regulator stores the on-state of the output, allowing the regulator to remain enabled even if EN is pulled low. To shut down the regulator, release HOLD after EN is pulled low. If HOLD is unused, either connect HOLD to OUT or leave unconnected. HOLD is internally connected to OUT through a 4µA pullup current. 5 PGND_LDO 6 7 8 LDO Power Ground. Connect PGND_LDO to the power ground plane. Connect the PGND_LDO ground and signal ground plane together. Feedback Input for the LDO. Connect SET directly to SGND to set the output voltage of the LDO to the preset voltage of 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B). Connect SET to the center tap of a resistor-divider connected between the LDO output and SGND to set the output voltage. VSET regulates to 1.24V when using an adjustable output. SET OUT_SENSE LDO Regulator Output Sense. Connect OUT_SENSE to OUT at the output capacitor near the load. LDO Regulator Output. Bypass OUT to the power ground plane with a 10µF ceramic capacitor. VOUT regulates to a preset voltage of 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B), or is adjustable from 1.5V to 9V (MAX5902_) or 1.5V to 10V (MAX5093_). OUT Boost Regulator Output Voltage. Bypass BSOUT to the PGND_BST ground plane with a 22µF (low-ESR) aluminum electrolytic capacitor in parallel with a 1µF ceramic capacitor placed as close to the IC as possible. Connect BSFB directly to SGND to regulate the BOOST output to a fixed voltage of 7V for VIN ≤ 7V. VBSOUT follows VIN for VBSOUT - VOUT > 2.5V (typ). VBSOUT is programmable up to 11V (MAX5092_) or 12V (MAX5093_) by connecting BSFB to the center tap of an external resistor-divider connected between the BOOST output and PGND_BST. 9 BSOUT 10, 11 LX 12 PGND_BST Boost Regulator Power Ground. Connect PGND_BST to the power ground plane. Connect the PGND_BST ground plane and the signal ground plane together at the negative terminal of the input capacitor(s). 13 BSFB Feedback Input for the Boost Regulator. Connect BSFB directly to SGND to set the boost regulator output voltage to 7V. Connect BSFB to the center tap of an external resistor-divider connected between BSOUT and SGND to set the output voltage. VBSFB regulates to 1.24V when using an adjustable output. 14 VL Internal Regulator Output for IC Supply. Bypass VL to SGND with a 1µF/6.3V ceramic capacitor placed as close to the IC as possible. VVL regulates to 5.5V with VBSOUT ≥ 5.5V. 15 CT RESET Timeout Programming Input. Connect a capacitor from CT to SGND to set the RESET timeout period. See the CT Capacitor Selection section. 16 RESET RESET Output. RESET is an open-drain output that goes high impedance when VOUT exceeds 92% of the output voltage threshold after a programmed time delay. RESET pulls low immediately once VOUT drops below 90% of the regulated LDO output voltage. — EP Exposed Paddle. Connect to the signal ground plane (SGND). Connect to a large-signal ground plane for increased thermal performance. Inductor Connection to the Drain of the Internal Power MOSFET. Connect LX to the switched side of the inductor. Connect pins 10 and 11 together as close to the device as possible. For the MAX5093, also connect LX to the anode of the external Schottky diode. _______________________________________________________________________________________ 9 MAX5092/MAX5093 Pin Description 4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093 Functional Diagrams IN 1μs ONE-SHOT MAX5092_ OUT VL VL INTERNAL LDO LX IN LX BSOUT S Q R Q DRIVER BSOUT CURRENT-LIMITING COMPARATOR R1 RS OUT BSFB VPK 2.25μs ONE-SHOT MUX IN R2 BSOUT VREF VDIS_TH LDO BST_DIS OUT OUT VREF OUT ERROR AMPLIFIER HOLD OUT_SENSE CONTROL LOGIC, THERMAL SHUTDOWN, AND OVERCURRENT PROTECTION EN R3 R4 VL MUX SET CT COMPARATOR 2μA CT DELAY COMPARATOR 0.92 x VREF SGND PGND_LDO PGND_BST P Figure 1. MAX5092_ Functional Diagram 10 ______________________________________________________________________________________ RESET 4V to 72V Input LDOs with Boost Preregulator IN 1μs ONE-SHOT MAX5093_ OUT VL VL INTERNAL LDO LX IN LX BSOUT S Q R Q DRIVER BSOUT CURRENT-LIMITING COMPARATOR R1 RS OUT BSFB VPK 2.25μs ONE-SHOT MUX IN R2 BSOUT VREF VDIS_TH LDO BST_DIS OUT OUT VREF OUT ERROR AMPLIFIER HOLD OUT_SENSE CONTROL LOGIC, THERMAL SHUTDOWN, AND OVERCURRENT PROTECTION EN R3 R4 VL MUX SET CT COMPARATOR 2μA CT DELAY COMPARATOR RESET 0.92 x VREF SGND PGND_LDO PGND_BST P Figure 2. MAX5093_ Functional Diagram ______________________________________________________________________________________ 11 MAX5092/MAX5093 Functional Diagrams (continued) MAX5092/MAX5093 4V to 72V Input LDOs with Boost Preregulator Detailed Description The MAX5092A/MAX5092B/MAX5093A/MAX5093B include a step-up, switch-mode DC-DC converter and a linear regulator to provide step-up/-down voltage conversion over a wide range of input voltages. This combination of an LDO and a boost converter offers the advantage of using a single off-the-shelf inductor in place of the multiple-winding custom magnetics needed in typical SEPIC or transformer-based flyback topologies. The boost preregulator is completely turned off during normal automotive operation (V IN = 14V), reduces quiescent current to 65µA (typ), and makes the devices suitable for always-on power supplies. The devices have an internal UVLO threshold of 3.8V (max, VIN rising) that must be exceeded before the device is enabled. When VIN is above VUVLO, the internal boost converter starts switching and regulates VBSOUT to the programmed boost output voltage. The low quiescent-current LDO steps down VBSOUT to the programmed LDO output voltage. The LDO output is preset to 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B). Both output voltages can be adjusted by using external resistor-dividers. If (VBSOUT - VOUT) rises above 2.5V (typ), the boost converter is disabled, forcing V BSOUT to follow V IN . If VBSOUT - VOUT falls below 2V (typ), the boost converter starts switching and regulates V BSOUT to the programmed voltage. The boost converter regulates VBSOUT for VIN down to 3.5V, providing uninterrupted operation during low cold-crank voltages even if the programmed LDO output voltage is greater than VIN (but less than 9V). The boost converter turn-on response time is less than 10µs, making cold-crank input glitches transparent to the system even at full load. The boost-converter output is followed by a high PSRR, low-quiescent-current LDO. The LDO rejects the switching noise present at BSOUT and provides a clean, regulated output voltage. The linear regulator uses an internal p-channel MOSFET pass element. Additional features include a power-on-reset function with an externally adjustable timeout, an enable (EN) input, and a hold (HOLD) regulator control input. Boost Converter The switch-mode converter uses a minimum off-time, maximum on-time pulse frequency modulation (PFM) control scheme. The internal MOSFET turns on whenever VBSOUT falls below the regulation point determined by VBSFB (see the Setting the Boost Output Voltage 12 (VBSOUT) section). The MOSFET turns off when the inductor current reaches the peak current limit (2.5A typ) or after 2.25µs maximum on-time, whichever occurs first. The MOSFET is held off for at least 1µs after the turn-on phase. A new switching cycle initiates once VBSOUT falls below the threshold. In this control scheme, switching frequency and output ripple are functions of load current and input voltage. No frequency compensation is needed in the PFM control scheme. The output of the boost converter is preset to 7V and is adjustable by using external resistors. See the Setting the Boost Output Voltage VBSOUT section. If V BSOUT is programmed greater than (V OUT + VBST_DIS), larger ripple is observed on BSOUT. The reason is as VBSOUT rises above VOUT + VBST_DIS, the boost converter is disabled, causing VBSOUT to fall. As VBSOUT falls to VOUT + VBST_EN, the boost converter turns back on, and VBSOUT rises. For the lowest VBSOUT ripple, program VBSOUT within the boost disable threshold. See the Typical Operating Characteristics for the Switching Waveforms. Due to the integrated blocking diode in the MAX5092_, VBSOUT is limited to 11V. Use the MAX5093_ for higher boost output voltages (or to reduce the power dissipation in to the package). The MAX5093_ requires an external diode for the boost converter. Select the external diode according to the Schottky Diode Selection (MAX5093_) section. Linear Regulator The MAX5092_/MAX5093_ contain an internal p-channel MOSFET used as the pass transistor for the LDO. The output of the boost regulator is connected to the source of the p-MOSFET. The LDO starts up 200µs after the boost regulator starts up. The LDO supplies up to 250mA with a typical dropout voltage of 0.9V. The maximum LDO output current is determined by the package power-dissipation limit as well as the internal current limit. The LDO is designed to be a low-quiescent-current type. During normal operation when the battery voltage is > 9V, the MAX5092_/MAX5093_ consume only 75µA (max) at +85°C and 100µA load. The output voltage of the LDO is set using the SET input. Connect SET to SGND to use the factory-preset output voltage. Connect SET to the center of an external resistor-divider connected from OUT to SGND to program a different output voltage. See the Setting the LDO Output Voltage (VOUT) section. ______________________________________________________________________________________ 4V to 72V Input LDOs with Boost Preregulator Enable and Hold Inputs The MAX5092_/MAX5093_ utilize two logic inputs, EN (active-high) and HOLD (active low), to implement a self-holding circuit with no additional components. For example, an automotive ignition switch drives EN high and the regulator turns on. If HOLD is then driven low, the regulator remains on even if EN goes low. As long as HOLD is forced low and remains low after initial regulator power-up, the regulator remains on. From this state, release HOLD (an internal current source connects HOLD to OUT), or connect HOLD to OUT to turn the regulator off. Drive EN low and HOLD high to place the IC into shutdown mode. Shutdown mode reduces supply current to 5µA. Figure 3 shows the timing diagram for the enable and hold functions. Table 1 shows the state of the regulator output with respect to the voltage level at EN and HOLD with reference to Figure 3. Connect HOLD to OUT or leave unconnected to disable the hold feature and use EN as a standard on/off control input. Power-On-Reset Output (RESET) The MAX5092_/MAX5093_ contain an open-drain output (RESET) that indicates when the LDO output (VOUT) is out of regulation. If the output of the LDO falls below 90% of the nominal output voltage, RESET pulls low after a short delay. Once the output rises above 92% of the nominal output voltage, RESET goes high impedance after the programmed reset timeout period. Connect a 100kΩ pullup resistor from OUT to RESET. See the CT Capacitor Selection section for details on setting the RESET timeout period. HOLD EN OUT ORDER 1 2 4 3 5 6 Figure 3. Enable and Hold Timing Diagram Table 1. Truth Table for Enable and Hold Timing Diagram ORDER EN HOLD OUT COMMENTS Initial State. EN has a 500nA pulldown to GND. HOLD has an internal current source to OUT. HOLD follows OUT. Regulator output is active when EN is pulled high. HOLD is in release state, and it follows OUT. HOLD is in release state. OUT follows EN. 1 Low X Off 2 High Released On 3 Low Released Off 4 High Low On HOLD is pulled low externally after OUT turns on. The regulator output is forced on regardless of the state of EN. A self-holding state. 5 Low Released Off HOLD is released after EN is pulled low. Output turns off. 5 High X On Regulator enabled. Normal turn-on behavior. Regulator follows EN and HOLD follows OUT. ______________________________________________________________________________________ 13 MAX5092/MAX5093 Internal Regulator (VL) An internal regulator (VL) is used to supply all internal low-voltage blocks. Bypass VL to SGND with a 1µF ceramic capacitor placed as close to the IC as possible. VVL regulates to 5.5V when VBSOUT is above 5.5V. V VL tracks the voltage at BSOUT when V BSOUT is below 5.5V. 4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093 Applications Information L1 4.7μH 10 INPUT 4V TO 72V 11 LX 1 C1* 47μF LX VL IN C2* 1μF 14 C6 1μF U1 MAX5092B VOUT BSOUT R1 100kΩ 16 RESET PGND_BST RESET BSFB 7V 9 12 C3* 1μF C4* 22μF 13 ON 2 OFF 3 EN HOLD OUT CT C5 0.22μF *** μP SIGNAL SGND OUT_SENSE 15 4 PGND_LDO SET 7 OUTPUT 5V AT 250mA** 8 5 6 C7 10μF VOUT P P *THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE. **OUTPUT CURRENT IS LIMITED BY THE TOTAL POWER-DISSIPATION CAPABILITY OF THE PACKAGE. ***SEE PCB LAYOUT GUIDELINES SECTION. Figure 4. MAX5092B Typical Application Circuit with Factory Preprogrammed LDO and Boost Output Voltages 14 ______________________________________________________________________________________ 4V to 72V Input LDOs with Boost Preregulator L1 4.7μH 10 INPUT 4V TO 72V 11 LX 1 C1* 47μF LX VL IN C2* 1μF 14 C6 1μF U1 MAX5093B VOUT BSOUT R1 100kΩ 16 RESET PGND_BST RESET BSFB 9 7V 12 C4* 22μF C3* 1μF 13 ON 2 OFF 3 EN HOLD μP SIGNAL SGND OUT_SENSE OUT 15 4 CT C5 0.22μF *** PGND_LDO SET 7 OUTPUT 5V AT 250mA** 8 5 6 C7 10μF VOUT P P *THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE. **OUTPUT CURRENT IS LIMITED BY THE TOTAL POWER-DISSIPATION CAPABILITY OF THE PACKAGE. ***SEE PCB LAYOUT GUIDELINES SECTION. Figure 5. MAX5093B Typical Application Circuit with Factory Preprogrammed Boost and LDO Output Voltages ______________________________________________________________________________________ 15 MAX5092/MAX5093 Applications Information (continued) 4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093 Applications Information (continued) L1 4.7μH 10 INPUT 4V TO 72V 11 LX 1 C1* 47μF LX VL IN C2* 1μF 14 5.5V C6 1μF U1 MAX5092A VOUT BSOUT R3 100kΩ 16 RESET PGND_BST OUTPUT 5.3V 9 12 C4* 22μF C3* 1μF R1 1.65MΩ RESET BSFB 13 ON 2 OFF 3 EN HOLD OUT CT C5 0.22μF *** μP SIGNAL R2 499kΩ VOUT SGND OUT_SENSE 15 4 PGND_LDO SET 7 OUTPUT 3.3V** 8 5 6 C7 10μF P P *THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE. **OUTPUT CURRENT IS LIMITED BY THE TOTAL OUTPUT POWER AND THE DISSIPATION CAPABILITY OF THE PACKAGE. ***SEE PCB LAYOUT GUIDELINES SECTION. Figure 6. MAX5092A Typical Application Circuit with User-Programmed LDO and Boost Output Voltages 16 ______________________________________________________________________________________ 4V to 72V Input LDOs with Boost Preregulator L1 4.7μH 10 INPUT 4V TO 72V 11 LX 1 C1* 47μF LX VL IN C2* 1μF 14 C6 1μF U1 MAX5093A VOUT BSOUT R3 100kΩ 16 RESET PGND_BST OUTPUT 12V 9 12 C4* 22μF C3* 1μF R1 4.32MΩ RESET BSFB 13 ON 2 OFF 3 EN HOLD OUT CT C5 0.22μF *** μP SIGNAL R2 499kΩ VOUT SGND OUT_SENSE 15 4 PGND_LDO SET 7 OUTPUT 10V** 8 5 C7 10μF R4 698kΩ 6 P R5 100kΩ *THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE. **OUTPUT CURRENT IS LIMITED BY THE TOTAL OUTPUT POWER AND THE DISSIPATION CAPABILITY OF THE PACKAGE. ***SEE PCB LAYOUT GUIDELINES SECTION. Figure 7. MAX5093A Typical Application Circuit with User-Programmable Boost Output Voltage and LDO Output Voltage ______________________________________________________________________________________ 17 MAX5092/MAX5093 Applications Information (continued) MAX5092/MAX5093 4V to 72V Input LDOs with Boost Preregulator Design Guidelines Input Capacitor (CIN) and Boost Capacitor (CBSOUT) Selection The input current waveform of the boost converter is continuous, and usually does not demand high capacitance at its input. However, the MAX5092_/MAX5093_ boost converter is designed to fully turn on as soon as the input drops below a certain voltage in order to ride out cold-crank droops. This operation demands low input source impedance for proper operation. If the source (battery) is located far from the IC, high-capacity, low-ESR capacitors are recommended for CIN. The worst-case peak capacitor current could be as high as 3A. Use a 47µF, 100mΩ low-ESR capacitor placed as close as possible to the input of the device. Note that the aluminum electrolytic capacitor ESR increases significantly at cold temperatures. In the cold temperature case, choose an electrolyte capacitor with ESR lower than 40mΩ or connect a low-ESR ceramic capacitor (10µF) in parallel with the electrolytic capacitor. The boost converter output (BSOUT) is fed to the input of the internal 250mA LDO. The boost-converter output current waveform is discontinuous and requires highcapacity, low-ESR capacitors at BSOUT to ensure low VBSOUT ripple. During the on-time of the internal MOSFET, the BSOUT capacitor supplies 250mA current to the LDO input. During the off-time, the inductor dumps current into the output capacitor while supplying the output load current. The internal 250mA LDO is designed with high PSRR; however, high-frequency spikes may not be rejected by the LDO. Thus, high-value, low-ESR electrolytic capacitors are recommended for C BSOUT . Peak-to-peak VBSOUT ripple depends on the ESR of the electrolyte capacitor. Use the following equation to calculate the required ESR (ESR BSOUT) of the BSOUT capacitor: ESRBSOUT = 18 ΔVESRBS ILIM − IOUT where ΔVESRBS is 75% of total peak-to-peak ripple at BSOUT, ILIM is the internal switch current limit (3A max), and IOUT is the LDO output current. Use a 100mΩ or lower ESR electrolytic capacitor. Make sure the ESR at cold temperatures does not cause excessive ripple voltage. Alternately, use a 10µF ceramic capacitor in parallel with the electrolyte capacitor. During the switch on-time, the BSOUT capacitor discharges while supplying IOUT. The ripple caused by the capacitor discharge (ΔVCBS) is estimated by using the following equation: I × 2.7 × 10−6 ΔVCBS = OUT CBSOUT where IOUT is the LDO output current and CBSOUT is the BSOUT capacitance. Inductor Selection The control scheme of the MAX5092/MAX5093 permits flexibility in choosing an inductor value. Smaller inductance values typically offer smaller physical size for a given series resistance, allowing the smallest overall circuit dimensions. Circuits using larger inductance may provide higher efficiency and exhibit less ripple, but also may reduce the maximum output current. This occurs when the inductance is sufficiently large to prevent the LX current limit (I LIM ) from being reached before the maximum on-time (tON-MAX) expires. For maximum output current, choose the inductor value so that the controller reaches the current limit before the maximum on-time is reached: V ×t − L ≤ IN ON MAX ILIM where tON-MAX is typically 2.25µs, and the current limit (I LIM ) is a maximum of 3A (see the Electrical Characteristics). Choose an inductor with the maximum saturation current (ISAT) greater than 3A. ______________________________________________________________________________________ 4V to 72V Input LDOs with Boost Preregulator The MAX5092_/MAX5093_ feature Dual Mode™ operation for the internal boost converter output voltage. These devices operate in a preset output-voltage mode or an adjustable output-voltage mode. In preset mode, internal trimmed feedback resistors set VBSOUT to a fixed 7V. Select the preset mode by directly connecting BSFB to SGND (Figures 4 and 5). Ensure a low-impedance path between BSFB and SGND to limit the transient at BSFB to below 100mV. In adjustable mode, connect BSFB to the center tap of an external resistordivider connected between BSOUT and SGND to program VBSOUT (Figures 6 and 7). Program (VBSOUT < VOUT + VBST_DIS) for lower VBSOUT ripple. Note that the current drawn by the resistor-divider at BSOUT adds to the quiescent current and the shutdown current of the IC. Use the resistor-divider only if VBSOUT is required to be significantly different than 7V. Select 499kΩ or lower resistance value for the bottom resistor (R2) of the divider connected to SGND. The top resistor (R1) value is calculated as: ⎛V ⎞ R1 = R2 × ⎜ BSOUT − 1⎟ ⎝ VBSFB ⎠ where VBSFB is the regulation voltage at BSFB (1.24V typ) and V BSOUT is the desired output voltage for BSOUT. Setting the LDO Output Voltage (VOUT) The LDO output voltage is also Dual Mode (preset and adjustable). Preset mode is selected by connecting SET to SGND (Figures 4 and 5). In preset mode, VOUT regulates to 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B) by internal trimmed feedback resistors. Adjustable mode is selected by connecting SET to the center tap of an external resistor-divider connected between OUT and SGND (Figures 6 and 7). Note that the current drawn by the resistor-divider at OUT adds to the quiescent current of the LDO. Use the resistor-divider only if VOUT is required to be significantly different than the preset voltage. Select 100kΩ or lower value for the bottom resistor (R5) of the divider connected to SGND. The top resistor (R4) value is calculated as: Schottky Diode Selection (MAX5093_) The MAX5093_ requires an external diode connected between LX and BSOUT (Figures 5 and 7). Proper selection of an external diode can offer a lower forwardvoltage drop and a higher reverse-voltage handling capability. Since the high switching frequency of the IC demands a high-speed rectifier, Schottky diodes are recommended for most applications because of their fast recovery time and low forward-voltage drop. Ensure that the diode’s peak current rating is greater than or equal to the peak current limit of internal boost converter MOSFET. A diode average forward current rating of at least 1A is recommended. Additionally, the diode reverse breakdown voltage must be greater than the worst-case load-dump-condition voltage. CT Capacitor Selection The MAX5092_/MAX5093_ contain an open-drain power-on-reset output (RESET) that indicates when the LDO output voltage (VOUT) is out of regulation. When VOUT rises above 92% of the nominal output voltage, RESET goes high impedance after a user-programmable time delay. This time duration is programmable by a capacitor (CCT) from CT to SGND (Figures 4–7). For a chosen RESET active timeout period (tDELAY), calculate the required capacitor value as: CCT = 2 × 10 −6 × tDELAY 1.24 When VOUT drops below 90% of the LDO output regulation voltage, a 5mA pulldown current from CT to SGND discharges CCT. The time required to discharge CT determines the delay necessary to pull RESET low. This delay provides glitch immunity to the RESET function. The glitch immunity delay is directly proportional to the CT capacitor and is approximately 70µs for a 0.1µF capacitor at CT. ⎛V ⎞ R4 = R5 × ⎜ OUT − 1⎟ V ⎝ SET ⎠ where VSET is the regulation voltage at SET (1.24V typ) and VOUT is the desired output voltage for the LDO output. Dual Mode is a trademark of Maxim Integrated Products, Inc. ______________________________________________________________________________________ 19 MAX5092/MAX5093 Setting the Boost Output Voltage (VBSOUT) MAXIMUM POWER DISSIPATION vs. AMBIENT TEMPERATURE MAX5092/93 fig08 3.0 MAXIMUM POWER DISSIPATION (W) MAX5092/MAX5093 4V to 72V Input LDOs with Boost Preregulator 2.5 2.0 1.5 PCB Layout Guidelines 1.0 0.5 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 AMBIENT TEMPERATURE (°C) Figure 8. MAX5092/MAX5093 Package Power Dissipation Maximum Output Current (IOUT_MAX) The MAX5092_/MAX5093_ high input voltage (+72V max) provides up to 250mA of current from OUT. Package power-dissipation limits the amount of output current available for a given input/output voltage and ambient temperature. Figure 8 depicts the maximum power-dissipation curve for the devices. The graph assumes that the exposed metal pad of the IC package is soldered to the PCB copper according to the JEDEC 51 standard (multilayer board). Use Figure 8 to determine the allowable package dissipation for a given ambient temperature. Alternately, use the following formula to calculate the allowable package dissipation (PDISS) in watts: For TA ≤ +70°C: PDISS = 2.67 For +70°C < TA ≤ +125°C: PDISS = 2.67 - (0.0333 x (TA - 70)) where +70°C < TA ≤ +125°C and 0.0333W/°C is the package thermal derating. After determining the allowable package dissipation, calculate the maximum output current (IOUT_MAX) using the following formula: IOUT _ MAX = PDISS − PLOSS(BST) VIN − VOUT where PDISS is the allowable package power dissipation and PLOSS(BST) is the boost converter power loss. 20 PDISS includes the losses in the boost converter operation and the LDO itself. The boost converter loss PLOSS(BST), depends on VIN, VBSOUT, and IOUT. See the Boost Converter Power Loss graphs in the Typical Operating Characteristics to estimate the losses at a given VIN and VBSOUT at room temperature. At a higher ambient temperature of +105°C, PLOSS(BST) increases by up to 20% due to higher RDS-ON and switching losses of the internal boost converter MOSFET. (Note: IOUT_MAX must be less than 250mA). Good PCB layout and routing are required in high-frequency switching power supplies to achieve proper regulation and stability. It is strongly recommended that the evaluation kit PCB layouts be followed as closely as possible. Refer to the MAX5092 EV kit for an example layout. Follow these guidelines for good PCB layout: 1) For SGND, use a large copper plane under the IC and solder it to the exposed paddle. To effectively use this copper area as a heat exchanger between the PCB and ambient, expose this copper area on the top and bottom side of the PCB. Do not make a direct connection from the EP copper plane to pin 3 (SGND) underneath the IC so as to minimize ground bounce. 2) Isolate the power components and high-current path from the sensitive analog circuit. 3) Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. 4) Connect the return terminals of input capacitors and boost output capacitors to the PGND_BST power ground plane. Connect the power ground (PGND_BST) and signal ground (SGND) planes together at the negative terminal of the input capacitors. Do not connect them anywhere else. Connect PGND_LDO ground plane to SGND ground plane at a single point. 5) Ensure that the feedback connections are short and direct. Ensure a low-impedance path between BSFB and SGND to limit the transient at BSFB to 100mV. 6) Route high-speed switching nodes away from the sensitive analog areas. Use the internal PCB layer for SGND as an EMI shield to keep radiated noise away from the IC, feedback dividers, and bypass capacitors. ______________________________________________________________________________________ 4V to 72V Input LDOs with Boost Preregulator INPUT 4V TO 72V LX LX VL IN MAX5092B VOUT +7V OUTPUT BSOUT PGND_BST RESET OUTPUT RESET BSFB ENABLE EN HOLD SGND OUT_SENSE +5V OUTPUT VOUT OUT * CT PGND_LDO P SET P *SEE PCB LAYOUT GUIDELINES SECTION. Selector Guide PART PRESET LDO OUTPUT (V) ADJUSTABLE LDO OUTPUT PRESET BSOUT OUTPUT (V) ADJUSTABLE BSOUT OUTPUT BOOST DIODE MAX5092AATE+ 3.3 Yes 7 Yes Internal MAX5092BATE+ 5 Yes 7 Yes Internal MAX5093AATE+ 3.3 Yes 7 Yes External MAX5093BATE+ 5 Yes 7 Yes External Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 21 MAX5092/MAX5093 Typical Operating Circuit Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) QFN THIN.EPS MAX5092/MAX5093 4V to 72V Input LDOs with Boost Preregulator 22 ______________________________________________________________________________________ 4V to 72V Input LDOs with Boost Preregulator ______________________________________________________________________________________ 23 MAX5092/MAX5093 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX5092/MAX5093 4V to 72V Input LDOs with Boost Preregulator Revision History REVISION NUMBER REVISION DATE 0 10/06 Initial release 1 1/08 Updated Ordering Information and Electrical Characteristics table, added two tocs, updated Functional Diagrams and Applications Diagrams, added boost converter details DESCRIPTION PAGES CHANGED — 1–12, 14–17, 19, 22, 23 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.