19-1481; Rev 1; 7/02
KIT
ATION
EVALU
E
L
B
A
AVAIL
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
This device offers three fully differential input channels
that may be independently programmed with a gain
between +1V/V and +128V/V. Furthermore, it can compensate an input-referred DC offset up to 117% of the
selected full-scale range. These three differential channels may also be configured to operate as five pseudodifferential input channels. Two additional, fully
differential system-calibration channels are provided for
gain and offset error correction.
The MAX1403 can be configured to sequentially scan all
signal inputs and provide the results via the serial interface with minimum communications overhead. When
used with a 2.4576MHz or 1.024MHz master clock, the
digital decimation filter can be programmed to produce
zeros in its frequency response at the line frequency and
associated harmonics, ensuring excellent line rejection
without the need for further postfiltering.
Features
♦ 18-Bit Resolution, Sigma-Delta ADC
♦ 16-Bit Accuracy with No Missing Codes to 480sps
♦ Matched On-Board Current Sources (200µA) for
Sensor Excitation
♦ Low Quiescent Current
250µA (operating mode)
2µA (power-down mode)
♦ 3 Fully Differential or 5 Pseudo-Differential Signal
Input Channels
♦ 2 Additional, Fully Differential Calibration
Channels/Auxiliary Input Channels
♦ Programmable Gain and Offset
♦ Fully Differential Reference Inputs
♦ Converts Continuously or On Command
♦ Automatic Channel Scanning and Continuous
Data Output Mode
♦ Operates with Analog and Digital Supplies
from +2.7V to +3.6V
♦ SPI™/QSPI™-Compatible 3-Wire Serial Interface
♦ 28-Pin SSOP Package
Pin Configuration
The MAX1403 is available in a 28-pin SSOP package.
TOP VIEW
CLKIN 1
Applications
28 SCLK
CLKOUT 2
27 DIN
CS 3
Portable Industrial Instruments
26 DOUT
RESET 4
Portable Weigh Scales
25 INT
DS1 5
Loop-Powered Systems
DS0 6
Pressure Transducers
Ordering Information
24 VDD
MAX1403
23 DGND
OUT2 7
22 CALOFF+
OUT1 8
21 CALOFF-
AGND 9
20 REFIN+
V+ 10
19 REFIN-
PIN-PACKAGE
AIN1 11
18 CALGAIN+
MAX1403CAI
0°C to +70°C
28 SSOP
AIN2 12
17 CALGAIN-
MAX1403EAI
-40°C to +85°C
28 SSOP
AIN3 13
16 AIN6
AIN4 14
15 AIN5
PART
TEMP RANGE
SPI and QSPI are trademarks of Motorola, Inc.
SSOP
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1403
General Description
The MAX1403 18-bit, low-power, multichannel, serialoutput analog-to-digital converter (ADC) features
matched 200µA current sources for sensor excitation.
This ADC uses a sigma-delta modulator with a digital
decimation filter to achieve 16-bit accuracy. The digital
filter’s user-selectable decimation factor allows the conversion resolution to be reduced in exchange for a
higher output data rate. True 16-bit performance is
achieved at an output data rate of up to 480sps. In
addition, the modulator sampling frequency may be
optimized for either lowest power dissipation or highest
throughput rate. The MAX1403 operates from +3V.
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
ABSOLUTE MAXIMUM RATINGS
Maximum Current Input into Any Pin ..................................50mA
Continuous Power Dissipation (TA = +70°C)
28-Pin SSOP (derate 9.52mW/°C above +70°C) ........524mW
Operating Temperature Ranges
MAX1403CAI .....................................................0°C to +70°C
MAX1403EAI...................................................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
V+ to AGND, DGND .................................................-0.3V to +6V
VDD to AGND, DGND ...............................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
Analog Inputs to AGND................................-0.3V to (V+ + 0.3V)
Analog Outputs to AGND .............................-0.3V to (V+ + 0.3V)
Reference Inputs to AGND...........................-0.3V to (V+ + 0.3V)
CLKIN and CLKOUT to DGND...................-0.3V to (VDD + 0.3V)
All Other Digital Inputs to DGND..............................-0.3V to +6V
All Digital Outputs to DGND .......................-0.3V to (VDD + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Noise-Free Resolution
No missing codes guaranteed by design;
for filter settings with FS1 = 0
Output Noise
Depends on filter setting and selected gain
Integral Nonlinearity
(Note 1)
Bipolar mode; FS1 = 0; MF1, MF0 = 0
INL
16
(Tables 16a, 16b)
-0.0015
FS1 = 0; MF1, MF0 = 1, 2, 3
Unipolar Offset Drift
Positive Full-Scale Error
(Note 3)
Full-Scale Drift (Note 4)
Gain Error (Note 5)
Gain-Error Drift (Note 6)
Bipolar Negative Full-Scale Error
Bipolar Negative Full-Scale Drift
2
%FSR
0.98
Relative to nominal of 1% FSR
-1
2
For gains of 1, 2, 4
0.5
For gains of 8, 16, 32, 64, 128
0.3
Bipolar Zero Error
Bipolar Zero Drift
0.0015
±0.001
Nominal Gain (Note 2)
Unipolar Offset Error
Bits
-2.0
µV/°C
2.0
For gains of 1, 2, 4
0.8
For gains of 8, 16, 32, 64, 128
0.3
-2.5
2.5
For gain of 128
-3.5
3.5
0.8
For gains of 8, 16, 32, 64, 128
0.3
-2
2
For gain of 128
-3
3
1
For gain of 128
5
-2.5
2.5
For gain of 128
-3.5
3.5
0.8
For gains of 8, 16, 32, 64, 128
0.3
_______________________________________________________________________________________
%FSR
ppm/°C
For gains of 1, 2, 4, 8, 16, 32, 64
For gains of 1, 2, 4
%FSR
µV/°C
For gains of 1, 2, 4, 8, 16, 32, 64
For gains of 1, 2, 4, 8, 16, 32, 64
%FSR
µV/°C
For gains of 1, 2, 4, 8, 16, 32, 64
For gains of 1, 2, 4
%FSR
%FSR
µV/°C
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
(V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OFFSET DAC
Offset DAC Range (Note 7)
Offset DAC Resolution
Offset DAC Full-Scale Error
Unipolar mode
-116.7
116.7
Bipolar mode
-58.35
58.35
Unipolar mode
16.7
Bipolar mode
8.35
Input referred
Additional Noise from Offset
DAC (Note 8)
%FSR
Gain = 1, 2, 4, 8, 16, 32, 64
-2.5
+2.5
Gain = 128
-3.5
+3.5
Offset DAC Zero-Scale Error
DAC code = 0000
%FSR
%FSR
0
%FSR
0
µVRMS
ANALOG INPUTS/REFERENCE INPUTS (Specifications for AIN and REFIN, unless otherwise noted.)
Common-Mode Rejection
CMR
At DC
90
For filter notch 50Hz, ±0.02 · fNOTCH,
MF1 = 0, MF0 = 0, fCLKIN = 2.4576MHz (Note 9)
150
For filter notch 60Hz, ±0.02 · fNOTCH,
MF1 = 0, MF0 = 0, fCLKIN = 2.4576MHz (Note 9)
150
dB
Normal Mode 50Hz Rejection
(Note 9)
NMR
For filter notch 50Hz, ±0.02 · fNOTCH,
MF1 = 0, MF0 = 0, fCLKIN = 2.4576MHz
100
dB
Normal Mode 60Hz Rejection
(Note 9)
NMR
For filter notch 60Hz, ±0.02 · fNOTCH,
MF1 = 0, MF0 = 0, fCLKIN = 2.4576MHz
100
dB
Common-Mode Voltage Range
(Note 10)
REFIN and AIN for BUFF = 0
VAGND
V+
V
Absolute Input Voltage Range
REFIN and AIN for BUFF = 0
VAGND
- 30mV
V+
+ 30mV
V
Absolute and Common-Mode
AIN Voltage Range
BUFF = 1
VAGND
+ 200mV
V+
- 1.5
V
DC Input Leakage Current
(Note 11)
REFIN and AIN for
BUFF = 0
AIN Input Current (Note 11)
BUFF = 1
AIN Input Capacitance
(Notes 12)
BUFF = 0
TA = +25°C
TA = TMIN to TMAX
Gain = 1
34
Gain = 2
38
Gain = 4
45
Gain = 8, 16, 32, 64, 128
60
BUFF = 1, all gains
AIN Differential Voltage Range
(Note 13)
40
Unipolar input range (U/B bit = 1)
Bipolar input range (U/B bit = 0)
pA
10
nA
10
nA
pF
30
0 to VREF / gain
±VREF / gain
V
_______________________________________________________________________________________
3
MAX1403
ELECTRICAL CHARACTERISTICS (continued)
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
AIN and REFIN Input Sampling
Frequency
fS
REFIN+ - REFIN- Voltage
(Note 14)
CONDITIONS
MIN
TYP
MAX
(Table 15)
±5% for specified performance; functional
with lower VREF
UNITS
Hz
1.25
V
+10
µA
LOGIC INPUTS
Input Current
IIN
Input Low Voltage
VIL
Input High Voltage
VIH
Input Hysteresis
VHYS
-10
All inputs except CLKIN
0.4
CLKIN only
0.4
All inputs except CLKIN
CLKIN only
2
V
V
2.4
All inputs except CLKIN
200
mV
LOGIC OUTPUTS
Output Low Voltage (Note 15)
VOL
Output High Voltage (Note 15)
VOH
Floating-State Leakage Current
IL
Floating-State Output
Capacitance
DOUT and INT, ISINK = 100µA
0.4
CLKOUT, ISINK = 10µA
0.4
DOUT and INT, ISOURCE = 100µA
VDD - 0.3
CLKOUT, ISOURCE = 10µA
VDD - 0.3
V
-10
CO
V
10
µA
9
pF
TRANSDUCER BURN-OUT (Note 16)
Current
IBO
Initial Tolerance
Drift
0.1
µA
±10
%
±0.05
%/°C
200
uA
TRANSDUCER EXCITATION CURRENTS
Current
IEXC
Initial Tolerance
15
Drift
100
Match
OUT1 to OUT2
±1
Drift Match
5
Compliance Voltage Range
%
ppm/°C
%
ppm/°C
VAGND
V+ - 1.0
V
2.7
3.6
V
2.7
3.6
V
POWER REQUIREMENTS
V+ Voltage
V+
VDD Voltage
VDD
Power-Supply Rejection V+
(Note 17)
PSR
4
For specified performance
(Note 18)
_______________________________________________________________________________________
dB
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
(V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG POWER-SUPPLY CURRENT (Measured with digital inputs at either DGND or VDD, external CLKIN, burn-out and
transducer excitation currents disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
V+ Standby Current (Note 19)
PD bit = 1, external clock stopped
Normal mode,
MF1 = 0,
MF0 = 0
2X mode,
MF1 = 0,
MF0 = 1
V+ Current
1.024MHz
2.4576MHz
1.024MHz
2.4576MHz
IV+
4X mode,
MF1 = 1,
MF0 = 0
8X mode,
MF1 = 1,
MF0 = 1
1.024MHz
2.4576MHz
1.024MHz
2.4576MHz
1
10
Buffers off
175
210
Buffers on
370
420
Buffers off
250
300
Buffers on
610
700
Buffers off
245
Buffers on
610
Buffers off
0.42
0.55
Buffers on
1.2
1.5
Buffers off
0.42
Buffers on
1.2
Buffers off
1.8
2.2
Buffers on
4.8
6
Buffers off
1.8
Buffers on
4.8
Buffers off
1.8
2.2
Buffers on
4.8
6
µA
µA
mA
DIGITAL POWER-SUPPLY CURRENT (Measured with digital inputs at either DGND or VDD, external CLKIN, burn-out and
transducer excitation currents disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
VDD Standby Current (Note 19)
Digital Supply Current
PD bit = 1, external clock stopped
IDD
1
10
Normal mode,
MF1 = 0, MF0 = 0
1.024MHz
70
200
2.4576MHz
150
300
2X mode,
MF1 = 0, MF0 = 1
1.024MHz
0.08
2.4576MHz
0.17
4X mode,
MF1 = 1, MF0 = 0
1.024MHz
0.11
2.4576MHz
0.22
8X mode,
MF1 = 1, MF0 = 1
1.024MHz
0.15
2.4576MHz
0.32
µA
µA
0.35
0.40
mA
0.50
_______________________________________________________________________________________
5
MAX1403
ELECTRICAL CHARACTERISTICS (continued)
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER DISSIPATION (V+ = VDD = +3.3V, digital inputs = 0 or VDD, external CLKIN, burn-out and transducer excitation currents
disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
Normal mode,
MF1 = 0,
MF0 = 0
2X mode,
MF1 = 0,
MF0 = 1
Power Dissipation
2.4576MHz
1.024MHz
2.4576MHz
PD
4X mode,
MF1 = 1,
MF0 = 0
8X mode,
MF1 = 1,
MF0 = 1
Standby Power Dissipation
1.024MHz
(Note 19)
1.024MHz
2.4576MHz
1.024MHz
2.4576MHz
Buffers off
0.81
1.36
Buffers on
1.45
2.05
Buffers off
1.32
1.98
Buffers on
2.51
3.30
Buffers off
1.08
Buffers on
2.28
Buffers off
1.95
2.97
Buffers on
4.53
6.11
Buffers off
1.75
Buffers on
4.32
Buffers off
6.67
8.58
Buffers on
16.6
21.2
Buffers off
6.44
Buffers on
16.4
Buffers off
7.0
8.91
Buffers on
16.9
21.45
7
70
mW
µW
Note 1: Contact factory for INL limits applicable with FS1 = 0 and MF1, MF0 = 1, 2, or 3.
Note 2: Nominal gain is 0.98. This ensures a full-scale input voltage may be applied to the part under all conditions without causing saturation of the digital output data.
Note 3: Positive Full-Scale Error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
and bipolar input ranges. This error does not include the nominal gain of 0.98.
Note 4: Full-Scale Drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar
input ranges.
Note 5: Gain Error does not include zero-scale errors. It is calculated as (full-scale error - unipolar offset error) for unipolar ranges
and as (full-scale error - bipolar zero error) for bipolar ranges. This error does not include the nominal gain of 0.98.
Note 6: Gain-Error Drift does not include unipolar offset drift or bipolar zero drift. It is effectively the drift of the part if zero-scale
error is removed.
Note 7: Use of the offset DAC does not imply that any input may be taken below AGND.
Note 8: Additional noise added by the offset DAC is dependent on the filter cutoff, gain, and DAC setting. No noise is added for a
DAC code of 0000.
Note 9: Guaranteed by design or characterization; not production tested.
Note 10: The absolute input voltage must be within the input voltage range specification.
Note 11: All AIN and REFIN pins have identical input structures. Leakage is production tested only for the AIN3, AIN4, AIN5,
CALGAIN, and CALOFF inputs.
Note 12: The dynamic load presented by the MAX1403 analog inputs for each gain setting is discussed in detail in the Switching
Network section. Values are provided for the maximum allowable external series resistance.
Note 13: The input voltage range for the analog inputs is with respect to the voltage on the negative input of its respective differential or pseudo-differential pair. Table 5 shows which inputs form differential pairs.
Note 14: VREF = VREFIN+ - VREFIN-.
Note 15: These specifications apply to CLKOUT only when driving a single CMOS load.
6
_______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
MAX1403
Note 16: The burn-out currents require a 500mV overhead between the analog input voltage and both V+ and AGND to operate
correctly.
Note 17: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST
bit = 0. PSR at 60Hz will exceed 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
Note 18: PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical. For a gain of +2V/V, PSR is 75dB typical. For a gain of
+4V/V, PSR is 80dB typical. For gains of +8V/V to +128V/V, PSR is 85dB typical.
Note 19: Standby power-dissipation and current specifications are valid only with CLKIN driven by an external clock and with the
external clock stopped. If the clock continues to run in standby mode, the power dissipation will be considerably higher.
When used with a resonator or crystal between CLKIN and CLKOUT, the actual power dissipation and IDD in standby
mode will depend on the resonator or crystal type.
TIMING CHARACTERISTICS
(V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, AGND = DGND, fCLKIN = 2.4576MHz, input logic 0 = 0V, logic 1 = VDD, TA = TMIN to
TMAX, unless otherwise noted.) (Notes 20, 21, 22)
PARAMETER
Master Clock Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
Crystal oscillator or clock exterX2CLK = 0
nally supplied for specified perforX2CLK = 1
mance (Notes 23, 24)
0.4
2.5
fCLKIN
0.8
5.0
UNITS
MHz
Master Clock Input Low Time
fCLKIN LO
tCLKIN = 1 / fCLKIN, X2CLK = 0
0.4 ·
tCLKIN
ns
Master Clock Input High Time
fCLKIN HI
tCLKIN = 1 / fCLKIN, X2CLK = 0
0.4 ·
tCLKIN
ns
X2CLK = 0, N = 2(2 · MF1 + MF0)
INT High Time
tINT
X2CLK = 1, N = 2(2 · MF1 + MF0)
RESET Pulse Width Low
t2
280 / N
· tCLKIN
ns
560 / N
· tCLKIN
100
ns
SERIAL-INTERFACE READ OPERATION
INT to CS Setup Time (Note 9)
t3
0
ns
SCLK Setup to Falling Edge CS
t4
30
ns
CS Falling Edge to SCLK Falling
Edge Setup Time
t5
30
ns
SCLK Falling Edge to Data Valid
Delay (Notes 25, 26)
t6
0
0
SCLK High Pulse Width
t7
100
ns
SCLK Low Pulse Width
t8
100
ns
CS Rising Edge to SCLK Rising
Edge Hold Time (Note 22)
t9
0
ns
Bus Relinquish Time After SCLK
Rising Edge (Note 27)
t10
10
SCLK Rising Edge to INT High
(Note 28)
t11
100
100
ns
100
ns
200
ns
SERIAL-INTERFACE WRITE OPERATION
SCLK Setup to Falling Edge CS
t12
30
ns
_______________________________________________________________________________________
7
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
TIMING CHARACTERISTICS (continued)
(V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, AGND = DGND, fCLKIN = 2.4576MHz, input logic 0 = 0V, logic 1 = VDD, TA = TMIN to
TMAX, unless otherwise noted.) (Notes 20, 21, 22)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CS Falling Edge to SCLK Falling
Edge Setup Time
t13
30
ns
Data Valid to SCLK Rising Edge
Setup Time
t14
30
ns
Data Valid to SCLK Rising Edge
Hold Time
t15
0
ns
SCLK High Pulse Width
t16
100
ns
SCLK Low Pulse Width
t17
100
ns
CS Rising Edge to SCLK Rising
Edge Hold Time
t18
0
ns
AUXILIARY DIGITAL INPUTS (DS0 and DS1)
DS0/DS1 to SCLK Falling Edge
Setup Time (Notes 21, 29)
t19
40
ns
DS0/DS1 to SCLK Falling Edge
Hold Time (Notes 21, 29)
t20
0
ns
Note 20: All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 21: See Figure 4.
Note 22: Timings shown in tables are for the case where SCLK idles high between accesses. The part may also be used with SCLK
idling low between accesses, provided CS is toggled. In this case SCLK in the timing diagrams should be inverted and
the terms “SCLK Falling Edge” and “SCLK Rising Edge” exchanged in the specification tables. If CS is permanently tied
low, the part should only be operated with SCLK idling high between accesses.
Note 23: CLKIN duty cycle range is 45% to 55%. CLKIN must be supplied whenever the MAX1403 is not in standby mode. If no
clock is present, the device can draw higher current than specified.
Note 24: The MAX1403 is production tested with fCLKIN at 2.5MHz (1MHz for some IDD tests).
Note 25: Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.
Note 26: For read operations, SCLK active edge is falling edge of SCLK.
Note 27: Derived from the time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The number is
then extrapolated back to remove effects of charging or discharging the 50pF capacitor. This ensures that the times quoted in the timing characteristics are true bus-relinquish times and are independent of external bus loading capacitances.
Note 28: INT returns high after the first read after an output update. The same data can be read again while INT is high, but be
careful not to allow subsequent reads to occur close to the next output update.
Note 29: Auxiliary inputs DS0 and DS1 are latched on the first falling edge of SCLK during a data-read cycle.
100µA
at VDD = +3.3V
TO
OUTPUT
PIN
50pF
100µA
at VDD = +3.3V
Figure 1. Load Circuit for Bus-Relinquish Time and VOL and
VOH Levels
8
_______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
100
V+ = +3.3V
0
0.5
1.0
1.5
2.0
2.5
3.0
INL (ppm)
0
0
-5
-5
-10
-10
-15
-1.0
3.5
-0.5
0
0.5
-1.0
1.0
-0.5
0
0.5
1.0
COMPLIANCE VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (V)
VDD SUPPLY CURRENT vs. TEMPERATURE
(20sps OUTPUT DATA RATE UNBUFFERED)
VDD SUPPLY CURRENT vs. TEMPERATURE
(60sps OUTPUT DATA RATE UNBUFFERED)
VDD SUPPLY CURRENT vs. TEMPERATURE
(120sps OUTPUT DATA RATE UNBUFFERED)
200
150
100
VDD = +3.6V
50
250
200
150
100
300
VDD = +3.6V
(NOTE 30)
50
(NOTE 30)
-50
-25
0
25
50
75
200
150
100
VDD = +3.6V
(NOTE 30)
0
-50
100
250
50
0
0
MAX1403 toc06
300
350
VDD SUPPLY CURRENT (µA)
250
MAX1403 toc05
300
350
VDD SUPPLY CURRENT (µA)
MAX1403 toc04
350
-25
0
25
50
75
-50
100
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
V+ SUPPLY CURRENT vs. TEMPERATURE
(20sps OUTPUT DATA RATE)
V+ SUPPLY CURRENT vs. TEMPERATURE
(60sps OUTPUT DATA RATE)
V+ SUPPLY CURRENT vs. TEMPERATURE
(120sps OUTPUT DATA RATE)
250
200
150
UNBUFFERED
100
400
300
200
UNBUFFERED
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
BUFFERED
800
600
400
UNBUFFERED
0
0
0
1000
200
100
50
MAX1403 toc09
BUFFERED
500
V+ SUPPLY CURRENT (µA)
BUFFERED
300
1200
MAX1403 toc08
350
600
V+ SUPPLY CURRENT (µA)
MAX1403 toc07
400
V+ SUPPLY CURRENT (µA)
MAX1403-03
5
-15
0
480sps
GAIN = +1V/V
262, 144 pts
10
5
150
50
VDD SUPPLY CURRENT (µA)
480sps
GAIN = +1V/V
262, 144 pts
10
15
MAX1403-02
MAX1402 toc01
15
DNL (ppm)
OUTPUT CURRENT (µA)
200
INTEGRAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
OUT1 AND OUT2 COMPLIANCE
250
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
_______________________________________________________________________________________
9
MAX1403
Typical Operating Characteristics
(V+ = +3V, VDD = +3V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, transducer excitation currents disabled, TA =
+25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(V+ = +3V, VDD = +3V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, transducer excitation currents disabled, TA =
+25°C, unless otherwise noted.)
VDD SUPPLY CURRENT vs. TEMPERATURE
(240sps OUTPUT DATA RATE UNBUFFERED)
300
250
200
150
100
500
400
300
200
100
VDD = +3.6V
(NOTE 30)
50
MAX1403 toc11
350
600
VDD = +3.6V
(NOTE 30)
0
0
-50
-25
0
25
50
75
-50
100
-25
0
25
50
75
100
TEMPERATURE (°C)
V+ SUPPLY CURRENT vs. TEMPERATURE
(240sps OUTPUT DATA RATE)
V+ SUPPLY CURRENT vs. TEMPERATURE
(480sps OUTPUT DATA RATE)
MAX1403 toc12
TEMPERATURE (°C)
4000
BUFFERED
3000
2000
UNBUFFERED
1000
5000
V+ SUPPLY CURRENT (µA)
5000
MAX1403 toc13
VDD SUPPLY CURRENT (µA)
400
VDD SUPPLY CURRENT vs. TEMPERATURE
(480sps OUTPUT DATA RATE UNBUFFERED)
VDD SUPPLY CURRENT (µA)
MAX1403 toc10
450
V+ SUPPLY CURRENT (µA)
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
BUFFERED
4000
3000
2000
1000
0
UNBUFFERED
0
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
Note 30: Minimize capacitive loading at CLKOUT for lowest VDD supply current. Typical Operating Characteristics show VDD
supply current with CLKOUT loaded by 120pF.
10
______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
PIN
NAME
FUNCTION
1
CLKIN
Clock Input. A crystal can be connected across CLKIN and CLKOUT. Alternatively, drive CLKIN with a
CMOS-compatible clock at a nominal frequency of 2.4576MHz or 1.024MHz, and leave CLKOUT unconnected. Frequencies of 4.9152MHz and 2.048MHz may be used if the X2CLK control bit is set to 1.
2
CLKOUT
Clock Output. When deriving the master clock from a crystal, connect the crystal between CLKIN and
CLKOUT. In this mode, the on-chip clock signal is not available at CLKOUT. Leave CLKOUT unconnected
when CLKIN is driven with an external clock.
3
CS
Chip-Select Input. This active-low logic input is used to enable the digital interface. With CS hard-wired
low, the MAX1403 operates in its 3-wire interface mode with SCLK, DIN, and DOUT used to interface to
the device. CS is used either to select the device in systems with more than one device on the serial bus,
or as a frame-synchronization signal for the MAX1403, when a continuous SCLK is used.
4
RESET
Active-Low Reset Input. Drive low to reset the control logic, interface logic, digital filter, and analog modulator to power-on status. RESET must be high and CLKIN must be toggling in order to exit reset.
5
DS1
Digital Input for Auxiliary Data Input Bit 1. The status of this bit is reflected in the output data by bit D4.
Used to communicate the status of DS1 via the serial interface.
6
DS0
Digital Input for Auxiliary Data Input Bit 0. The status of this bit is reflected in the output data by bit D3.
Used to communicate the status of DS0 via the serial interface.
7
OUT2
Transducer Excitation Current Source 2
8
OUT1
Transducer Excitation Current Source 1
9
AGND
Analog Ground. Reference point for the analog circuitry. AGND connects to the IC substrate.
10
V+
11
AIN1
Analog Input Channel 1. May be used as a pseudo-differential input with AIN6 as common, or as the positive input of the AIN1/AIN2 differential analog input pair (see On-Chip Registers section).
12
AIN2
Analog Input Channel 2. May be used as a pseudo-differential input with AIN6 as common, or as the negative input of the AIN1/AIN2 differential analog input pair (see On-Chip Registers section).
13
AIN3
Analog Input Channel 3. May be used as a pseudo-differential input with AIN6 as common, or as the positive input of the AIN3/AIN4 differential analog input pair (see On-Chip Registers section).
14
AIN4
Analog Input Channel 4. May be used as a pseudo-differential input with AIN6 as common, or as the negative input of the AIN3/AIN4 differential analog input pair (see On-Chip Registers section).
15
AIN5
Analog Input Channel 5. Used as a differential or pseudo-differential input with AIN6 (see On-Chip
Registers section).
16
AIN6
Analog Input 6. May be used as a common point for AIN1 through AIN5 in pseudo-differential mode, or as
the negative input of the AIN5/AIN6 differential analog input pair (see On-Chip Registers section).
17
CALGAIN-
Negative Gain Calibration Input. Used for system gain calibration. It forms the negative input of a fully
differential input pair with CALGAIN+. Normally these inputs are connected to reference voltages in the
system. When system gain calibration is not required and the auto-sequence mode is used, the
CALGAIN+/CALGAIN- input pair provides an additional fully differential input channel.
18
CALGAIN+
Positive Gain Calibration Input. Used for system gain calibration. It forms the positive input of a fully
differential input pair with CALGAIN-. Normally these inputs are connected to reference voltages in the
system. When system gain calibration is not required and the auto-sequence mode is used, the
CALGAIN+/CALGAIN- input pair provides an additional fully differential input channel.
Analog Positive Supply Voltage (+2.7V to +3.6V).
______________________________________________________________________________________
11
MAX1403
Pin Description
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
MAX1403
Pin Description (continued)
PIN
NAME
FUNCTION
19
REFIN-
Negative Differential Reference Input. Bias REFIN- between V+ and AGND, provided that REFIN+ is more
positive than REFIN-.
20
REFIN+
Positive Differential Reference Input. Bias REFIN+ between V+ and AGND, provided that REFIN+ is more
positive than REFIN-.
CALOFF-
Negative Offset Calibration Input. Used for system offset calibration. It forms the negative input of a fully
differential input pair with CALOFF+. Normally these inputs are connected to zero-reference voltages in
the system. When system offset calibration is not required and the auto-sequence mode is used, the
CALOFF+/CALOFF- input pair provides an additional fully differential input channel.
22
CALOFF+
Positive Offset Calibration Input. Used for system offset calibration. It forms the positive input of a fully
differential input pair with CALOFF-. Normally these inputs are connected to zero-reference voltages in the
system. When system offset calibration is not required and the auto-sequence mode is used, the
CALOFF+/CALOFF- input pair provides an additional fully differential input channel.
23
DGND
24
VDD
Digital Supply Voltage (+2.7V to +3.6V)
25
INT
Interrupt Output. A logic low indicates that a new output word is available from the data register. INT
returns high upon completion of a full output word read operation. INT also returns high for short periods
(determined by the filter and clock control bits) if no data read has taken place. A logic high indicates
internal activity, and a read operation should not be attempted under this condition. INT can also provide
a strobe to indicate valid data at DOUT (MDOUT = 1).
26
DOUT
Serial Data Output. DOUT outputs data from the internal shift register containing information from the
Communications Register, Global Setup Registers, Transfer Function Registers, or Data Register. DOUT
can also provide the digital bit stream directly from the Σ-∆ modulator (MDOUT = 1).
27
DIN
21
28
12
SCLK
Digital Ground. Reference point for digital circuitry.
Serial Data Input. Data on DIN is written to the input shift register and later transferred to the
Communications Register, Global Setup Registers, Special Function Register, or Transfer Function
Registers, depending on the register selection bits in the Communications Register.
Serial Clock Input. Apply an external serial clock to transfer data to and from the MAX1403. This serial
clock can be continuous, with data transmitted in a train of pulses, or intermittently. If CS is used to frame
the data transfer, then SCLK may idle high or low between conversions and CS determines the desired
active clock edge (see Selecting Clock Polarity). If CS is tied permanently low, SCLK must idle high
between data transfers.
______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Circuit Description
The MAX1403 is a low-power, multichannel, serial-output,
sigma-delta ADC designed for applications with a wide
dynamic range, such as weigh scales and pressure
transducers. The functional block diagram in Figure 2
contains a switching network, a modulator, a PGA, two
buffers, an oscillator, an on-chip digital filter, two
matched transducer excitation current sources, and a
bidirectional serial communications port.
Three fully differential input channels feed into the
switching network. Each channel may be independently programmed with a gain between +1V/V and
+128V/V. These three differential channels may also be
configured to operate as five pseudo-differential input
channels. Two additional, fully differential system-calibration channels allow system gain and offset error to
be measured. These system-calibration channels can
be used as additional differential signal channels when
dedicated gain and offset error correction channels are
not required.
Two chopper-stabilized buffers are available to isolate
the selected inputs from the capacitive loading of the
PGA and modulator. Three independent DACs provide
compensation for the DC component of the input signal
on each of the differential input channels.
The sigma-delta modulator converts the input signal into
a digital pulse train whose average duty cycle represents
the digitized signal information. The pulse train is then
processed by a digital decimation filter, resulting in a
conversion accuracy exceeding 16 bits. The digital filter’s
decimation factor is user-selectable, which allows the
conversion result’s resolution to be reduced to achieve a
higher output data rate. When used with 2.4576MHz or
1.024MHz master clocks, the decimation filter can be
programmed to produce zeros in its frequency response
at the line frequency and associated harmonics. This
ensures excellent line rejection without the need for further postfiltering. In addition, the modulator sampling
frequency can be optimized for either lowest power dissipation or highest output data rate.
V+
MAX1403
OUT1
CLOCK
GEN
DIVIDER
OUT2
CALOFF+
CALGAIN+
AIN4
CLKOUT
BUFFER
AIN1
AIN2
AIN3
CLKIN
VDD
SWITCHING
NETWORK
PGA
V+
MODULATOR
DIGITAL
FILTER
DGND
V+
AGND
AIN5
AIN6
CALOFFCALGAIN-
BUFFER
SCLK
DAC
DIN
DOUT
AGND
INTERFACE
AND CONTROL
INT
CS
RESET
DS1
REFIN+
REFIN-
DS0
Figure 2. Functional Diagram
______________________________________________________________________________________
13
MAX1403
_______________Detailed Description
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
The MAX1403 can be configured to sequentially scan
all signal inputs and to transmit the results through the
serial interface with minimum communications overhead. The output word contains a channel identification
tag to indicate the source of each conversion result.
Serial Digital Interface
The serial digital interface provides access to eight onchip registers (Figure 3). All serial-interface commands
begin with a write to the communications register
(COMM). On power-up, system reset, or interface reset,
the part expects a write to its communications register.
The COMM register access begins with a 0 start bit.
The COMM register R/W bit selects a read or write
operation, and the register select bits (RS2, RS1, RS0)
select the register to be addressed. Hold DIN high
when not writing to COMM or another register (Table 1).
The serial interface consists of five signals: CS, SCLK,
DIN, DOUT, and INT. Clock pulses on SCLK shift bits
into DIN and out of DOUT. INT provides an indication
that data is available. CS is a device chip-select input
as well as a clock polarity select input (Figure 4).
Using CS allows the SCLK, DIN, and DOUT signals to
be shared among several SPI-compatible devices.
When short on I/O pins, connect CS low and operate
the serial digital interface in CPOL = 1, CPHA = 1 mode
using SCLK, DIN, and DOUT. This 3-wire interface mode
is ideal for opto-isolated applications. Furthermore, a
microcontroller (such as a PIC16C54 or 80C51) can
use a single bidirectional I/O pin for both sending to
DIN and receiving from DOUT (see Applications
Information), because the MAX1403 drives DOUT only
during a read cycle.
Additionally, connecting the INT signal to a hardware
interrupt allows faster throughput and reliable, collisionfree data flow.
The MAX1403 features a mode where the raw modulator data output is accessible. In this mode, the DOUT
and INT functions are reassigned (see the Modulator
Data Output section).
COMMUNICATIONS REGISTER
RS2 RS1 RS0
DIN
GLOBAL SETUP REGISTER 1
GLOBAL SETUP REGISTER 2
XFER FUNCTION REGISTER 1
XFER FUNCTION REGISTER 2
XFER FUNCTION REGISTER 3
DOUT
DATA REGISTER D17–D10
DATA REGISTER D9–D2
DATA REGISTER D1–D0/CID
Figure 3. Register Summary
t11
INT
t1
t3
CS
t12
t4
SCLK
(CPOL = 1)
t16
t7
t13
t5
Table 1. Control-Register Addressing
RS2
RS1
RS0
0
0
0
Communications Register
TARGET REGISTER
0
0
1
Global Setup Register 1
0
1
0
Global Setup Register 2
0
1
1
Special Function Register
1
0
0
Transfer Function Register 1
1
0
1
1
1
0
1
1
1
Data Register
REGISTER
SELECT
DECODER
SPECIAL FUNCTION REGISTER
t9
t18
t8
t17
SCLK
(CPOL = 0)
t14
t15
DIN
(DURING
WRITE)*
MSB D6
MSB D6
Transfer Function Register 2
DOUT
(DURING
READ)*
Transfer Function Register 3
DS1, DS0
D5
D4
D3
D2
D1
D0
D5
D4
D3
D2
D1
D0
t6
t19
t10
t20
*DOUT IS HIGH IMPEDANCE DURING THE WRITE CYCLE; DIN IS IGNORED
DURING THE READ CYCLE.
Figure 4. Serial-Interface Timing
14
______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Data-Ready Signal (DRDY bit true or INT = low)
The data-ready signal indicates that new data may be
read from the 24-bit data register. After the end of a successful data register read, the data-ready signal
becomes false. If a new measurement completes before
the data is read, the data-ready signal becomes false.
The data-ready signal becomes true again when new
data is available in the data register.
The MAX1403 provides two methods of monitoring the
data-ready signal. INT provides a hardware solution
(active low when data is ready to be accessed), while
the DRDY bit in the COMM register provides a software
solution (active high).
Read data as soon as possible once data-ready
becomes true. This becomes increasingly important for
faster measurement rates. If the data read is delayed
significantly, a collision may result. A collision occurs
when a new measurement completes during a dataregister read operation. After a collision, information in
the data register is invalid. The failed read operation
must be completed even though the data is invalid.
Resetting the Interface
Reset the serial interface by clocking in 32 1s.
Resetting the interface does not affect the internal registers.
If continuous data output mode is in use, clock in eight
0s followed by 32 1s. More than 32 1s may be clocked
in, since a leading 0 is used as the start bit for all operations.
Continuous Data Output Mode
When scanning the input channels (SCAN = 1), the serial interface allows the data register to be read repeatedly without requiring a write to the COMM register.
The initial COMM write (01111000) is followed by 24
clocks (DIN = high) to read the 24-bit data register.
Once the data register has been read, it can be read
again after the next conversion by writing another 24
clocks (DIN = high). Terminate the continuous data output mode by writing to the COMM register with any
valid access.
Modulator Data Output (MDOUT = 1)
Single-bit, raw modulator data is available at DOUT for
custom filtering when MDOUT = 1. INT provides a modulator clock for data synchronization. Data is valid on
the falling edge of INT. Write operations can still be
performed; however, read operations are disabled.
After MDOUT is returned to 0, valid data is accessed
by the normal serial-interface read operation.
On-Chip Registers
Communications Register
0/DRDY: (Default = 0) Data Ready Bit. On a write, this
bit must be reset to 0 to signal the start of the Communications Register data word. On a read, a 1 in this
location (0/DRDY) signifies that valid data is available in
the data register. This bit is reset after the data register
is read or, if data is not read, 0/DRDY will go low at the
end of the next measurement.
RS2, RS1, RS0: (Default = 0, 0, 0) Register Select
Bits. These bits select the register to be accessed
(Table 1).
R/W: (Default = 0) Read/Write Bit. When set high, the
selected register is read; when R/W = 0, the selected
register is written.
RESET: (Default = 0) Software Reset Bit. Setting this
bit high causes the part to be reset to its default powerup condition (RESET = 0).
STDBY: (Default = 0) Standby Power-Down Bit. Setting
the STDBY bit places the part in “standby” condition,
shutting down everything except the serial interface
and the CLK oscillator.
FSYNC: (Default = 0) Filter Sync Bit. When FSYNC = 0,
conversions are automatically performed at a data rate
determined by CLK, FS1, FS0, MF1, and MF0 bits.
When FSYNC = 1, the digital filter and analog modulator
Communications Register
First Bit (MSB)
FUNCTION
Name
Defaults
DATA
RDY
(LSB)
REGISTER SELECT BITS
0/DRDY
RS2
RS1
RS0
R/W
RESET
STDBY
FSYNC
0
0
0
0
0
0
0
0
______________________________________________________________________________________
15
MAX1403
Selecting Clock Polarity
The serial interface can be operated with the clock idling
either high or low. This is compatible with Motorola’s SPI
interface operated in CPOL = 1, CPHA = 1 mode or
CPOL = 0, CPHA = 1 mode. The clock polarity is determined by the state of SCLK at the falling edge of CS.
Ensure that the setup times t4/t12 and t5/t13 are not violated. If CS is connected to ground, resulting in no falling
edge on CS, SCLK must idle high (CPOL = 1, CPHA = 1).
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
are held in reset, inhibiting normal self-timed operation.
This bit may be used to convert on command to minimize the settling time to valid output data, or to synchronize operation of a number of MAX1403s. FSYNC does
not reset the serial interface or the 0/DRDY flag. To clear
the 0/DRDY flag while FSYNC is active, simply read the
data register.
Global Setup Register 1
A1, A0: (Default = 0, 0) Channel-Selection Control Bits.
These bits (combined with the state of the DIFF, M1,
and M0 bits) determine the channel selected for conversion according to Tables 8, 9, and 10. These bits
are ignored if the SCAN bit is set.
MF1, MF0: (Default = 0, 0) Modulator Frequency Bits.
MF1 and MF0 determine the ratio of CLKIN oscillator frequency to modulator operating frequency. They affect
the output data rate, the position of the digital filter notch
frequencies, and the power dissipation of the device.
Achieve lowest power dissipation with MF1 = 0 and MF0
= 0. Highest power dissipation and fastest output data
rate occur with these bits set to 1, 1 (Table 2).
CLK: (Default = 1) CLK Bit. The CLK bit is used in conjunction with X2CLK to tell the MAX1403 the frequency
of the CLKIN input signal. If CLK = 0, a CLKIN input frequency of 1.024MHz (2.048MHz for X2CLK = 1) is
expected. If CLK = 1, a CLKIN input frequency of
2.4576MHz (4.9152MHz for X2CLK = 1) is expected.
This bit affects the decimation factor in the digital filter
and thus the output data rate (Table 2).
FS1, FS0: (Default = 0, 1) Filter Selection Bits. These
bits (in conjunction with the CLK bit) control the decimation ratio of the digital filter. They determine the output data rate, the position of the digital filter frequency
response notches, and the noise present in the output
result (Table 2).
FAST: (Default 0) Fast Bit. FAST = 0 causes the digital
filter to perform a SINC3 filter function on the modulator
data stream. The output data rate will be determined by the values in the CLK, FS1, FS0, MF1, and
MF0 bits (Table 2). The settling time for SINC3 function
is 3 · [1 / (output data rate)]. In SINC 3 mode, the
MAX1403 automatically holds the DRDY signal false
(after any significant configuration change) until settled
data is available. FAST = 1 causes the digital filter to
perform a SINC1 filter function on the modulator data
stream. The signal-to-noise ratio achieved with this filter
function is less than that of the SINC3 filter; however,
SINC1 settles in a single output sample period rather
than a minimum of three output sample periods for
SINC3. When switching from SINC1 to SINC3 mode, the
DRDY flag will be deasserted and reasserted after the
filter has fully settled. This mode change requires a
minimum of three samples.
Global Setup Register 2
SCAN: (Default = 0) Scan Bit. Setting this bit to a 1
causes sequential scanning of the input channels as
determined by DIFF, M1, and M0 (see Scanning (ScanMode) section). When SCAN = 0, the MAX1403 repeatedly measures the unique channel selected by A1, A0,
DIFF, M1, and M0 (Table 4).
M1, M0: (Default 0, 0) Mode Control Bits. These bits
control access to the calibration channels CALOFF and
CALGAIN. When SCAN = 0, setting M1 = 0 and M0 = 1
selects the CALOFF input, and M1 = 1 and M0 = 0
selects the CALGAIN input (Table 3). When SCAN = 1
and M1 ≠ M0, the scanning sequence includes both
CALOFF and CALGAIN inputs (Table 4). When SCAN is
set to 1 and the device is scanning the available input
channels, selection of either calibration mode (01 or 10)
will cause the scanning sequence to be extended to
include a conversion on both the CALGAIN+/CALGAINinput pair and the CALOFF+/CALOFF-input pair. The
Global Setup Register 1
First Bit (MSB)
FUNCTION
(LSB)
MODULATOR
FREQUENCY
CHANNEL SELECTION
Name
FILTER SELECTION
A1
A0
MF1
MF0
CLK
FS1
FS0
FAST
0
0
0
0
1
0
1
0
Defaults
Global Setup Register 2
First Bit (MSB)
FUNCTION
Name
Defaults
16
(LSB)
MODE CONTROL
SCAN
M1
M0
BUFF
DIFF
BOUT
IOUT
X2CLK
0
0
0
0
0
0
0
0
______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
BOUT: (Default = 0) Burn-Out Current Bit. Setting BOUT
= 1 connects 100nA current sources to the selected analog input channel. This mode is used to check that a
transducer has not burned out or opened circuit. The
burn-out current source must be turned off (BOUT = 0)
before measurement to ensure best linearity.
IOUT: (Default = 0) The IOUT bit controls the
Transducer Excitation Currents. A 0 in this bit disables
OUT1 and OUT2, effectively making these pins highimpedance. A 1 in this location activates both IOUT1
and IOUT2, causing each pin to source 200µA.
X2CLK: (Default = 0) Times-Two Clock Bit. Setting this
bit to 1 selects a divide-by-2 prescaler in the clock signal path. This allows use of a higher frequency crystal
or clock source and improves immunity to asymmetric
clock sources.
Table 2. Data Output Rate vs. CLK, Filter Select, and Modulator Frequency Bits
AVAILABLE OUTPUT DATA RATES
(sps)
CLKIN FREQUENCY,
fCLKIN (MHz)
CLK
MF1
MF0
FS1, FS0*
(0, 0)
FS1, FS0*
(0, 1)
FS1, FS0
(1, 0)
FS1, FS0
(1, 1)
0
20
25
100
200
0
1
40
50
200
400
1
0
80
100
400
800
0
1
1
160
200
800
1600
4.9152
1
0
0
50
60
300
600
2.4576
4.9152
1
0
1
100
120
600
1200
2.4576
4.9152
1
1
0
200
240
1200
2400
2.4576
4.9152
1
1
1
400
480
2400
4800
X2CLK = 0
X2CLK = 1
1.024
2.048
0
0
1.024
2.048
0
1.024
2.048
0
1.024
2.048
2.4576
* Data rates offering noise-free 16-bit resolution.
Note: When FAST = 0, f-3dB = 0.262 · Data Rate. When FAST = 1, f-3dB = 0.443 · Data Rate.
Note: Default condition is in bold print.
Table 3. Special Modes Controlled by M1, M0 (SCAN = 0)
M1
M0
DESCRIPTION
0
0
Normal Mode: The device operates normally.
0
1
Calibrate Offset: In this mode, the MAX1403 converts the voltage applied across CALOFF+
and CALOFF-. The PGA gain, DAC, and format settings of the selected channel (defined by
DIFF, A1, A0) are used.
1
0
Calibrate Gain: In this mode, the MAX1403 converts the voltage applied across CALGAIN+
and CALGAIN-. The PGA gain, DAC, and format settings of the selected channel (defined by
DIFF, A1, A0) are used.
1
1
Reserved: Do not use.
______________________________________________________________________________________
17
MAX1403
exact sequence depends on the state of the DIFF bit
(Table 4). When scanning, the calibration channels use
the PGA gain, format, and DAC settings defined by the
contents of Transfer Function Register 3.
BUFF: (Default = 0) The BUFF bit controls operation of
the input buffer amplifiers. When this bit is 0, the internal buffers are bypassed and powered down. When
this bit is set high, the buffers drive the input sampling
capacitors and minimize the dynamic input load.
DIFF: (Default = 0) Differential/Pseudo-Differential Bit.
When DIFF = 0, the part is in pseudo-differential mode,
and AIN1–AIN5 are measured respective to AIN6, the
analog common. When DIFF = 1, the part is in differential mode with the analog inputs defined as AIN1/AIN2,
AIN3/AIN4, and AIN5/AIN6. The available input channels for each mode are tabulated in Table 5. Note that
DIFF also affects the scanning sequence when the part
is placed in SCAN mode (Table 4).
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Table 4. SCAN Mode Scanning
Sequences (SCAN = 1)
DIFF
M1
M0
SEQUENCE
0
0
0
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6, AIN5–AIN6
0
0
1
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6, AIN5–AIN6, CALOFF,
CALGAIN
0
1
0
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6, AIN5–AIN6, CALOFF,
CALGAIN
1
0
0
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6
1
0
1
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6,
CALOFF, CALGAIN
1
1
0
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6,
CALOFF, CALGAIN
Note: All other combinations reserved.
Table 5. Available Input Channels
(SCAN = 0)
DIFF
M1
M0
AVAILABLE CHANNELS
0
0
0
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6
0
0
1
CALOFF
0
1
0
CALGAIN
1
0
0
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6
1
0
1
CALOFF
1
1
0
CALGAIN
Special Function Register (Write-Only)
MDOUT: (Default = 0) Modulator Out Bit. MDOUT = 0
enables data readout on the DOUT pin, the normal condition for the serial interface. MDOUT = 1 changes the
function of the DOUT and INT pins, providing raw, single-bit modulator output instead of the normal serialdata interface output. This allows custom filtering
directly on the modulator output, without going through
the on-chip digital filter. The INT pin provides a clock to
indicate when the modulator data at DOUT should be
sampled (falling edge of INT). Note that in this mode,
the on-chip digital filter continues to operate normally.
When MDOUT is returned to 0, valid data may be
accessed through the normal serial-interface read
operation.
FULLPD: (Default = 0) Complete Power-Down Bit.
FULLPD = 1 forces the part into a complete power-down
condition, which includes the clock oscillator. The serial
interface continues to operate. The part requires a hardware reset to recover correctly from this condition.
Note: Changing the reserved bits in the special-function register from the default status of all 0s will select
one of the reserved modes and the part will not operate
as expected. This register is a write-only register.
However, in the event that this register is mistakenly
read, clock 24 bits of data out of the part to restore it to
the normal interface-idle state.
Transfer-Function Registers
The three transfer-function registers control the method
used to map the input voltage to the output codes. All
of the registers have the same format. The mapping of
control registers to associated channels depends on
the mode of operation and is affected by the state of
M1, M0, DIFF, and SCAN (Tables 8, 9, and 10).
Special Function Register (Write-Only)
First Bit (MSB)
FUNCTION
(LSB)
RESERVED BITS
RESERVED BITS
Name
0
0
MDOUT
0
0
0
0
FULLPD
Defaults
0
0
0
0
0
0
0
0
Transfer-Function Register
First Bit (MSB)
FUNCTION
Name
Defaults
18
(LSB)
PGA GAIN CONTROL
PGA
OFFSET CORRECTION
G2
G1
G0
U/B
D3
D2
D1
D0
0
0
0
0
0
0
0
0
______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
mapped to the correct output range. Note that U/B
must be set before a conversion is performed; it will not
affect any data already held in the output register.
CALGAIN and CALOFF
When not in scan mode (SCAN = 0), A1 and A0 select
which transfer function applies to CALGAIN and
CALOFF. In scan mode (SCAN = 1), CALGAIN and
CALOFF are always mapped to transfer-function register 3. Note that when scanning while M1 ≠ M0, the scan
sequence includes both CALGAIN and CALOFF channels (Table 4). CALOFF always precedes CALGAIN,
even though both channels share the same channel ID
tag (Table 11).
Offset-Correction DACs
Bits D3–D0 control the offset-correction DAC. The DAC
range depends on the PGA gain setting and is
expressed as a percentage of the available full-scale
input range (Table 7).
D3 is a sign bit, and D2–D0 represent the DAC magnitude. Note that when a DAC value of 0000 is programmed (the default), the DAC is disconnected from
the modulator inputs. This prevents the DAC from
degrading noise performance when offset correction is
not required.
Note that changing the status of any active channel
control bits will cause INT to immediately transition high
and the modulator/filter to be reset. INT will reassert
after the appropriate digital-filter settling time. The control settings of the inactive channels may be changed
freely without affecting the status of INT or causing the
filter/modulator to be reset.
PGA Gain
Bits G2–G0 control the PGA gain according to Table 6.
Unipolar/Bipolar Mode
The U/B bit places the channel in either bipolar or
unipolar mode. A 0 selects bipolar mode, and a 1
selects unipolar mode. This bit does not affect the analog-signal conditioning. The modulator always accepts
bipolar inputs and produces a bitstream with 50%
ones-density when the selected inputs are at the same
potential. This bit controls the processing of the digitalfilter output, such that the available output bits are
Table 6. PGA Gain Codes
G2
G1
G0
PGA GAIN
0
0
0
x1
0
0
1
x2
0
1
0
x4
0
1
1
x8
Selecting bipolar mode does not imply that any input
may be taken below AGND. It simply changes the gain
and offset of the part. All inputs must remain within their
specified operating voltage range.
Transfer-Function Register Mapping
Tables 8, 9, and 10 show the channel-control register
mapping in the various operating modes.
Table 7. DAC Code vs. DAC Value
BIPOLAR
DAC VALUE
(% of FSR)
UNIPOLAR
DAC VALUE
(% of FSR)
D3
D2
D1
D0
0
0
0
0
0
0
0
1
+8.3
+16.7
0
0
1
0
+16.7
+33.3
0
0
1
1
+25
+50
0
1
0
0
+33.3
+66.7
0
1
0
1
+41.6
+83.3
0
1
1
0
+50
+100
0
1
1
1
+58.3
+116.7
1
0
0
0
1
0
0
1
-8.3
-16.7
1
0
1
0
-16.7
-33.3
1
0
1
1
-25
-50
1
0
0
-33.3
-66.7
-83.3
DAC not connected
DAC not connected
1
0
0
x16
1
1
0
1
x32
1
1
0
1
-41.6
x64
1
1
1
0
-50
-100
x128
1
1
1
1
-58.3
-116.7
1
1
1
1
0
1
______________________________________________________________________________________
19
MAX1403
Analog Inputs AIN1 to AIN6
Inputs AIN1 and AIN2 map to transfer-function register
1, regardless of scanning mode (SCAN = 1) or singleended vs. differential (DIFF) modes. Likewise, AIN3 and
AIN4 inputs always map to transfer-function register 2.
Finally, AIN5 always maps to transfer-function register 3
(input AIN6 is analog common).
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Table 8. Transfer-Function Register Mapping—Normal Mode (M1 = 0, M0 = 0)
SCAN
DIFF
A1
A0
CHANNEL
TRANSFERFUNCTION REGISTER
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
1
AIN1–AIN6
AIN2–AIN6
AIN3–AIN6
AIN4–AIN6
AIN1–AIN2
AIN3–AIN4
AIN5–AIN6
1
1
2
2
1
2
3
Do Not Use
AIN1–AIN6
AIN2–AIN6
AIN3–AIN6
AIN4–AIN6
AIN5–AIN6
AIN1–AIN2
AIN3–AIN4
AIN5–AIN6
Do Not Use
1
1
2
2
3
1
2
3
Do Not Use
X = Don’t care
Table 9. Transfer-Function Register Mapping—Offset-Calibration Mode (M1 = 0, M0 = 1)
20
SCAN
DIFF
A1
A0
CHANNEL
TRANSFERFUNCTION REGISTER
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
1
CALOFF+–CALOFFCALOFF+–CALOFFCALOFF+–CALOFFCALOFF+–CALOFFCALOFF+–CALOFFCALOFF+–CALOFFCALOFF+–CALOFF-
1
1
2
2
1
2
3
Do Not Use
AIN1–AIN6
AIN2–AIN6
AIN3–AIN6
AIN4–AIN6
AIN5–AIN6
CALOFF+–CALOFFCALGAIN+–CALGAINAIN1–AIN2
AIN3–AIN4
AIN5–AIN6
CALOFF+–CALOFFCALGAIN+–CALGAIN-
1
1
2
2
3
3
3
1
2
3
3
3
Do Not Use
______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
SCAN
DIFF
A1
A0
CHANNEL
TRANSFERFUNCTION REGISTER
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
1
CALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAIN-
1
1
2
2
1
2
3
Do Not Use
AIN1–AIN6
AIN2–AIN6
AIN3–AIN6
AIN4–AIN6
AIN5–AIN6
CALOFF+–CALOFFCALGAIN+–CALGAINAIN1–AIN2
AIN3–AIN4
AIN5–AIN6
CALOFF+–CALOFFCALGAIN+–CALGAIN-
1
1
2
2
3
3
3
1
2
3
3
3
Do Not Use
X = Don’t care
Data Register (Read-Only)
The data register is a 24-bit, read-only register. Any
attempt to write data to this location will have no effect.
If a write operation is attempted, 8 bits of data must be
clocked into the part before it will return to its normal
idle mode, expecting a write to the communications
register.
D17–D0: The conversion result. D17 is the MSB. The
result is in offset binary format. 00 0000 0000 0000
0000 represents the minimum value, and 11 1111 1111
1111 1111 represents the maximum value. Inputs
exceeding the available input range are limited to the
corresponding minimum or maximum output values.
0: This reserved bit will always be 0.
Data is output MSB first, followed by one reserved 0 bit,
two auxiliary data bits, and a 3-bit channel ID tag indicating the channel from which the data originated.
Data Register (Read-Only) Bits
First Bit (Data MSB)
DATA BITS
D17
D16
D15
D14
D13
D12
D11
D10
D5
D4
D3
D2
DATA BITS
D9
D8
D7
D6
(Data LSB)
DATA BITS
D1
(LSB)
RESERVED
D0
‘0’
AUXILIARY DATA
DS1
DS0
CHANNEL ID TAG
CID2
CID1
CID0
______________________________________________________________________________________
21
MAX1403
Table 10. Transfer-Function Register Mapping—Gain-Calibration Mode (M1 = 1, M0 = 0)
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
channels. Table 12 shows the channel configurations
available for both operating modes.
Table 11. Channel ID Tag Codes
CID2
0
CID1
0
CID0
0
CHANNEL
AIN1–AIN6
0
0
1
AIN2–AIN6
0
1
0
AIN3–AIN6
0
1
1
AIN4–AIN6
1
0
0
AIN1–AIN2
1
0
1
AIN3–AIN4
1
1
0
AIN5–AIN6
1
1
1
Calibration
DS1, DS0: The status of the auxiliary data input pins.
These are latched on the first falling edge of the SCLK
signal for the current data register read access.
CID2–0: Channel ID tag (Table 11).
Switching Network
A switching network provides selection between three
fully differential input channels or five pseudo-differential channels, using AIN6 as a shared common. The
switching network provides two additional fully differential input channels intended for system calibration,
which may be used as extra fully differential signal
Scanning (SCAN-Mode)
To sample and convert the available input channels
sequentially, set the SCAN control bit in the global
setup register. The sequence is determined by DIFF
(fully differential or pseudo-differential) and by the
mode control bits M1 and M0 (Tables 8, 9, 10). With
SCAN set, the device automatically sequences through
each available channel, transmitting a single conversion result before proceeding to the next channel. The
MAX1403 automatically allows sufficient time for each
conversion to fully settle, to ensure optimum resolution
before asserting the data-ready signal and moving to
the next available channel. The scan rate is, therefore,
dependent on the clock bit (CLK), the filter control bits
(FS1, FS0), and the modulator frequency selection bits
(MF1, MF0).
Burn-Out Currents
The input circuitry also provides two “burn-out” currents. These small currents may be used to test the
integrity of the selected transducer. They can be selectively enabled or disabled by the BOUT bit in the global
setup register.
Table 12. Input Channel Configuration in Fully Differential and Pseudo-Differential
Mode (SCAN = 0)
M1
M0
DIFF
A1
A0
HIGH INPUT
LOW INPUT
0
0
0
0
0
MODE
AIN1
AIN6
0
0
0
0
1
AIN2
AIN6
0
0
0
1
0
AIN3
AIN6
0
0
0
1
1
AIN4
AIN6
0
0
X
X
X
AIN5*
AIN6*
0
1
X
X
X
CALOFF+**
CALOFF-**
1
0
X
X
X
CALGAIN+**
CALGAIN-**
0
0
1
0
0
AIN1
AIN2
0
0
1
0
1
AIN3
AIN4
0
0
1
1
0
AIN5
AIN6
0
1
X
X
X
CALOFF+**
CALOFF-**
1
0
X
X
X
CALGAIN+**
CALGAIN-**
PseudoDifferential
Fully
Differential
X = Don’t care
* This combination is available only in pseudo-differential mode when using the internal scanning logic.
** These combinations are only available in the calibration modes.
22
______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
REXT
RMUX
CEXT
Dynamic Input Impedance at the
Channel Selection Network
When used in unbuffered mode (BUFF = 0), the analog
inputs present a dynamic load to the driving circuitry.
The size of the sampling capacitor and the input sampling frequency (Figure 5) determine the dynamic load
seen by the driving circuitry. The MAX1403 samples at a
constant rate for all gain settings. This provides a maximum time for the input to settle at a given data rate. The
dynamic load presented by the inputs varies with the
gain setting. For gains of +2V/V, +4V/V, and +8V/V, the
input sampling capacitor increases with the chosen
gain. Gains of +16V/V, +32V/V, +64V/V, and +128V/V
present the same input load as the x8 gain setting.
CPIN
MAX1403
Transducer Excitation Currents
The MAX1403 provides two matched 200µA transducer
excitation currents at OUT1 and OUT2. These currents
have low absolute temperature coefficients and tight
TC matching. These characteristics enable accurate
compensation of errors due to IR drops in long transducer cable runs. They may be enabled or disabled
using a single register control bit (IOUT).
RSW
CST
CSAMPLE
CC
Figure 5. Analog Input, Unbuffered Mode (BUFF = 0)
phase margin and reduces the possibility of ringing.
The resistor spreads the transient-load current from the
sampler over time due to the RC time constant of the
circuit. However, an improperly chosen series resistance can hinder performance in fast 16-bit converters.
The settling time of the RC network can limit the speed
at which the converter can operate properly, or reduce
the settling accuracy of the sampler. In practice, this
means ensuring that the RC time constant—resulting
from the product of the driving source impedance and
the capacitance presented by both the MAX1403’s
input and any external capacitances—is sufficiently
small to allow settling to the desired accuracy. Tables
13a–13d summarize the maximum allowable series
resistance vs. external capacitance for each MAX1403
gain setting in order to ensure 16-bit performance in
unbuffered mode.
When designing with the MAX1403, as with any other
switched-capacitor ADC input, consider the advantages
and disadvantages of series input resistance. A series
resistor reduces the transient-current impulse to the
external driving amplifier. This improves the amplifier
Table 13a. REXT, CEXT Values for Less than 16-Bit Gain Error in Unbuffered (BUFF = 0)
Mode—1x Modulator Sampling Frequency (MF1, MF0 = 00); X2CLK = 0; CLKIN = 2.4576MHz
PGA GAIN
EXTERNAL RESISTANCE, REXT (kΩ)
CEXT = 0pF
CEXT = 50pF
CEXT = 100pF
CEXT = 500pF
CEXT = 1000pF
CEXT = 5000pF
1
34
15
9.8
2.9
1.6
0.43
2
34
15
9.8
2.9
1.6
0.43
4
25
13
8.7
2.7
1.5
0.40
8, 16, 32,
64, 128
17
10
7.3
2.4
1.4
0.37
Table 13b. REXT, CEXT Values for Less than 16-Bit Gain Error in Unbuffered (BUFF = 0)
Mode—2x Modulator Sampling Frequency (MF1, MF0 = 01); X2CLK = 0; CLKIN =
2.4576MHz
PGA GAIN
EXTERNAL RESISTANCE, REXT (kΩ)
CEXT = 0pF
CEXT = 50pF
CEXT = 100pF
CEXT = 500pF
CEXT = 1000pF
CEXT = 5000pF
1
17
7.5
4.9
1.4
0.81
0.22
2
17
7.5
4.9
1.4
0.81
0.22
4
13
6.4
4.4
1.3
0.76
0.20
8, 16, 32,
64, 128
8.4
5.0
3.7
1.2
0.70
0.18
______________________________________________________________________________________
23
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Table 13c. REXT, CEXT Values for Less than 16-Bit Gain Error in Unbuffered (BUFF = 0)
Mode—4x Modulator Sampling Frequency (MF1, MF0 = 10 ); X2CLK = 0; CLKIN =
2.4576MHz
EXTERNAL RESISTANCE, REXT (kΩ)
PGA GAIN
CEXT = 0pF
CEXT = 50pF
CEXT = 100pF
CEXT = 500pF
CEXT = 1000pF
CEXT = 5000pF
1
8.3
3.7
2.4
0.72
0.40
0.11
2
8.3
3.7
2.4
0.72
0.40
0.11
4
6.2
3.2
2.2
0.67
0.38
0.10
8, 16, 32,
64, 128
4.1
2.5
1.8
0.60
0.35
0.09
Table 13d. REXT, CEXT Values for Less than 16-Bit Gain Error in Unbuffered (BUFF = 0)
Mode—8x Modulator Sampling Frequency (MF1, MF0 = 11); X2CLK = 0; CLKIN =
2.4576MHz
EXTERNAL RESISTANCE, REXT (kΩ)
PGA GAIN
CEXT = 0pF
CEXT = 50pF
CEXT = 100pF
CEXT = 500pF
CEXT = 1000pF
CEXT = 5000pF
1
4.1
1.8
1.2
0.35
0.20
0.05
2
4.1
1.8
1.2
0.35
0.20
0.05
4
3.0
1.5
1.1
0.32
0.18
0.05
8, 16, 32,
64, 128
2.0
1.2
0.88
0.29
0.17
0.04
Input Buffers
The MAX1403 provides a pair of input buffers to isolate
the inputs from the capacitive load presented by the
PGA/modulator (Figure 6). The buffers are chopper stabilized to reduce the effect of their DC offsets and lowfrequency noise. Since the buffers can represent more
than 50% of the total analog power dissipation, they may
be shut down in applications where minimum power dissipation is required and the capacitive input load is not a
REXT
CEXT
RMUX
CPIN
concern. Disable the buffers in applications where the
inputs must operate close to AGND or V+.
When used in buffered mode, the buffers isolate the
inputs from the sampling capacitors. The samplingrelated gain error is dramatically reduced in this mode.
A small dynamic load remains from the chopper stabilization. The multiplexer exhibits a small input leakage
current of up to 10nA. With high source resistances,
this leakage current may result in a DC offset.
RIN
CST
CAMP
CSAMPLE
Figure 6. Analog Input, Buffered Mode (BUFF = 1)
24
______________________________________________________________________________________
CC
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
PGA GAIN
EXTERNAL RESISTANCE, REXT (kΩ)
CEXT = 0pF
CEXT = 50pF
CEXT = 100pF
CEXT = 500pF
CEXT = 1000pF
CEXT = 5000pF
1
10
10
10
10
10
10
2
10
10
10
10
10
10
4
10
10
10
10
10
10
8
10
10
10
10
10
10
16
10
10
10
10
10
10
32
10
10
10
10
10
10
64
10
10
10
10
10
10
128
10
10
10
10
10
10
Reference Input
The MAX1403 is optimized for ratiometric measurements and includes a fully differential reference input.
Apply the reference voltage across REFIN+ and REFIN-,
ensuring that REFIN+ is more positive than REFIN-.
REFIN+ and REFIN- must be between AGND and V+.
The MAX1403 is specified with a +1.25V reference.
Modulator
The MAX1403 performs analog-to-digital conversion
using a single-bit, second-order, switched-capacitor
modulator. A single comparator within the modulator
quantizes the input signal at a much higher sample rate
than the bandwidth of the signal to be converted. The
quantizer then presents a stream of 1s and 0s to the
digital filter for processing, to remove the frequencyshaped quantization noise.
The MAX1403 modulator provides 2nd-order frequency
shaping of the quantization noise resulting from the single bit quantizer. The modulator is fully differential for
maximum signal-to-noise ratio and minimum susceptibility to power-supply noise.
The modulator operates at one of a total of eight different sampling rates (fM) determined by the master clock
frequency (fCLKIN), the X2CLK bit, the CLK bit, and the
modulator frequency control bits MF1 and MF0. Power
dissipation is optimized for each of these modes by
controlling the bias level of the modulator. Table 15
shows the input and reference sample rates.
PGA
A programmable gain amplifier (PGA) with a userselectable gain of x1, x2, x4, x8, x16, x32, x64, or x128
(Table 6) precedes the modulator. Figure 8 shows the
default bipolar transfer function with the following illustrated codes: 1) PGA = 0, DAC = 0; 2) PGA = 3, DAC =
0; or 3) PGA = 3, DAC = 3.
Output Noise
Tables 16a and 16b show the rms noise for typical output frequencies (notches) and -3dB frequencies for the
MAX1403 with f CLKIN = 2.4576MHz. The numbers
given are for the bipolar input ranges with V REF =
+1.25V, with no buffer (BUFF = 0), and with the buffer
inserted (BUFF = 1). These numbers are typical and
are generated at a differential analog input voltage of 0.
Figure 7 shows graphs of Effective Resolution vs. Gain
and Notch Frequency. The effective resolution values
were derived from the following equation:
Effective Resolution = (SNRdB - 1.76dB) / 6.02
The maximum possible signal divided by the noise of
the device, SNRdB, is defined as the ratio of the input
full-scale voltage (i.e., 2 · VREFIN / GAIN) to the output
rms noise. Note that it is not calculated using peak-topeak output noise numbers. Peak-to-peak noise numbers can be up to 6.6 times the rms numbers, while
effective resolution numbers based on peak-to-peak
noise can be 2.5 bits below the effective resolution
based on rms noise, as quoted in the tables.
The noise shown in Tables 16a and 16b is composed
of device noise and quantization noise. The device
noise is relatively low, but becomes the limiting noise
source for high gain settings. The quantization noise is
dependent on the notch frequency and becomes the
dominant noise source as the notch frequency is
increased.
______________________________________________________________________________________
25
MAX1403
Table 14. REXT, CEXT Values for Less than 16-Bit Gain Error in Buffered (BUFF = 1)
Mode—All Modulator Sampling Frequencies (MF1, MF0 = XX); X2CLK = 0; CLKIN =
2.4576MHz
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Table 15. Modulator Operating Frequency, Sampling Frequency, and 16-Bit Data Output
Rates
CLKIN FREQUENCY,
fCLKIN (MHz)
MODULATOR
FREQUENCY,
fM
(kHz)
AVAILABLE
OUTPUT
DATA RATES
AT 16-BIT
ACCURACY
(sps)
20, 25
CLK
MF1
MF0
AIN/REFIN
SAMPLING
FREQUENCY,
fS
(kHz)
2.048
0
0
0
16
8
2.048
0
0
1
32
16
40, 50
2.048
0
1
0
64
32
80, 100
160, 200
X2CLK = 0
DEFAULT
X2CLK = 1
1.024
1.024
1.024
1.024
2.048
0
1
1
128
64
2.4576
4.9152
1
0
0
38.4
19.2
50, 60
2.4576
4.9152
1
0
1
76.8
38.4
100, 120
2.4576
4.9152
1
1
0
153.6
76.8
200, 240
2.4576
4.9152
1
1
1
307.2
153.6
400, 480
Note: Default condition is in bold print.
Table 16a. Noise vs. Gain and Output Data Rate—Unbuffered Mode, VREF = 1.25V,
fCLKIN = 2.4576MHz
OUTPUT
DATA
RATE
(sps)
-3dB
FREQ.
(Hz)
x1
x2
x4
x8
x16
x32
x64
x128
MF1:MF0 = 0
50
13.1
5.42
3.03
1.70
1.11
1.06
1.05
1.05
1.04
FS1:FS0 = 0
60
15.7
5.91
3.20
1.90
1.25
1.13
1.18
1.15
1.15
FS1:FS0 = 1
300
78.6
80.5
38.6
20.6
10.3
5.73
3.62
2.84
2.67
FS1:FS0 = 2
600
157.2
441
236
112
54.8
29.2
14.5
7.61
5.13
TYPICAL OUTPUT NOISE (µVRMS)
FOR VARIOUS PROGRAMMABLE GAINS
BIT
STATUS
FS1:FS0 = 3
MF1:MF0 = 1
100
26.2
5.53
2.96
1.73
1.13
1.06
1.06
1.08
1.05
FS1:FS0 = 0
120
31.4
6.06
3.28
1.90
1.25
1.17
1.11
1.12
1.11
FS1:FS0 = 1
600
157.2
81.5
39.9
19.6
10.2
5.45
3.49
2.72
2.59
FS1:FS0 = 2
1200
314.4
450
232
115
53.4
27.8
14.7
8.00
5.08
FS1:FS0 = 3
MF1:MF0 = 2
200
52.4
5.39
2.92
1.70
1.09
1.06
1.02
1.02
1.03
FS1:FS0 = 0
240
62.9
6.27
3.28
1.89
1.20
1.18
1.14
1.17
1.11
FS1:FS0 = 1
1200
314.4
77.8
40.1
20.1
10.0
5.53
3.56
2.74
2.59
FS1:FS0 = 2
2400
628.8
431
232
109
54.9
28.2
14.1
8.08
4.99
FS1:FS0 = 3
MF1:MF0 = 3
26
400
104.8
5.36
3.00
1.82
1.17
1.10
1.06
1.10
1.11
FS1:FS0 = 0
480
125.7
5.88
3.25
1.94
1.28
1.26
1.16
1.17
1.15
FS1:FS0 = 1
2400
628.8
79.7
39.6
20.2
10.5
5.74
3.63
3.02
2.76
FS1:FS0 = 2
4800
1258
441
227
111
55.5
29.7
14.6
7.73
5.43
FS1:FS0 = 3
______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
OUTPUT
DATA
RATE
(sps)
-3dB
FREQ.
(Hz)
x1
x2
x4
x8
x16
x32
x64
x128
MF1:MF0 = 0
50
13.1
5.72
3.21
2.10
1.41
1.42
1.44
1.38
1.34
FS1:FS0 = 0
60
15.7
6.29
3.57
2.30
1.55
1.61
1.56
1.49
1.56
FS1:FS0 = 1
300
78.6
80.6
39.8
19.3
10.2
6.14
4.25
3.03
3.52
FS1:FS0 = 2
600
157.2
436
225
116
57.1
28.8
15.0
8.70
5.99
TYPICAL OUTPUT NOISE (µVRMS)
FOR VARIOUS PROGRAMMABLE GAINS
BIT
STATUS
FS1:FS0 = 3
MF1:MF0 = 1
100
26.2
5.82
3.35
2.08
1.43
1.37
1.36
1.35
1.31
FS1:FS0 = 0
120
31.4
6.01
3.65
2.27
1.51
1.51
1.50
1.50
1.47
FS1:FS0 = 1
600
157.2
77.7
40.1
20.2
10.6
5.93
4.19
3.54
3.23
FS1:FS0 = 2
1200
314.4
434
222
111
57.0
28.3
14.8
8.37
5.81
FS1:FS0 = 3
MF1:MF0 = 2
200
52.4
5.82
3.07
1.87
1.26
1.20
1.18
1.15
1.17
FS1:FS0 = 0
240
62.9
6.17
3.54
2.09
1.45
1.30
1.27
1.31
1.29
FS1:FS0 = 1
1200
314.4
79.0
41.1
19.8
10.5
5.68
3.68
3.14
2.99
FS1:FS0 = 2
2400
628.8
439
226
111
57.9
28.7
15.4
8.26
5.32
FS1:FS0 = 3
MF1:MF0 = 3
400
104.8
5.60
3.10
1.85
1.32
1.24
1.25
1.19
1.21
FS1:FS0 = 0
480
125.7
6.18
3.47
2.02
1.38
1.37
1.29
1.33
1.33
FS1:FS0 = 1
2400
628.8
76.3
39.3
20.8
9.83
5.92
3.92
3.92
3.07
FS1:FS0 = 2
4800
1258
455
225
114
57.1
29.9
14.5
8.13
5.55
FS1:FS0 = 3
20
20
CLK = 1
18
FS1: FS0 = 0 OR 1
17
16
FS1: FS0 = 2
15
14
FS1: FS0 = 3
13
12
CLK = 1
BUFF = 0
11
10
18
FS1: FS0 = 0 OR 1
17
16
FS1: FS0 = 2
15
14
FS1: FS0 = 3
13
12
CLK = 1
BUFF = 1
11
10
1
a) BUFF = 0
19
EFFECTIVE RESOLUTION (BITS)
EFFECTIVE RESOLUTION (BITS)
19
2
4
8
16 32
GAIN (V/V)
64
128 256
1
b) BUFF = 1
2
4
8
16
32
64
128 256
GAIN (V/V)
Figure 7. Effective Resolution vs. Gain and Notch Frequency
______________________________________________________________________________________
27
MAX1403
Table 16b. Noise vs. Gain and Output Data Rate—Buffered Mode, VREF = 1.25V,
fCLKIN = 2.4576MHz
Clock Oscillator
The clock oscillator may be used with an external crystal
(or resonator) connected between CLKIN and CLKOUT,
or may be driven directly by an external oscillator at
CLKIN with CLKOUT left unconnected. In normal operating mode, the MAX1403 is specified for operation with
CLKIN at either 1.024MHz (CLK = 0) or 2.4576MHz
(CLK = 1, default). When operated at these frequencies,
the device may be programmed to produce frequency
response nulls at the local line frequency (either 60Hz or
50Hz) and the associated line harmonics.
MAX CODE 262144
FULL-SCALE 259522
PGA = 3
DAC = 0
PGA = 0
DAC = 0
PGA = 3
DAC = +3
MIDSCALE 131072
NEGATIVE DAC STEP
SHIFTS THE TRANSFER
FUNCTION TOWARD
THE POSITIVE RAIL.
V+
(VAIN-) + VREF
(VAIN-) + VREF/8
(VAIN-)
(VAIN-) - VREF/8 - VREF/16
(VAIN-) - VREF/8
(VAIN-) - VREF/8 - VREF/16
AGND
(VAIN-)-VREF
ZERO-SCALE 2621
INPUT VOLTAGE RANGE
In standby mode (STBY = 1) all circuitry, with the
exception of the serial interface and the clock oscillator,
is powered down. The interface consumes minimal
power with a static SCLK. Enter power-down mode
(including the oscillator) by setting the FULLPD bit in
the special-function register. When exiting a full-power
shutdown, perform a hardware reset or a software reset
after the master clock signal is established (typically
10ms when using the on-board oscillator with an external crystal) to ensure that any potentially corrupted registers are cleared.
It is often helpful to use higher-frequency crystals or
resonators, especially for surface-mount applications
where the result may be reduced PC board area for the
oscillator component and a lower price or better component availability. Also, it may be necessary to operate the part with a clock source whose duty cycle is not
close to 50%. In either case, the MAX1403 can operate
with a master clock frequency of up to 5MHz, and
includes an internal divide-by-2 prescaler to restore the
internal clock frequency to a range of up to 2.5MHz
with a 50% duty cycle. To activate this prescaler, set
the X2CLK bit in the control registers. Note that using
CLKIN frequencies above 2.5MHz in combination with
the X2CLK mode will result in a small increase in digital
supply current.
(VREF = 1.25V
PGA = 000)
2.708V
2.50V
2.292V
2.083V
1.875V
1.667V
1.458V
1.25V
1.042V
0.833V
0.625V
0.416V
0.208V
0V
-0.208V
-0.416V
-0.625V
-0.833V
-1.042V
-1.25V
-1.458V
-1.667V
-1.875V
-2.083V
-2.292V
-2.50V
-2.708V
-7 -6
D3: 1 1
D2: 1 1
D1: 1 1
D0: 1 0
MA
XIM
UM
INP
UT
MI
NIM
UM
INP
UT
MI
(U
/B
NIM
UM
=1
)
INP
UT
(U
/B
=0
)
-5
1
1
0
1
-4
1
1
0
0
-3
1
0
1
1
-2
1
0
1
0
-1
1
0
1
0
0
0
0
0
0
+1
0
0
0
1
+2
0
0
1
0
+3
0
0
1
1
+4
0
1
0
0
+5
0
1
0
1
+6
0
1
1
0
DAC CODE
Figure 8. Effect of PGA and DAC Codes on the Bipolar Transfer
Function
28
Figure 9. Input Voltage Range vs. DAC Code
______________________________________________________________________________________
+7
0
1
1
1
13/6 VREF/2PGA
2 VREF/2PGA
11/6 VREF/2PGA
10/6 VREF/2PGA
9/6 VREF/2PGA
8/6 VREF/2PGA
7/6 VREF/2PGA
VREF/2PGA
5/6 VREF/2PGA
4/6 VREF/2PGA
3/6 VREF/2PGA
2/6 VREF/2PGA
1/6 VREF/2PGA
0
-1/6 VREF/2PGA
-2/6 VREF/2PGA
-3/6 VREF/2PGA
-4/6 VREF/2PGA
-5/6 VREF/2PGA
-VREF/2PGA
-7/6 VREF/2PGA
-8/6 VREF/2PGA
-9/6 VREF/2PGA
-10/6 VREF/2PGA
-11/6 VREF/2PGA
-2 VREF/2PGA
-13/6 VREF/2PGA
INPUT VOLTAGE RANGE
Offset-Correction DAC
The MAX1403 provides a coarse (3-bit plus sign) offsetcorrection DAC at the modulator input. Use this DAC to
remove the offset component in the input signal, allowing the ADC to operate on a more sensitive range. The
DAC offsets up to ±116.7% of the selected range in
±16.7% increments for unipolar mode, and up to
±58.3% of the selected range in ±8.3% increments for
bipolar mode. When a DAC value of 0 is selected, the
DAC is completely disconnected from the modulator
inputs and does not contribute any noise. Figures 8
and 9 show the effect of the DAC codes on the input
range and transfer function.
CODE
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
The SINC1 function results in a faster settling response
while retaining the same frequency response notches
as the default SINC3 filter. This allows the filter to settle
faster at the expense of resolution and quantization
noise. The SINC1 filter settles in one data word period.
With 60Hz notches (60Hz data rate), the settling time
would be 1 / 60Hz or 16.7ms, whereas the SINC3 filter
would settle in 3 / 60Hz or 50ms. Toggle between these
filter responses using the FAST bit in the global setup
register. Use SINC1 mode for faster settling and switch
to SINC3 mode when full accuracy is required. Switch from
the SINC1 to SINC3 mode by resetting the FAST bit low.
The DRDY signal will go false and will be reasserted
when valid data is available, a minimum of three dataword periods later.
The digital filter can be bypassed by setting the MDOUT
bit in the global setup register. When MDOUT = 1, the
raw output of the modulator is directly available at DOUT.
Filter Characteristics
The MAX1403 digital filter implements both a SINC1
(sinx/x) and SINC3 (sinx/x)3 lowpass filter function. The
transfer function for the SINC3 function is that of three
cascaded SINC1 filters described in the z-domain by:
1
H(z) =
N
⋅
1 − z −N
1 – z −1
of 15.72Hz for a first filter notch frequency of 60Hz. The
response shown in Figure 10 is repeated at either side
of the digital filter’s sample frequency (fM) and at either
side of the related harmonics (2fM, 3fM, . . .).
The response of the SINC3 filter is similar to that of a
SINC1 (averaging filter) filter but with a sharper rolloff.
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s frequency response. Therefore, for the plot of Figure 10
where the first notch of the filter is at 60Hz, the output
data rate is 60Hz. The notches of this (sinx/x)3 filter are
repeated at multiples of the first notch frequency. The
SINC 3 filter provides an attenuation of better than
100dB at these notches.
Determine the cutoff frequency of the digital filter by the
value loaded into CLK, X2CLK, MF1, MF0, FS1, and FS0
in the global setup register. Programming a different
cutoff frequency with FS0 and FS1 does not alter the
profile of the filter response; it changes the frequency of
the notches. For example, Figure 11 shows a cutoff frequency of 13.1Hz and a first notch frequency of 50Hz.
For step changes at the input, a settling time must be
allowed before valid data can be read. The settling time
depends upon the output data rate chosen for the filter.
The settling time of the SINC3 filter to a full-scale step
input can be up to four-times the output data period.
For a synchronized step input (using the FSYNC function or the internal scanning logic), the settling time is
three-times the output data period.
3
0
-40
⋅
f
sin Nπ
fM
f
sin π
fM
3
where N, the decimation factor, is the ratio of the modulator frequency fM to the output frequency fN.
Figure 10 shows the filter frequency response. The
SINC3 characteristic cutoff frequency is 0.262 times the
first notch frequency. This results in a cutoff frequency
GAIN (dB)
and in the frequency domain by:
1
H(f) =
N
fCLKIN = 2.4576MHz
MF1, 0 = 0
FS1, 0 = 1
fN = 60Hz
-20
-60
-80
-100
-120
-140
-160
0
20 40 60 80 100 120 140 160 180 200
FREQUENCY (Hz)
Figure 10. Frequency Response of the SINC3 Filter (Notch at
60Hz)
______________________________________________________________________________________
29
MAX1403
Digital Filter
The on-chip digital filter processes the 1-bit data
stream from the modulator using a SINC3 or SINC1 filter. The SINC filters are conceptually simple, efficient,
and extremely flexible, especially where variable resolution and data rates are required. Also, the filter notch
positions are easily controlled since they are directly
related to the output data rate (1 / data word period).
Analog Filtering
Calibration Channels
The digital filter does not provide any rejection close to
the harmonics of the modulator sample frequency.
However, due to the high oversampling ratio of the
MAX1403, these bands occupy only a small fraction of
the spectrum and most broadband noise is filtered.
Therefore, the analog filtering requirements in front of
the MAX1403 are considerably reduced compared to a
conventional converter with no on-chip filtering. In addition, because the part’s common-mode rejection of
90dB extends out to several kHz, common-mode noise
susceptibility in this frequency range is substantially
reduced.
Two fully differential calibration channels allow measurement of the system gain and offset errors. Connect
the CALOFF channel to 0V and the CALGAIN channel
to the reference voltage. Average several measurements on both CALOFF and CALGAIN. Subtract the
average offset code and scale to correct for the gain
error. This linear calibration technique can be used to
remove errors due to source impedances on the analog
input (e.g., when using a simple RC anti-aliasing filter
on the front end).
Depending on the application, it may be necessary to
provide filtering prior to the MAX1403 to eliminate
unwanted frequencies the digital filter does not reject. It
may also be necessary in some applications to provide
additional filtering to ensure that differential noise signals outside the frequency band of interest do not saturate the analog modulator.
If passive components are placed in front of the
MAX1403, when the part is used in unbuffered mode,
ensure that the source impedance is low enough not to
introduce gain errors in the system (Tables 13a–13d).
This can significantly limit the amount of passive antialiasing filtering that can be applied in front of the
MAX1403 in unbuffered mode. However, when the part
is used in buffered mode, large source impedances will
simply result in a small DC offset error (a 1kΩ source
resistance will cause an offset error of less than 10µV).
Therefore, where any significant source impedances
are required, Maxim recommends operating the part in
buffered mode.
Applications Information
SPI Interface (68HC11, PIC16C73)
Microprocessors with a hardware SPI (serial peripheral
interface) can use a 3-wire interface to the MAX1403
(Figure 12). The SPI hardware generates groups of
eight pulses on SCLK, shifting data in on one pin and
out on the other pin.
For best results, use a hardware interrupt to monitor the
INT pin and acquire new data as soon as it is available.
If hardware interrupts are not available, or if interrupt
latency is longer than the selected conversion rate, use
the FSYNC bit to prevent automatic measurement while
reading the data output register.
The example code in Listing 1 shows how to interface
with the MAX1403 using a 68HC11. System-dependent
initialization code is not shown.
VDD
0
fCLKIN = 2.4576MHz
MF1, 0 = 0
FS1, 0 = 0
fN = 50Hz
-20
-40
GAIN (dB)
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
VDD
SS
INTERRUPT
-60
-80
68HC11
-100
RESET
INT
SCK
SCLK
MISO
DOUT
MOSI
DIN
-120
-140
CS
-160
0
20 40 60 80 100 120 140 160 180 200
FREQUENCY (Hz)
Figure 11. Frequency Response of the SINC3 Filter
(Notch at 50Hz)
30
Figure 12. MAX1403 to 68HC11 Interface
______________________________________________________________________________________
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
MAX1403
/* Assumptions:
**
The MAX140X's CS pin is tied to ground
**
The MAX140X's INT pin drives a falling-edge-triggered interrupt
**
MAX140X's DIN is driven by MOSI, DOUT drives MISO, and SCLK drives SCLK
*/
/* Low-level function to write 8 bits using 68HC11 SPI */
void WriteByte (BYTE x)
{
/* System-dependent: write to SPI hardware and wait until it is finished */
HC11_SPDR = x;
while (HC11_SPSR & HC11_SPSR_SPIF) { /* idle loop */ }
}
/* Low-level function to read 8 bits using 68HC11 SPI */
BYTE ReadByte (void)
{
/* System-dependent: use SPI hardware to clock in 8 bits */
HC11_SPDR = 0xFF;
while (HC11_SPSR & HC11_SPSR_SPIF) { /* idle loop */ }
return HC11_SPDR;
}
/* Low-level interrupt handler called whenever the MAX140X's INT pin goes low.
** This function reads new data from the MAX140X and feeds it into a
** user-defined function Process_Data().
*/
void HandleDRDY (void)
{
BYTE data_H_bits, data_M_bits, data_L_bits; /* storage for data register */
WriteByte(0x78);
/* read the latest data regsiter value */
data_H_bits = ReadByte();
data_M_bits = ReadByte();
data_L_bits = ReadByte();
Process_Data(data_H_bits, data_M_bits, data_L_bits);
/* System-dependent: re-enable the interrupt service routine */
}
/* High-level function to configure the MAX140X's registers
** Refer to data sheet for custom setup values.
*/
void Initialize (void)
{
/* System-dependent: configure the SPI hardware (CPOL=1,CPHA=1) */
/* write to all of configuration registers */
MY_GS1 = 0x0A; MY_GS2 = 0x00; MY_GS3 = 0x00;
MY_TF1 = 0x00; MY_TF2 = 0x00; MY_TF3 = 0x00;
WriteByte(0x10); WriteByte(MY_GS1); /* write Global Setup 1 */
WriteByte(0x20); WriteByte(MY_GS2); /* write Global Setup 2 */
WriteByte(0x30); WriteByte(MY_GS3); /* write Global Setup 3 */
WriteByte(0x40); WriteByte(MY_TF1); /* write Transfer Function 1 */
WriteByte(0x50); WriteByte(MY_TF2); /* write Transfer Function 2 */
WriteByte(0x60); WriteByte(MY_TF3); /* write Transfer Function 3 */
/* System-dependent: enable the data-ready (DRDY) interrupt handler */
}
Listing 1. Example SPI Interface
______________________________________________________________________________________
31
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
MAX1403
Bit-Banging Interface (80C51, PIC16C54)
VDD
RESET
8051
P3.0
DOUT
DIN
P3.1
SCLK
CS
MAX1403
Any microcontroller can use general-purpose I/O pins
to interface to the MAX1403. If a bidirectional or opendrain I/O pin is available, reduce the interface pin count
by connecting DIN to DOUT (Figure 13). Listing 2
shows how to emulate the SPI in software. Use the
same initialization routine shown in Listing 1.
For best results, use a hardware interrupt to monitor the
INT pin and acquire new data as soon as it is available.
If hardware interrupts are not available, or if interrupt
latency is longer than the selected conversion rate, use
the FSYNC bit to prevent automatic measurement while
reading the data output register.
Figure 13. MAX1403 to 8051 Interface
/* Low-level function to write 8 bits
** The example shown here is for a bit-banging system with (CPOL=1, CPHA=1)
*/
void WriteByte (BYTE x)
{
drive SCK pin high
count = 0;
while (cout <= 7)
{
if (bit 7 of x is 1)
drive DIN pin high
else
drive DIN pin low
drive SCK pin low
x = x * 2;
drive SCK pin high
count = count + 1;
}
}
/* Low-level function to read 8 bits
** The example shown here is for a bit-banging system with (CPOL=1, CPHA=1)
*/
BYTE ReadByte (void)
{
x = 0;
drive SCK pin high
count = 0;
while (cout <= 7)
{
x = x * 2;
drive SCK pin low
if (DOUT pin is high)
x = x + 1;
drive SCK pin high
count = count + 1;
}
}
return x;
Listing 2. Bit-Banging SPI Replacement
32
______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Temperature Measurement
Figure 15 shows a connection from a thermocouple to
the MAX1403. In this application, the MAX1403 is operated in its buffered mode to allow large decoupling
capacitors on the front end. These decoupling capacitors eliminate any noise pickup from the thermocouple
leads. When the MAX1403 is operated in buffered
mode, it has a reduced common-mode range. In order
to place the differential voltage from the thermocouple
on a suitable common-mode voltage, the AIN2 input of
the MAX1403 is biased at the reference voltage,
+1.25V.
ANALOG SUPPLY
V+
REFIN+
VDD
V+
RREF
CLOCK
GEN
DIVIDER
MAX1403
CLKIN
CLKOUT
REFINACTIVE
GAUGE
BUFFER
BUFFER
R
AIN1
AIN2
DUMMY
GAUGE
R
SWITCHING
NETWORK
PGA
ADDITIONAL
ANALOG
AND
CALIBRATION
CHANNELS
OUT1
MODULATOR
DIGITAL
FILTER
BUFFER
BUFFER
DAC
AGND
OUT2
AGND
INTERFACE
AND
CONTROL
SCLK
DIN
DOUT
INT
CS
RESET
DS1
DS0
DGND
Figure 14. Strain-Gauge Application with MAX1403
______________________________________________________________________________________
33
MAX1403
Strain-Gauge Operation
Connect the differential inputs of the MAX1403 to the
bridge network of the strain gauge. In Figure 14, the
analog positive supply voltage powers the bridge network and the MAX1403 along with its reference voltage.
The on-chip PGA allows the MAX1403 to handle an
analog input voltage range as low as 10mV full scale.
The differential inputs of the device allow this analog
input range to have an absolute value anywhere
between AGND and V+.
Loop-Powered, 4–20mA Transmitters
Low-power, single-supply operation, and easy interfacing with optocouplers make the MAX1403 ideal for
loop-powered 4–20mA transmitters. Loop-powered
transmitters draw their power from the 4–20mA loop,
limiting the transmitter circuitry to a current budget of
4mA. Tolerances in the loop further limit this current
budget to 3.5mA. Since the MAX1403 consumes only
250µA, a total of 3.25mA remains to power the remaining transmitter circuitry. Figure 16 shows a block diagram for a loop-powered 4–20mA transmitter.
MAX1403
THERMOCOUPLE
JUNCTION
R
AIN1
SWITCHING
NETWORK
R
PGA
BUFFER
AIN2
C
3-Wire and 4-Wire RTD Configurations
C
+3V
+1.25V
Tightly matched 200µA current sources compensate for
errors in 3-wire and 4-wire RTD configurations. In the 3wire configuration (Figure 17), the lead resistances
result in errors if only one current source is used. The
200µA will flow through RL1 developing a voltage error
between AIN1 and AIN2. An additional current source
compensates for this error by developing an equivalent
voltage across RL2, ensuring the differential voltage at
AIN1 and AIN2 is not affected by lead resistance. This
assumes both leads are of the same material and of
equal length (R L1 = R L2 ), and assumes OUT1 and
OUT2 have matching tempcos (5ppm/°C). Both current
sources will flow through RL3, developing a commonmode voltage that will not affect the differential voltage
at AIN1 and AIN2. Using one of the current sources to
supply the reference voltage ensures a more accurate
ratiometric result.
REFIN+
REFINAGND
DGND
Figure 15. Thermocouple Application with MAX1403
V+
ISOLATION
BARRIER
V+
VOLTAGE
REGULATOR
VIN+
ROFST
RX
RGAIN
SENSOR
MAX1403
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
4
4
SPI
SPI
µP/µC
3
RY
4–20mA LOOP
INTERFACE
DAC
SPI
CC
GND
GND
RFDBK
RSENSE
VIN-
Figure 16. 4–20mA Transmitter
34
______________________________________________________________________________________
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
MAX1403
+3V
V+
VDD
200µA
V+
REFIN- REFIN+
VDD
200µA
OUT1
OUT2
MAX1403
12.5k
REFIN+
MODULATOR
AIN1
RL1
RTD
AIN2
MODULATOR
RREF
PGA
REFIN-
GAIN = 1 TO 128
200µA
OUT2
OUT1
RL2
200µA
AGND
MAX1403
RL3
AIN1
DGND
RTD
PGA
Figure 17. 3-Wire RTD Application
AIN2
Unlike the 3-wire configuration, the 4-wire configuration
(Figure 18) has no error associated with lead resistances, as no current flows in the measurement leads
connected to AIN1 and AIN2. Current source OUT1
provides the excitation current for the RTD, and current
source OUT2 provides current to generate the reference voltage. This reference voltage, developed across
R REF , ensures that the analog input voltage span
remains ratiometric to the reference voltage. RTD tempco errors in the analog input voltage are due to the temperature drift of the RTD current source and are
compensated for by the variation in the reference voltage. A common resistance value for the RTD is 100Ω,
generating a 20mV signal directly handled at the analog input of the MAX1403. The voltage at OUT1 and
OUT2 can go to within 1.0V of the V+ supply.
AGND
GAIN = 1 TO 128
Power Supplies
No specific power sequence is required for the
MAX1403; either the V+ or the VDD supply can come
up first. While the latchup performance of the MAX1403
is good, to avoid latchup it is important that power be
applied to the MAX1403 before the analog input signals
(AIN_) or the CLKIN inputs. If this is not possible, then
the current flow into any of these pins should be limited
to 50mA. If separate supplies are used for the
MAX1403 and the system digital circuitry, then the
MAX1403 should be powered up first.
DGND
Figure 18. 4-Wire RTD Application
Grounding and Layout
For best performance, use printed circuit boards with
separate analog and digital ground planes. Wire-wrap
boards are not recommended.
Design the printed circuit board so that the analog and
digital sections are separated and confined to different
areas of the board. Join the digital and analog ground
planes at only one point. If the MAX1403 is the only
device requiring an AGND to DGND connection, then
the ground planes should be connected at the AGND
and DGND pins of the MAX1403. In systems where multiple devices require AGND to DGND connections, the
connection should still be made at only one point. Make
the star ground as close to the MAX1403 as possible.
Avoid running digital lines under the device because
these may couple noise onto the die. Run the analog
ground plane under the MAX1403 to minimize coupling
of digital noise. Make the power-supply lines to the
MAX1403 as wide as possible to provide low-impedance paths and reduce the effects of glitches on the
power-supply line.
______________________________________________________________________________________
35
Shield fast switching signals, such as clocks, with digital ground to avoid radiating noise to other sections of
the board. Avoid running clock signals near the analog
inputs. Avoid crossover of digital and analog signals.
Traces on opposite sides of the board should run at
right angles to each other. This will reduce the effects
of feedthrough on the board. A microstrip technique is
best but is not always possible with double-sided
boards. In this technique, the component side of the
board is dedicated to ground planes while signals are
placed on the solder side.
Good decoupling is important when using high-resolution ADCs. Decouple all analog supplies with 10µF tantalum capacitors in parallel with 0.1µF HF ceramic
capacitors to AGND. Place these components as close
to the device as possible to achieve the best decoupling.
See the MAX1403 evaluation kit manual for the recommended layout. The evaluation board package includes
a fully assembled and tested evaluation board.
Chip Information
TRANSISTOR COUNT: 34,648
SUBSTRATE CONNECTED TO AGND
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
2
SSOP.EPS
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
+5V,
Oversampling (Sigma-Delta) ADC
1
INCHES
E
H
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A
0.068
0.078
1.73
1.99
A1
0.002
0.008
0.05
0.21
B
0.010
0.015
0.25
0.38
C
D
0.20
0.09
0.004 0.008
SEE VARIATIONS
E
0.205
e
0.212
0.0256 BSC
5.20
INCHES
D
D
D
D
D
5.38
MILLIMETERS
MIN
MAX
MIN
MAX
0.239
0.239
0.278
0.249
0.249
0.289
6.07
6.07
7.07
6.33
6.33
7.33
0.317
0.397
0.328
0.407
8.07
10.07
8.33
10.33
N
14L
16L
20L
24L
28L
0.65 BSC
H
0.301
0.311
7.65
7.90
L
0.025
0∞
0.037
8∞
0.63
0∞
0.95
8∞
N
A
C
B
e
A1
L
D
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL
DOCUMENT CONTROL NO.
21-0056
REV.
C
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.