AD S1 258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com 16-Channel, 24-Bit Analog-to-Digital Converter Check for Samples: ADS1258 FEATURES DESCRIPTION • • • • • • • • • • The ADS1258 is a 16-channel (multiplexed), low-noise, 24-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC) that provides single-cycle settled data at channel scan rates from 1.8k to 23.7k samples per second (SPS) per channel. A flexible input multiplexer accepts combinations of eight differential or 16 single-ended inputs with a full-scale differential range of 5V or true bipolar range of ±2.5V when operating with a 5V reference. The fourth-order delta-sigma modulator is followed by a fifth-order sinc digital filter optimized for low-noise performance. 1 23 • • • • • • • • 24 Bits, No Missing Codes Fixed-Channel or Automatic Channel Scan Fixed-Channel Data Rate: 125kSPS Auto-Scan Data Rate: 23.7kSPS/Channel Single-Conversion Settled Data 16 Single-Ended or 8 Differential Inputs Unipolar (+5V) or Bipolar (±2.5V) Operation Low Noise: 2.8μVRMS at 1.8kSPS 0.0003% Integral Nonlinearity DC Stability (typical): 0.02μV/°C Offset Drift, 0.4ppm/°C Gain Drift Open-Sensor Detection Conversion Control Pin Multiplexer Output for External Signal Conditioning On-Chip Temperature, Reference, Offset, Gain, and Supply Voltage Readback 42mW Power Dissipation Standby, Sleep, and Power-Down Modes 8 General-Purpose Inputs/Outputs (GPIO) 32.768kHz Crystal Oscillator or External Clock The differential output of the multiplexer is accessible to allow signal conditioning prior to the input of the ADC. Internal system monitor registers provide supply voltage, temperature, reference voltage, gain, and offset data. An onboard PLL generates the system clock from a 32.768kHz crystal, or can be overridden by an external clock source. A buffered system clock output (15.7MHz) is provided to drive a microcontroller or additional converters. Serial digital communication is handled via an SPI™ -compatible interface. A simple command word structure controls channel configuration, data rates, digital I/O, monitor functions, etc. APPLICATIONS Programmable sensor bias current sources can be used to bias sensors or verify sensor integrity. • • • • • The ADS1258 operates from a unipolar +5V or bipolar ±2.5V analog supply and a digital supply compatible with interfaces ranging from 2.7V to 5.25V. The ADS1258 is available in a QFN-48 package. Medical, Avionics, and Process Control Machine and System Monitoring Fast Scan Multi-Channel Instrumentation Industrial Systems Test and Measurement Systems AVDD DVDD VREF Internal Monitoring GPIO[7:0] ADS1258 GPIO Digital Filter SPI Interface CS DRDY SCLK DIN DOUT Oscillator Control START RESET PWDN Analog Inputs … 1 24−Bit ADC 16:1 Analog Input MUX 16 AINCOM AVSS MUX OUT ADC IN Extclk In/Out 32.768kHz DGND 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2011, Texas Instruments Incorporated ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the ADS1258 device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). ADS1258 UNIT AVDD to AVSS –0.3 to +5.5 V AVSS to DGND –2.8 to +0.3 V DVDD to DGND –0.3 to +5.5 V Input Current 100, Momentary mA Input Current 10, Continuous mA AVSS – 0.3 to AVDD + 0.3 V Analog Input Voltage –0.3 to DVDD + 0.3 V +150 °C Operating Temperature Range –40 to +105 °C Storage Temperature Range –60 to +150 °C Digital Input Voltage to DGND Maximum Junction Temperature (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS All specifications at TA = –40°C to +105°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, VREF = +4.096V, VREFN = –2.5V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), and OPA227 buffer between MUX outputs and ADC inputs, unless otherwise noted. ADS1258 TEST CONDITIONS PARAMETER MIN TYP MAX UNIT AVDD + 100mV V ANALOG MULTIPLEXER INPUTS Absolute Input Voltage AIN0–AIN15, AINCOM with respect to DGND AVSS – 100mV 80 Ω fIN = 1kHz –110 dB SBCS[1:0] = 01 1.5 SBCS[1:0] = 11 24 On-Channel Resistance Crosstalk Sensor Bias (Current Source) 1.5μA:24μA Ratio Error μA 1 % ADC INPUT Full-Scale Input Voltage (VIN = ADCINP – ADCINN) Absolute Input Voltage (ADCINP, ADCINN) ±1.06 VREF AVSS – 100mV Differential Input Impedance V AVDD + 100mV V 65 kΩ SYSTEM PERFORMANCE Resolution No Missing Codes 24 Data Rate, Fixed-Channel Mode Data Rate, Auto-Scan Mode Offset Drift (3) 125 1.805 Integral Nonlinearity (INL) (1) Offset Error Bits 1.953 Differential Input Chopping Off 0.0003 Chopping Off 1 kSPS 0.0010 % of FSR (2) μV 10 0.5 Shorted Inputs Chopping On 23.739 20 Shorted Inputs Chopping On kSPS μV/°C 0.02 0.1 Gain Error 0.1 0.5 % Gain Drift (3) 0.4 2 ppm/°C Noise (see Table 6) Common-Mode Rejection Power-Supply Rejection fCM = 60Hz AVDD, AVSS fPS = 60Hz DVDD 90 100 70 85 80 95 0.5 4.096 dB dB VOLTAGE REFERENCE INPUT AVDD – AVSS V Negative Reference Input (VREFN) AVSS – 0.1V VREFP – 0.5 V Positive Reference Input (VREFP) VREFN + 0.5 AVDD + 0.1V Reference Input Voltage (VREF = VREFP – VREFN) Reference Input Impedance V 40 kΩ SYSTEM PARAMETERS External Reference Reading Error 1 3 Analog Supply Reading Error 1 3 Voltage Temperature Sensor Reading (1) (2) (3) (4) (5) Coefficient % % TA = +25°C (4) 168 mV See note (4) 394 μV/°C (5) 563 μV/°C See note Best straight line fit method. FSR = Full-scale range = 2.13VREF. Ensured by characterization. Only ADS1258 temperature forced; test PCB in free-air. ADS1258 and test PCB temperatures forced together. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 3 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = –40°C to +105°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, VREF = +4.096V, VREFN = –2.5V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), and OPA227 buffer between MUX outputs and ADC inputs, unless otherwise noted. ADS1258 TEST CONDITIONS PARAMETER MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic Levels VIH 0.7DVDD DVDD V VIL DGND 0.3DVDD V V VOH IOH = 2mA 0.8DVDD DVDD VOL IOL = 2mA DGND 0.2DVDD V 10 μA MHz Input Leakage Master Clock Input (CLKIO) Crystal Oscillator (see Crystal Oscillator section) VIN = DVDD, GND Frequency 0.1 16 Duty Cycle 40 60 % Crystal Frequency 32.768 kHz Clock Output Frequency 15.729 MHz Start-Up Time (Clock Output Valid) 150 Clock Output Duty Cycle mS 40 60 % DVDD 2.7 5.25 V AVSS –2.6 0 V AVDD AVSS + 4.75 AVSS + 5.25 V 0.6 mA POWER SUPPLY DVDD Supply Current AVDD, AVSS Supply Current Power Dissipation (6) (7) 4 External Clock Operation 0.25 Internal Oscillator Operation, Clock Output Disabled 0.04 mA Internal Oscillator Operation, Clock Output Enabled (6) 1.4 mA Power-Down (7) 1 25 µA Converting 8.2 12 mA Standby 5.6 Sleep 2.1 Power-Down 2 85 µA Converting 42 62 mW Standby 29 mW Sleep 11 mW Power-Down 14 μW mA mA CLKIO load = 20pF. No clock applied to CLKIO. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com PIN CONFIGURATION AIN4 AIN5 AIN6 AIN7 MUXOUTP MUXOUTN ADCINP ADCINN AIN8 AIN9 AIN10 AIN11 RTC PACKAGE QFN-48 (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 AIN3 1 36 AIN12 AIN2 2 35 AIN13 AIN1 3 34 AIN14 AIN0 4 33 AIN15 AVSS 5 32 AINCOM AVD D 6 31 VREFP ADS1258 PLLCAP 7 30 VREFN XTAL1 8 29 DGND XTAL2 9 28 DVDD PWDN 10 RESET 27 CS 11 26 START CL KSEL 12 18 19 20 21 22 23 24 GPIO6 GPIO7 SCLK DI N DOUT GPIO1 17 GPIO5 GPIO0 16 GPIO4 15 GPIO3 14 GPIO2 13 CLKIO 25 DRDY PIN ASSIGNMENTS PIN # NAME ANALOG/DIGITAL INPUT/OUTPUT 1 AIN3 Analog Input Analog Input 3: Single-Ended Channel 3, Differential Channel 1 (–) 2 AIN2 Analog Input Analog Input 2: Single-Ended Channel 2, Differential Channel 1 (+) 3 AIN1 Analog Input Analog Input 1: Single-Ended Channel 1, Differential Channel 0 (–) 4 AIN0 Analog Input Analog Input 0: Single-Ended Channel 0, Differential Channel 0 (+) 5 AVSS Analog Negative Analog Power Supply: 0V for unipolar operation, –2.5V for bipolar operation. (Internally connected to exposed thermal pad of QFN package.) 6 AVDD Analog Positive Analog Power Supply: +5V for unipolar operation, +2.5V for bipolar operation. 7 PLLCAP Analog PLL Bypass Capacitor: Connect 22nF capacitor to AVSS when using crystal oscillator. 8 XTAL1 Analog 32.768kHz Crystal Oscillator Input 1; see Crystal Oscillator section. 9 XTAL2 Analog 32.768kHz Crystal Oscillator Input 2; see Crystal Oscillator section. 10 PWDN Digital Input Power-Down Input: Hold low for minimum of two fCLK cycles to engage low-power mode. 11 RESET Digital Input Reset Input: Hold low for minimum of two fCLK cycles to reset the device. 12 CLKSEL Digital Input Clock Select Input: Low = Activates Crystal Oscillator, fCLK output on CLKIO. High = Disables Crystal Oscillator, apply fCLK to CLKIO. 13 CLKIO Digital I/O System Clock Input/Output (See CLKSEL pin.) 14 GPIO0 Digital I/O General-Purpose Digital Input/Output 0 15 GPIO1 Digital I/O General-Purpose Digital Input/Output 1 16 GPIO2 Digital I/O General-Purpose Digital Input/Output 2 17 GPIO3 Digital I/O General-Purpose Digital Input/Output 3 18 GPIO4 Digital I/O General-Purpose Digital Input/Output 4 19 GPIO5 Digital I/O General-Purpose Digital Input/Output 5 DESCRIPTION Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 5 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com PIN ASSIGNMENTS (continued) 6 PIN # NAME ANALOG/DIGITAL INPUT/OUTPUT 20 GPIO6 Digital I/O General-Purpose Digital Input/Output 6 21 GPIO7 Digital I/O General-Purpose Digital Input/Output 7 22 SCLK Digital Input SPI Interface Clock Input: Data clocked in on rising edge, clocked out on falling edge. 23 DIN Digital Input SPI Interface Data Input: Data is input to the device. 24 DOUT Digital Output SPI Interface Data Output: Data is output from the device. 25 DRDY Digital Output Data Ready Output: Active low. 26 START Digital Input Start Conversion Input: Active high. 27 CS Digital Input SPI Interface Chip Select Input: Active low. 28 DVDD Digital Digital Power Supply: 2.7V to 5.25V 29 DGND Digital Digital Ground 30 VREFN Analog Input Reference Input Negative 31 VREFP Analog Input Reference Input Positive 32 AINCOM Analog Input Analog Input Common: Common input pin to all single-ended inputs. 33 AIN15 Analog Input Analog Input 15: Single-Ended Channel 15, Differential Channel 7 (–) 34 AIN14 Analog Input Analog Input 14: Single-Ended Channel 14, Differential Channel 7 (+) 35 AIN13 Analog Input Analog Input 13: Single-Ended Channel 13, Differential Channel 6 (–) 36 AIN12 Analog Input Analog Input 12: Single-Ended Channel 12, Differential Channel 6 (+) 37 AIN11 Analog Input Analog Input 11: Single-Ended Channel 11, Differential Channel 5 (–) 38 AIN10 Analog Input Analog Input 10: Single-Ended Channel 10, Differential Channel 5 (+) 39 AIN9 Analog Input Analog Input 9: Single-Ended Channel 9, Differential Channel 4 (–) 40 AIN8 Analog Input Analog Input 8: Single-Ended Channel 8, Differential Channel 4 (+) 41 ADCINN Analog Input ADC Differential Input (–) 42 ADCINP Analog Input ADC Differential Input (+) 43 MUXOUTN Analog Output Multiplexer Differential Output (–) 44 MUXOUTP Analog Output Multiplexer Differential Output (+) 45 AIN7 Analog Input Analog Input 7: Single-Ended Channel 7, Differential Channel 3 (–) 46 AIN6 Analog Input Analog Input 6 : Single-Ended Channel 6, Differential Channel 3 (+) 47 AIN5 Analog Input Analog Input 5: Single-Ended Channel 5, Differential Channel 2 (–) 48 AIN4 Analog Input Analog Input 4: Single-Ended Channel 4, Differential Channel 2 (+) DESCRIPTION Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION CS(1) tCSPW tCSSC tSCLK tSPW SCLK tSPW tDIST DIN tDIHD tDOPD Hi-Z Hi-Z DOUT tCSDO tDOHD NOTE: (1) CS can be tied low. Figure 1. Serial Interface Timing Table 1. SERIAL INTERFACE TIMING CHARACTERISTICS At TA= –40°C to +105°C and DVDD = 2.7V to 5.25V, unless otherwise noted. (1) (2) (3) (4) SYMBOL DESCRIPTION MIN tSCLK SCLK Period 2 MAX UNITS τCLK (1) τCLK tSPW SCLK High or Low Pulse Width (exceeding max resets SPI interface) 0.8 tCSSC CS Low to First SCLK: Setup Time (3) 2.5 τCLK ns tDIST Valid DIN to SCLK Rising Edge: Setup Time 10 tDIHD Valid DIN to SCLK Rising Edge: Hold Time 5 tDOPD SCLK Falling Edge to Valid New DOUT: Propagation Delay (4) tDOHD SCLK Falling Edge to Old DOUT Invalid: Hold Time tCSDO CS High to DOUT Invalid (tri-state) tCSPW CS Pulse Width High 4096 (2) ns 20 ns 0 ns 5 τCLK τCLK 2 τCLK = master clock period = 1/fCLK. Programmable to 256 τCLK. CS can be tied low. DOUT load = 20 pF || 100kΩ to DGND. t DRDY DRDY tDDO DOUT Figure 2. DRDY Update Timing Table 2. DRDY UPDATE TIMING CHARACTERISTICS SYMBOL DESCRIPTION TYP UNITS t DRDY DRDY High Pulse Width Without Data Read 1 τCLK tDDO Valid DOUT to DRDY Falling Edge (CS = 0) 0.5 τCLK Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 7 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted. READING HISTOGRAM READING HISTOGRAM Number of Occurrences 2500 4500 DRATE[1:0] = 11 16384 Points DRATE[1:0] = 10 16384 Points 4000 Number of Occurrences 3000 2000 1500 1000 500 3500 3000 2500 2000 1500 1000 500 0 Offset (µV) READING HISTOGRAM 35 30 25 20 15 DRATE[1:0] = 00 16384 Points DRATE[1:0] = 01 16384 Points Number of Occurrences 2500 2000 1500 1000 2000 1500 1000 500 0 Offset (µV) 12 10 8 6 4 2 0 −2 −4 −6 −8 −12 20 16 12 8 4 0 −4 −8 −12 −16 −20 0 −10 Number of Occurrences 5 READING HISTOGRAM 2500 500 Offset (µV) Figure 5. Figure 6. NOISE HISTOGRAM NOISE vs INPUT VOLTAGE 20 50 units from two production lots. DRATE[1:0] = 11 15 15 RMS Noise (µV) Number of Occurrences 10 Figure 4. 3500 20 0 Offset (µV) Figure 3. 3000 −5 −10 −15 −20 −25 −30 −35 −50 −45 −40 −35 −30 −25 −20 −15 −10 5 0 5 10 15 20 25 30 35 40 45 50 0 10 DRATE[1:0] = 11 10 5 5 0 0 −100 DRATE[1:0] = 10 DRATE[1:0] = 01 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 DRATE[1:0] = 00 −75 −50 −25 0 25 50 75 100 Input Voltage (%FS) RMS Noise (µV) Figure 7. 8 Figure 8. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted. NOISE vs VREF 20 14 18 12 10 DRATE[1:0] = 10 8 DRATE[1:0] = 11 16 DRATE[1:0] = 11 RMS Noise (µV) RMS Noise (µV) NOISE vs SUPPLY VOLTAGE 16 6 DRATE[1:0] = 01 14 from DVDD 12 10 from AVDD−AVSS 8 4 DRATE[1:0] = 00 2 6 0 4 1.5 2.5 3.5 4.5 2.5 5.5 3.0 VREF (V) 3.5 4.0 5.0 Figure 9. Figure 10. NOISE vs TEMPERATURE NOISE AND OFFSET vs COMMON-MODE INPUT VOLTAGE 20 5.5 20 5 DRATE[1:0] = 11 OFFSET CHOP = 1 18 15 RMS Noise (µV) 16 RMS Noise (µV) 4.5 DVDD, AVDD−AVSS (V) 14 12 10 8 0 10 −5 NOISE OFFSET CHOP = 0 5 Offset (µV) 0.5 −10 6 −40 −20 0 20 40 60 80 −3 100 −2 Temperature (_C) 0 1 2 3 Figure 12. OFFSET HISTOGRAM OFFSET DRIFT HISTOGRAM 80 200 180 −1 Common−Mode Input Voltage (V) Figure 11. 311 units from one production lot. CHOP = 1 160 Number of Occurrences Number of Occurrences −15 0 4 140 120 100 80 60 40 60 50 units from two production lots. Based on 20_ C intervals over the range of −40_C to +105_ C. CHOP = 1 40 20 20 10 8 6 4 2 0 −2 −4 −6 −8 −10 Offset (µV) −0.10 −0.09 −0.08 −0.07 −0.06 −0.05 −0.04 −0.03 −0.02 −0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0 0 Offset Drift (µV/_ C) Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 9 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted. OFFSET vs TEMPERATURE OFFSET vs VREF 20 10 CHOP = 1, No Buffer 8 Normalized Offset (µV) Normalized Offset (µV) CHOP = 1 0 −20 −40 CHOP = 0, No Buffer −60 −20 0 20 40 60 80 4 2 0 −2 −4 −6 −8 50 units from two production lots. −40 6 −10 100 0.5 1.0 1.5 2.0 2.5 Temperature (_ C) Figure 15. 4.0 4.5 5.0 5.5 GAIN ERROR HISTOGRAM 80 Free−Air 320 units from one production lot. 8 6 Number of Occurrences Normalized Offset (µV) 3.5 Figure 16. OFFSET POWER-ON WARMUP 10 3.0 VREF (V) 4 2 0 −2 −4 −6 60 40 20 −8 −10 1900 1700 1500 Time After Power−On (s) 1300 60 1100 50 900 40 700 30 500 20 100 10 300 0 0 Absolute Gain Error (ppm) Figure 17. Figure 18. GAIN DRIFT HISTOGRAM GAIN ERROR vs TEMPERATURE 30 50 units from two production lots. Based on 20_C intervals over the range of −40_ C to +105_ C. Normalized Gain Error (ppm) Number of Occurrences 80 60 40 20 20 10 0 −10 −1.8 −1.6 −1.4 −1.2 −1.0 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 −40 −20 0 20 40 60 80 100 Temperature (_ C) Gain Drift (ppm/_ C) Figure 19. 10 Figure 20. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted. GAIN ERROR POWER-ON WARMUP 10 15 8 Normalized Gain Error (ppm) Normalized Gain Error (ppm) GAIN ERROR vs VREF 20 10 5 0 −5 −10 −15 Free−Air 6 4 2 0 −2 −4 −6 −8 −20 −10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 5.0 10 20 VREF (V) Figure 21. 40 50 60 Figure 22. INTEGRAL NONLINEARITY vs VREF INTEGRAL NONLINEARITY vs INPUT LEVEL 10 10 VREF = 5V TA = −40_C, −10_ C, +25_ C, +55_ C, +85_ C, +105_C 8 6 Linearity Error (ppm) 8 Linearity Error (ppm) 30 Time After Power−On (s) 6 4 4 2 0 −2 −4 2 −6 0 −10 −8 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 −5 5.0 −4 −3 −2 −1 VREF (V) Figure 23. 1 2 3 4 5 Figure 24. INTEGRAL NONLINEARITY vs TEMPERATURE OUTPUT SPECTRUM 8 0 f = 1kHz, -0.5dBFS DRATE[1:0] = 11 65536 Points -20 -40 Level (dBFS) 6 INL (ppm) 0 VIN (V) 4 -60 -80 -100 -120 2 -140 -160 0 −40 −20 -180 0 20 40 60 80 100 120 1 Temperature (_ C) 10 100 1k 10k 100k Frequency (Hz) Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 11 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +2.5V, AVSS = –2.5V, DVDD = +3.3V, fCLK = 16MHz (external clock) or fCLK = 15.729MHz (internal clock), OPA227 buffer between MUX outputs and ADC inputs, VREFP = +2.048V, and VREFN = –2.048V, unless otherwise noted. TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE TEMPERATURE SENSOR READING HISTOGRAM 8 220 ADS1258 and Test PCB Temperatures Forced Together Temperature Sensor Voltage (mV) 210 Number of Occurrences 200 190 180 170 Only ADS1258 Temperature Forced; Test PCB in Free-Air 160 150 140 6 5 4 3 2 1 130 120 0 0 -20 20 40 60 Temperature (°C) 80 100 120 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 -40 Temperature Reading (_C) Figure 27. Figure 28. SENSOR BIAS CURRENT SOURCE RATIO HISTOGRAM SENSOR BIAS CURRENT SOURCE RATIO vs TEMPERATURE 25 18 50 units from two production lots. 20 17 Ratio (µA/µA) Number of Occurrences 50 units from two production lots. TA = +25_C 7 15 10 16 15 5 14 −40 19.0 18.5 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 0 −20 0 20 40 60 80 100 120 Temperature (_C) Ratio (µA/µA) Figure 29. Figure 30. SUPPLY CURRENT vs TEMPERATURE 10 NOISE AND INL vs MASTER CLOCK 20 1.0 4 0.4 2 0.2 DVDD −20 0 20 40 60 80 100 0 120 16 Noise 12 12 8 8 4 4 Linearity 0 0.1 1 10 Temperature (_C) Master Clock (MHz) Figure 31. Figure 32. Submit Documentation Feedback Linearity Error (ppm) 0.6 RMS Noise (µV) 6 0 12 16 0.8 DVDD Current (mA) AVDD, AVSS Current (mA) 8 −40 20 DRATE[1:0] = 11 AVDD, AVSS 0 100 Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com OVERVIEW VIN = (ADCINP – ADCINN), against the differential reference input, VREF = (VREFP – VREFN). The digital filter receives the modulator signal and provides a low-noise digital output. The ADC channel block controls the multiplexer Auto-Scan feature. Channel Auto-Scan occurs at a maximum rate of 23.7kSPS. Slower scan rates can be used with corresponding increases in resolution. The ADS1258 is a flexible, 24-bit, low-noise ADC optimized for fast multi-channel, high-resolution measurement systems. The converter provides a maximum channel scan rate of 23.7kSPS, providing a complete 16-channel scan in less than 700μs. Figure 33 shows the block diagram of the ADS1258. The input multiplexer selects the analog input pins connected to the multiplexer output pins (MUXOUTP/MUXOUTN). External signal conditioning can be used between the multiplexer output pins and the ADC input pins (ADCINP/ADCINN) or the multiplexer output can be routed internally to the ADC inputs without external circuitry. Selectable current sources within the input multiplexer can be used to bias sensors or detect for a failed sensor. On-chip system function readings provide readback of temperature, supply voltage, gain, offset, and external reference. Communication is handled over an SPI-compatible serial interface with a set of simple commands providing control of the ADS1258. Onboard registers store the various settings for the input multiplexer, sensor detect bias, data rate selection, etc. Either an external 32.768kHz crystal, connected to pins XTAL1 and XTAL2, or an external clock applied to pin CLKIO can be used as the clock source. When using the external crystal oscillator, the system clock is available as an output for driving other devices or controllers. General-purpose digital I/Os (GPIO) provide input and output control of eight pins. The ADS1258 converter is comprised of a fourth-order, delta-sigma modulator followedby a programmable digital filter. The modulator measures the differential input signal, DVDD AVDD GPIO[7:0] CLKIO CLKSEL PLLCAP XTAL2 XTAL1 Clock Control GPIO AIN0 Sensor Bias AIN1 CS AIN2 SPI Interface AIN3 AIN4 Temperature DRDY AIN6 AIN8 DIN DOUT Supply Monitor AIN5 AIN7 SCLK 16−Channel MUX Control Logic ADC Channel Control PWDN RESET START AIN9 AIN10 Internal Ref AIN11 AIN12 Ext Ref Monitor AIN13 ADC AIN14 Digital Filter AIN15 AINCOM AVSS MUXOUTP MUXOUTN ADCINP ADCINN VREFN VREFP GND Figure 33. ADS1258 Block Diagram Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 13 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com MULTIPLEXER INPUTS A simplified diagram of the input multiplexer is illustrated in Figure 35. The multiplexer connects one of 16 single-ended external inputs, one of eight differential external inputs, or one of the on-chip internal variables to the ADC inputs. The output of the channel multiplexer can be routed to external pins and then to the input of the ADC. This flexibility allows for use of external signal conditioning. See the External Multiplexer Loop section. ESD diodes protect the analog inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below AVSS by more than 100mV, and likewise do not exceed AVDD by more than 100mV: AVDD ESD Diodes VREFP 3pF Reff = 40kΩ (fCLK = 16MHz) VREFN ESD Diodes AVSS – 100mV < (Analog Inputs) < AVDD + 100mV. Overdriving the multiplexer inputs may affect the conversions of other channels. See the Input Overload Protection description in the Hardware Considerations segment of the Applications section. The converter supports two modes of channel access through the multiplexer: the Auto-Scan mode and the Fixed-Channel mode. These modes are selected by the MUXMOD bit of register CONFIG0. The Auto-Scan mode scans through the selected channels automatically, with break-before-make switching. The Fixed-Channel mode requires the user to set the channel address for each channel measured. VOLTAGE REFERENCE INPUTS (VREFP, VREFN) The voltage reference for the ADS1258 ADC is the differential voltage between VREFP and VREFN: VREF = VREFP – VREFN. The reference inputs use a structure similar to that of the analog inputs with the circuitry on the reference inputs shown in Figure 34. The load presented by the switched capacitor can be modeled with an effective resistance (Reff) of 40kΩ for fCLK = 16MHz. Note that the effective impedance of the reference inputs will load an external reference with a non-zero source impedance. 14 AVSS Figure 34. Simplified Reference Input Circuit ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AVSS by more than 100mV, and likewise do not exceed AVDD by 100mV, as described in Equation 1: AVSS * 100mV t ǒVREFP or VREFNǓ t AVDD ) 100mV (1) A high-quality reference voltage is essential for achieving the best performance from the ADS1258. Noise and drift on the reference degrade overall system performance. It is especially critical that special care be given to the circuitry that generates the reference voltages and the layout when operating in the low-noise settings (that is, with low data rates) to prevent the voltage reference from limiting performance. See the Reference Inputs description in the Hardware Considerations segment of the Applications section. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com VREFP VREFN Multiplexer Reference/Gain Monitor AIN0 AIN1 AIN2 Temperature Sensor Monitor AVDD AIN3 1x AIN4 2x AIN5 8x 1x AIN6 AVSS AIN7 Supply Monitor AIN8 AVDD AVSS AIN9 AIN10 AIN11 NOTE: ESD diodes not shown. Internal Reference AIN12 AVSS AIN13 AIN14 ADC AIN15 AINCOM (AVDD − AVSS)/2 ADCINN ADCINP Offset Monitor MUXOUTP Sensor Bias MUXOUTN AVSS AVDD Figure 35. Input Multiplexer Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 15 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com ADC INPUTS The ADS1258 ADC inputs (ADCINP, ADCINN) measure the input signal using internal capacitors that are continuously charged and discharged. The left side of Figure 37 shows a simplified schematic of the ADC input circuitry; the right side of Figure 37 shows the input circuitry with the capacitors and switches replaced by an equivalent circuit. Figure 36 shows the ON/OFF timings of the switches shown in Figure 37. S1 switches close during the input sampling phase. With S1 closed, CA1 charges to ADCINP, CA2 charges to ADCINN, and CB charges to (ADCINP – ADCINN). For the discharge phase, S1 opens first and then S2 closes. CA1 and CA2 discharge to approximately AVSS + 1.3V and CB discharges to 0V. This two-phase sample/discharge cycle repeats with a period of tSAMPLE = 2/fCLK. The charging of the input capacitors draws a transient current from the source driving the ADS1258 ADC inputs. The average value of this current can be used to calculate an effective impedance (Reff) where Reff = VIN/IAVERAGE. These impedances scale inversely with fCLK. For example, if fCLK is reduced by a factor of two, the impedances will double. As with the multiplexer and reference inputs, ESD diodes protect the ADC inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below AVSS by more than 100mV, and likewise do not exceed AVDD by more than 100mV. t SAMPLE ON S1 OFF ON S2 OFF Figure 36. S1 and S2 Switch Timing for Figure 37 AVSS + 1.3V AVSS + 1.3V S2 ReffA = 190kΩ CA1 = 0.65pF S1 Equivalent Circuit ADCINP ADCINP ReffB = 78kΩ CB = 1.6pF S1 (fCLK = 16MHz) ADCINN ADCINN ReffA = 190kΩ CA2 = 0.65pF S2 Reff = t SAMPLE/CX AVSS + 1.3V AVSS + 1.3V RAIN = ReffB || 2ReffA NOTE: ESD input diodes not shown. Figure 37. Simplified ADC Input Structure 16 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com MASTER CLOCK (fCLK) The ADS1258 oversamples the analog input at a high rate. This requires a high-frequency master clock to be supplied to the converter. As shown in Figure 38, the clock comes from either an internal oscillator (with external crystal), or an external clock source. 50Ω CLKSEL XTAL1 CLKENB Bit XTAL2 CLKIO Clock Output (15.729MHz) AVSS 0V to −2.5V PLLCAP 32.768kHz(1) 22nF 4.7pF 4.7pF Internal Master Clock (fCLK) NOTE: (1) Parallel resonant type, CL = 12.5pF, ESR = 35kΩ(max). Place the crystal and load capacitors as close as possible to the device pins. MUX CLKIO Figure 39. Crystal Oscillator Connection Oscillator and PLL CLKSEL XTAL1 XTAL2 Table 3. System Clock Source PLL Figure 38. Clock Generation Block Diagram The CLKSEL pin determines the source of the system clock, as shown in Table 3. The CLKIO pin functions as an input or as an output. When the CLKSEL pin is set to '1', CLKIO is configured as an input to receive the master clock. When the CLKSEL pin is set to '0', the crystal oscillator generates the clock. The CLKIO pin can then be configured to output the master clock. When the clock output is not needed, it can be disabled to reduce device power consumption. Crystal Oscillator An on-chip oscillator and Phase-Locked Loop (PLL) together with an external crystal can be used to generate the system clock. For this mode, tie the CLKSEL pin low. A 22nF PLL filter capacitor, connected from the PLLCAP pin to the AVSS pin, is required. The internal clock of the PLL can be output to the CLKIO to drive other converters or controllers. If not used, disable the clock output to reduce device power consumption; see Table 3 for settings. The clock output is enabled by a register bit setting (default is ON). Figure 39 shows the oscillator connections. Place these components as close to the pins as possible to avoid interference and coupling. Do not connect XTAL1 or XTAL2 to any other logic. The oscillator start-up time may vary, depending on the crystal and ambient temperature. The user should verify the oscillator start-up time. CLKSEL PIN CLOCK SOURCE CLKENB BIT CLKIO FUNCTION 0 32.768kHz Crystal Oscillator 0 Disabled (internally grounded) 0 32.768kHz Crystal Oscillator 1 Output (15.729MHz) 1 External Clock Input X Input (16MHz) Table 4. Approved Crystals VENDOR CRYSTAL PRODUCT Epson C-001R Epson MC-306 32.7680K-A0 Epson FC-135 32.7680KA-A0 ECS ECS-.327-12.5-17-TR External Clock Input When using an external clock to operate the device, apply the master clock to the CLKIO pin. For this mode, the CLKSEL pin is tied high. CLKIO then becomes an input, as shown in Figure 40. 50Ω CLKIO 2.7V to 5V Clock Input (16MHz) DVDD CLKSEL XTAL1 XTAL2 PLLCAP No Connection Figure 40. External Clock Connection Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 17 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com Make sure to use a clock source clean from jitter or interference. Ringing or under/overshoot should be avoided. A 50Ω resistor in series with the CLKIO pin (placed close to the source) can often help. ADC The ADC block of the ADS1258 is composed of two blocks: a modulator and a digital filter. Modulator The modulator converts the analog input voltage into a Pulse Code Modulated (PCM) data stream. When the level of differential analog input (ADCINP – ADCINN) is near the level of the reference voltage, the '1' density of the PCM data stream is at its highest. When the level of the differential analog input is near zero, the PCM '0' and '1' densities are nearly equal. The fourth-order modulator shifts the quantization noise to a high frequency (out of the passband) where the digital filter can easily remove it. The modulator continuously chops the input, resulting in excellent offset and offset drift performance. It is important to note that offset or offset drift originating from the external circuitry is not removed by the modulator chopping. These errors can be effectively removed by using the external chopping feature of the ADS1258 (see the External Chopping section). Digital Filter rate—filter more for higher resolution, filter less for higher data rate. The filter is comprised of two sections, a fixed filter followed by a programmable filter. Figure 41 shows the block diagram of the filter. Data is supplied to the filter from the analog modulator at a rate of fCLK/2. The fixed filter is a fifth-order sinc filter with a decimation value of 64 that outputs data at a rate of fCLK/128. The second stage of the filter is a programmable averager (first-order sinc filter) with the number of averages set by the DRATE[1:0] bits. The data rate depends upon the system clock frequency (fCLK) and the converter configuration. The data rate can be computed by Equation 2 or Equation 3: Data Rate (Auto-Scan): f CLK 128(4 11b*DR ) 4.265625 ) TD) 2 CHOP Data Rate (Fixed-Channel Mode): f CLK 11b*DR 128(4 ) CHOP(4.265625 ) TD)) (2) 2 CHOP (3) Where: DR = DRATE[1:0] register bits (binary). CHOP = Chop register bit. TD = time delay value given in Table 7 from the DLY[2:0] register bits (128/fCLK periods). The programmable low-pass digital filter receives the modulator output and produces a high-resolution digital output. By adjusting the amount of filtering, tradeoffs can be made between resolution and data Modulator Rate = fCLK/2 Analog Modulator Data Rate = fCLK/128 sinc5 Filter Data Rate(1) = fCLK/(128 × Num_Ave) Programmable Averager Num_Ave NOTE: (1) Data rate for Fixed−Channel Mode, Chop = 0, Delay = 0. Figure 41. Block Diagram of Digital Filter 18 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com Table 5 shows a listing of the averaging and data rates for each of the four DRATE[1:0] register settings for the Auto-Scan and Fixed-Channel modes, with CHOP, DLY = 0. Note that the data rate scales directly with fCLK. For example, reducing fCLK by 2x reduces the maximum data rate by 2x. Figure 43 shows the response with averaging set to 4 (DRATE[1:0] = 10). 4-reading, post-averaging produces three equally-spaced notches between each main notch of the sinc5 filter. The frequency response of DRATE[1:0] = 01 and 00 follows a similar pattern, but with 15 and 63 equally-spaced notches between the main sinc5 notches, respectively. FREQUENCY RESPONSE sinc Ť ŤHAveragerǒf ǓŤ + ǒf Ǔ 5 ȧ sinǒ128p fǓ ȧ ȧ ȧ ȧ64 sinǒ2p fǓȧ ȧ ȧ f CLK f CLK ȧ sinǒ ȧ ȧNum_Ave ȧ Ǔȧ ȧ 128p fǓȧ ǒ sin ȧ −40 128p Num_Ave f f CLK Data Rate Fixed−Channel Mode (125kSPS) −60 −80 −100 CLK f Data Rate Auto−Scan Mode (23.739kSPS) −20 −120 (4) The digital filter attenuates noise on the modulator output including noise from within the ADS1258 and external noise present within the ADS1258 input signal. Adjusting the filtering by changing the number of averages used in the programmable filter changes the filter bandwidth. With a higher number of averages, the bandwidth is reduced and more noise is attenuated. The low-pass filter has notches (or zeros) at the data output rate and multiples thereof. The sinc5 part of the filter produces wide notches at fCLK/128 and multiples thereof. At these frequencies, the filter has zero gain. Figure 42 shows the response with no post averaging. Note that in Auto-Scan mode, the data rate is reduced while retaining the same frequency response as in Fixed-Channel mode. With programmable averaging, the wide notches produced by the sinc5 filter remain, but a number of narrow notches are superimposed in the response. The number of the superimposed notches is determined by the number of readings averaged (minus one). −140 0 125 250 375 500 625 Frequency (kHz) Figure 42. Frequency Response, DRATE[1:0] = 11 0 Data Rate Auto−Scan Mode (15.123kSPS) −20 −40 Gain (dB) Ť Hǒ f ǓŤ + Ť H 5 0 Gain (dB) The low-pass digital filter sets the overall frequency response for the ADS1258. The filter response is the product of the responses of the fixed and programmable filter sections and is given by Equation 4: Data Rate Fixed−Channel Mode (31.25kSPS) −60 −80 −100 −120 −140 0 125 250 375 500 625 Frequency (kHz) Figure 43. Frequency Response, DRATE[1:0] = 10 Table 5. Data Rates (1) (1) (2) (3) DRATE[1:0] Num_Ave (2) DATA RATE AUTO-SCAN MODE (SPS) (3) DATA RATE FIXED-CHANNEL MODE (SPS) –3dB BANDWIDTH (Hz) 11 1 23739 125000 25390 10 4 15123 31250 12402 01 16 6168 7813 3418 00 64 1831 1953 869 fCLK = 16MHz, Chop = 0, and Delay = 0. Num_Ave is the number of averages performed by the digital filter second stage. In Auto-Scan mode, the data rate listed is for a single channel; the effective data rate for multiple channels (on a per-channel basis) is the value shown in Figure 42 and Figure 43 divided by the number of active channels in a scan loop. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 19 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com ALIASING The digital filter low-pass characteristic repeats at multiples of the modulator rate of fCLK/2. Figure 44 shows the response plotted out to 16MHz at the data rate of 125kSPS (Fixed-Channel mode). Notice how the responses near DC, 8MHz, and 16MHz are the same. The digital filter will attenuate high-frequency noise on the ADS1258 inputs up to the frequency where the response repeats. However, noise or frequency components present on the analog input where the response repeats will alias into the passband. For most applications, an anti-alias filter is recommended to remove the noise. A simple first-order input filter with a pole at 200kHz provides –34dB rejection at the first image frequency. input. For most modes of operation, the analog input must be stable for one complete conversion cycle to provide settled data. In Fixed-Channel mode (DRATE[1:0] = 11), the input must be stable for five complete conversion cycles. Data Not Settled DRDY Settled Data 1 2 Step Input Figure 45. Asynchronous Step-Input Settling Time (DRATE[1:0] = 10, 01, 00) 0 DRATE[1:0] = 11 125kSPS Fixed−Channel Mode −20 Data Not Settled Settled Data Gain (dB) −40 DRDY −60 1 2 6 −80 Step Input −100 −120 Figure 46. Asynchronous Step-Input Settling Time (Fixed-Channel Mode, DRATE[1:0] = 11) −140 0 4 8 12 16 Frequency (MHz) NOISE PERFORMANCE Figure 44. Frequency Response Out to 16MHz Referring to Figure 42 and Figure 43, frequencies present on the analog input above the Nyquist rate (sample rate/2) are first attenuated by the digital filter and then will alias into the passband. SETTLING TIME The design of the ADS1258 provides fully-settled data when scanning through the input channels in Auto-Scan mode. The DRDY flag asserts low when the data for each channel is ready. It may be necessary to use the automatic switch time delay feature to provide time for settling of the external buffer and associated components after channel switching. When the converter is started (START pin transitions high or Start Command) with stable inputs, the first converter output is fully settled. When applying asynchronous step inputs, the settling time is somewhat different. The step-input settling time diagrams (Figure 45 and Figure 46) show the converter step response with an asynchronous step 20 The ADS1258 offers outstanding noise performance that can be optimized by adjusting the data rate. As the averaging is increased by reducing the data rate, noise drops correspondingly. See Table 6 for Input-Referred Noise, Noise-Free Resolution, and Effective Number of Bits (ENOB). The noise performance of low-level signals can be improved substantially by using external gain. Note that when Chop = 1, the data rate is reduced by 2x and the noise is reduced by 1.4x. ENOB is defined in Equation 5: lnǒFSRńRMS NoiseǓ ENOB + ln(2) (5) where FSR is the full-scale range. The data for the Noise-Free Resolution (bits) is calculated in the same way as ENOB, except peak-to-peak noise is used. As seen in the illustration of Noise vs VREF (Figure 9), the converter noise is relatively constant versus the reference voltage. Optimum signal-to-noise ratio of the converter is achieved by using higher reference voltages (VREF MAX = AVDD – AVSS). Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com Table 6. Noise Performance (1) (1) DRATE[1:0] DATA RATE AUTO-SCAN MODE (SPS) DATA RATE FIXED-CHANNEL MODE (SPS) INPUT-REFERRED NOISE (µVRMS) NOISE-FREE RESOLUTION (Bits) EFFECTIVE NUMBER OF BITS (ENOB) 11 23739 10 15123 125000 12 16.8 19.5 31250 7.9 17.4 20.1 01 00 6168 7813 4.5 18.2 20.9 1831 1953 2.8 18.9 21.6 VREF = 4.096V, fCLK = 16MHz, Chop = 0, Delay = 0, Inputs shorted, and 2048 sample size. Table 7. Effective Data Rates with Switch-Time Delay (Auto-Scan Mode) (1) DLY[2:0] TIME DELAY (128/fCLK periods) TIME DELAY (μS) DRATE[1:0] = 11 DRATE[1:0] = 10 DRATE[1:0] = 01 DRATE[1:0] = 00 000 0 0 23739 15123 6168 1831 001 1 8 19950 13491 5878 1805 010 2 16 17204 12177 5614 1779 011 4 32 13491 10191 5151 1730 100 8 64 9423 7685 4422 1639 101 16 128 5878 5151 3447 1483 110 32 256 3354 3104 2392 1247 111 48 384 2347 2222 1831 1075 (1) Time delay and data rates scale with fCLK. If Chop = 1, the data rates are half those shown. fCLK = 16MHz, Auto-Scan Mode. EXTERNAL MULTIPLEXER LOOP The external multiplexer loop consists of two differential multiplexer output pins and two differential ADC input pins. The user may use external components (buffering/filtering, single-ended to differential conversion, etc.), forming a signal conditioning loop. For best performance, the ADC input should be buffered and driven differentially. To bypass the external multiplexer loop, connect the ADC input pins directly to the multiplexer output pins, or select internal bypass connection (BYPASS = 0 of CONFIG0). Note that the multiplexer output pins are active regardless of the bypass setting. Use of the switch time delay register reduces the effective channel data rate. Table 7 shows the actual data rates derived from Equation 2, when using the switch time delay feature. When pulse converting, where one channel is converted with each START pin pulse or each pulse command, the application software may provide the required time delay between pulses. However, with Chop = 1, the switch time delay feature may still be necessary to allow for settling. In estimating the time delay that may be required, Table 8 lists the time delay-to-time constant ratio (t/τ) and the corresponding final settled data in % and number of bits. SWITCH TIME DELAY Table 8. Settling Time When using the ADS1258 in the Auto-Scan mode, where the converter automatically switches from one channel to the next, the settling time of the external signal conditioning circuit becomes important. If the channel does not fully settle after the multiplexer channel is switched, the data may not be correct. The ADS1258 provides a switch time delay feature which automatically provides a delay after channel switching to allow the channel to settle before taking a reading. The amount of time delay required depends primarily on the settling time of the external signal conditioning. Additional consideration may be needed to account for the settling of the input source arising from the transient generated from channel switching. t/τ (1) FINAL SETTLING (%) FINAL SETTLING (Bits) 1 63 2 3 95 5 5 99.3 7 7 99.9 10 10 99.995 14 15 99.9999 20 17 99.999994 24 (1) Multiple time constants (τ1 2 + τ2 2+…)½. can be approximated Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 by: 21 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com SENSOR BIAS An integrated current source provides a means to bias an external sensor (for example, a diode junction); or, it verifies the integrity of a sensor or sensor connection. When the sensor fails to an open condition, the current sources drive the inputs of the converter to positive full-scale. The biasing is in the form of differential currents (programmable 1.5μA or 24μA), connected to the output of the multiplexer. Figure 47 shows a simplified diagram of ADS1258 input structure with the external sensor modeled as a resistance RS between two input pins. The two 80Ω series resistors, RMUX, model the ADS1258 internal resistances. RL represents the effective input resistance of the ADC input or external buffer. When the sensor bias is enabled, they source ISDC to one selected input pin (connected to the MUXOUTP channel) and sink ISDC from the other selected input pin (connected to the MUXOUTN channel). The signal measured with the biasing enabled equals the total IR drop: ISDC[(2RMUX + RS) ׀׀RL]. Note that when the sensor is a direct short (that is, RS = 0), there will still be a small signal measured by the ADS1258 when the biasing is enabled: ISDC[2RMUX ׀׀RL]. AVDD I SDC 80Ω MUXOUTP RS ADCINP RL 80Ω MUXOUTN ADCINN The time to charge the external capacitance is given in Equation 6: dV + I SDC C dt (6) It is also important to note that the low impedance (65kΩ) of the direct ADC inputs or the impedance of the external signal conditioning loads the current sources. This low impedance limits the ability of the current source to pull the inputs to positive full-scale for open-channel detection. OPEN-SENSOR DETECTION For open-sensor detection, set the biasing to either 1.5μA or 24μA. Then select the channel and read the output code. When a sensor opens, the positive input is pulled to AVDD and the negative input is pulled to AVSS. Because of this configuration, the output code trends toward positive full-scale. Note that the interaction of the multiplexer resistance with the current source may lead to degradation in converter linearity. It is recommended to enable the current source only periodically to check for open inputs and discard the associated data. EXTERNAL DIODE BIASING The current source can be used to bias external diodes for temperature sensing. Scan the appropriate channels with the current source set to 24µA. Re-scan the same channels with the current source set to 1.5µA. The difference in diode voltage readings resulting from the two bias currents is directly proportional to temperature. I SDC AVSS Figure 47. Sensor Bias Structure 22 The current source is connected to the output of the multiplexer. For unselected channels, the current source is not connected. This configuration means that when a new channel is selected, the current source charges stray sensor capacitance, which may slow the rise of the sensor voltage. The automatic switch time delay feature can be used to apply an appropriate time delay before a conversion is started to provide fully settled data (see the Switch Time Delay section). Note that errors in current ratio, diode and cable resistance, or the non-ideality factor of the diode can lead to errors in temperature readings. These effects can be compensated by characterization or by calibrating the diode at known temperatures. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com EXTERNAL CHOPPING GPIO DIGITAL PORT (GPIOx) The modulator of the ADS1258 incorporates a chopping front-end which removes offset errors, providing excellent offset and offset drift performance. However, offset and offset drift originating from external signal conditioning are not removed by the modulator. The ADS1258 has an additional chopping feature that removes external offset errors (CHOP = 1). The ADS1258 has eight dedicated pins for General-Purpose Digital I/O (GPIO). The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC (GPIO-Configure) register. The GPIOD (GPIO-Data) register controls the level of the pins. When reading the GPIOD register, the data returned is the level of the pins, whether they are programmed as inputs or outputs. As inputs, a write to the GPIOD has no effect. As outputs, a write to the GPIOD sets the output value. With external chopping enabled, the converter takes two readings in succession on the same channel. The first reading is taken with one polarity and the second reading is taken with the opposite polarity. The converter averages the two readings, canceling the offset, as shown in Figure 48. With chopping enabled, the effective reading is reduced to half of the nominal reading rate. Multiplexer (chopping) During Standby and Power-Down modes, the GPIO remains active. If configured as inputs, they must be driven (do not float). If configured as outputs, they continue to drive the pins. The GPIO pins are set as inputs after power-on or after a reset. Figure 49 shows the GPIO port structure. GPIO Data (read) MUXOUTP AINn ADCINP Optional Signal Conditioning GPIO Pin ADC GPIO Data (write) AINn MUXOUTN ADCINN GPIO Control Figure 48. External Chopping Note that since the inputs are reversed under control of the ADS1258, a delay time may be necessary to provide time for external signal conditioning to fully settle before the second phase of the reading sequence starts (see the Switch Time Delay section). External chopping can be used to significantly reduce total offset errors (to less than 10μV) and offset drift over temperature (to less than 0.2μV/°C). Note that chopping must be disabled (CHOP = 0) to take the internal monitor readings. Figure 49. GPIO Port Pin POWER-DOWN INPUT (PWDN) The PWDN pin is used to control the power-down mode of the converter. In power-down mode, all internal circuitry is deactivated including the oscillator and the clock output. Hold PWDN low for at least two fCLK cycles to engage power-down. The register settings are retained during power-down. When the pin is returned high, the converter requires a wake-up time before readings can be taken, as shown in the Power-Up Timing section. Note that in power-down mode, the inputs of the ADS1258 must still be driven and the device continues to drive the outputs. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 23 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com Table 9. Wake-Up Times POWER-UP TIMING When powering up the device or taking the PWDN pin high to wake the device, a wake-up time is required before readings can be taken. When using the internal oscillator, the wake-up time is composed of the oscillator start-up time and the PLL lock time, and if the supplies are also being powered, there is a reset interval time of 218 fCLK cycles. Note that CLKIO is not valid during the wake-up period, as shown in Figure 50. tWAKE INTERNAL OSCILLATOR(1) CONDITION tWAKE EXTERNAL CLOCK PWDN or CLKSEL tOSC 2/fCLK AVDD – AVSS tOSC + 218/fCLK 218/fCLK (1) Wake-up times for the internal oscillator operation are typical and may vary depending on crystal characteristics and layout capacitance. The user should verify the oscillator start-up times (tOSC = oscillator start-up time). POWER-UP SEQUENCE CLKIO t WAKE The analog and digital supplies should be applied before any analog or digital input is driven. The power supplies may be sequenced in any order. The internal master reset signal is generated from the analog power supply (AVDD – AVSS), when the level reaches approximately 3.2V. The power-up master reset signal is functionally the same as the Reset Command and the RESET input pin. PWDN or CLKSEL or Reset Input (RESET) AVDD − AVSS(1) Device Ready 3.2V, typical NOTE: (1) Shown with DVDD stable. Figure 50. Device Wake Time with Internal Oscillator When using the device with an external clock, the wake-up time is 2/fCLK periods when waking up with the PWDN pin and 218/fCLK periods when powering the supplies, all after a valid CLKIO is applied, as shown in Figure 51. When RESET is held low for at least two fCLK cycles, all registers are reset to their default values and the digital filter is cleared. When RESET is released high, the device is ready to convert data. Clock Select Input (CLKSEL) This pin selects the source of the system clock: the crystal oscillator or an external clock. Tie CLKSEL low to select the crystal oscillator. When using an external clock (applied to the CLKIO pin), tie CLKSEL high. Clock Input/Output (CLKIO) This pin serves either as a clock output or clock input, depending on the state of the CLKSEL pin. When using an external clock, apply the clock to this pin and set the CLKSEL pin high. When using the internal oscillator, this pin has the option of providing a clock output. The CLKENB bit of register CONFIG0 enables the clock output (default is enabled). tWAKE CLKIO PWDN, CLKSEL or AVDD − Start Input (START) AVSS(1) 3.2V, typical Device Ready NOTE: (1) Shown with DVDD stable. Figure 51. Device Wake Time with External Clock Table 9 summarizes the wake-up times using the internal oscillator and the external clock operations. 24 The START pin is an input that controls the ADC process. When the START pin is taken high, the converter starts converting the selected input channels. When the START pin is taken low, the conversion in progress runs to completion and the converter is stopped. The device then enters one of the two idle modes (see the Idle Modes section for more details). See the Conversion Control section for details of using the START pin. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com Data Ready Output (DRDY) The DRDY pin is an output that asserts low to indicate when new channel data is available to read (the previous conversion data is lost). DRDY returns high after the first falling edge of SCLK during a data read operation. If the data is not read (no SCLK pulses), DRDY remains low until new channel data is available once again. DRDY then pulses high, then low to indicate new data is available; see Figure 52. DRDY is usually connected to an interrupt of a controller, DSP, or connected to a controller port pin for polling in a software loop. Channel data can be read without the use of DRDY. Read the data using the register format read and check the Status Byte when the NEW bit = 1, which indicates new channel data. Output Data Scaling and Over-Range The ADS1258 is scaled such that the output data code resulting from an input voltage equal to ±VREF has a margin of 6.6% before clipping. This architecture allows operation of applied input signals at or near full-scale without overloading the converter. DRDY SCLK Specifically, the device is calibrated so that: DRDY with SCLK 1LSB = VREF/780000h, t DRDYPLS and the output clips when: DRDY |VIN| ≥ 1.06 × VREF. SCLK Table 10 summarizes the ideal output codes versus input signals. DRDY without SCLK tDRDYPLS = 1 fCLK Figure 52. DRDY Timing (See Figure 2 for the DRDY Pulse) Table 10. Ideal Output Code vs Input Signal INPUT SIGNAL VIN (ADCINP – ADCINN) IDEAL OUTPUT CODE (1) ≥ +1.06 VREF 7FFFFFh Maximum Positive Full-Scale Before Output Clipping +VREF 780000h VIN = +VREF +1.06 VREF/(223 – 1) 000001h +1LSB 0 000000h Bipolar Zero –1.06 VREF/(223 – 1) FFFFFFh –1LSB –VREF 87FFFFh VIN = –VREF 800000h Maximum Negative Full-Scale Before Output Clipping 23 23 ≤ –1.06 VREF × (2 /2 (1) DESCRIPTION – 1) Excludes effects of noise, linearity, offset, and gain errors. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 25 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com INTERNAL SYSTEM READINGS Analog Power-Supply Reading (VCC) The analog power-supply voltage of the ADS1258 can be monitored by reading the VCC register. The supply voltage is routed internal to the ADS1258 and is measured and scaled using an internal reference. The supply readback channel outputs the difference between AVDD and AVSS (AVDD – AVSS), for both single and dual configurations. Note that it is required to disable chopping (CHOP = 0) prior to taking this reading. The scale factor of Equation 7 converts the code value to volts: Total Analog Supply Voltage (V) + Code 786432 (7) When the power supply falls below the minimum specified operating voltage, the full operation of the ADS1258 cannot be ensured. Note that when the total analog supply voltage falls to below approximately 4.3V the returned data is set to zero. The SUPPLY bit in the status byte is then set. The bit is cleared when the total supply voltage rises approximately 50mV higher than the lower trip point. The digital supply (DVDD) may be monitored by looping-back the supply voltage to an input channel. A resistor divider may be required for bipolar supply operation to reduce the DVDD level to within the range of the analog supply. Gain Reading (GAIN) In this configuration, the external reference is connected both to the analog input and to the reference input of the ADC. The data from this register indicates the gain of the device. The following scale factor (Equation 8) converts the code value to device gain: Device Gain ǒVńVǓ + Code 7864320 (8) To correct the device gain error, the user software can divide each converter data value by the device gain. Note that this corrects only for gain errors originating within the ADC; system gain errors because of an external gain stage error or because of reference errors are not compensated. Note that it is required to disable chopping (CHOP = 0) also prior to taking this reading. Reference Reading (REF) In this configuration, the external reference is connected to the analog input and an internal reference is connected to the reference of the ADC. The data from this register indicates the magnitude of the external reference voltage. 26 The scale factor of Equation 9 converts the code value to external reference voltage: External Reference (V) + Code 786432 (9) This readback function can be used to check for missing or an out-of-range reference. If the reference input pins are floating (not connected), internal biasing pulls them to the AVSS supply. This causes the output code to tend toward '0'. Bypass capacitors connected to the external reference pins may slow the response of the pins when open. When reading this register immediately after power-on, verify that the reference has settled to ensure an accurate reading. Note that it is required to disable chopping (CHOP = 0) prior to taking this reading. Temperature Reading (TEMP) The ADS1258 contains an on-chip temperature sensor. This sensor uses two internal diodes with one diode having a current density of 16x of the other. The difference in current densities of the diodes yields a difference voltage that is proportional to absolute temperature. As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device temperature tracks the PCB temperature closely. Note also that self-heating of the ADS1258 causes a higher reading than the temperature of the surrounding PCB. Note that it is required to disable chopping (CHOP = 0) prior to taking this reading. The scale factor of Equation 10 converts the temperature reading to °C. Before using the equation, the temperature reading code must first be scaled to μV. Temperature(°C) = Temp Reading(mV) - 168,000mV + 25°C Temp Sensor Coefficient (10) Where Temp Sensor Coefficient = 563µV/°C (if the ADS1258 and test PCB temperatures are forced together), or 394µV/°C (if only the ADS1258 temperature is forced and the test PCB is in free-air). Offset Reading (OFFSET) The differential output of the multiplexer is shorted together and set to a common-mode voltage of (AVDD – AVSS)/2. Ideally, the code from this register function is 0h, but varies because of the noise of the ADC and offsets stemming from the ADC and external signal conditioning. This register can be used to calibrate or track the offset of the ADS1258 and external signal conditioning. The chop feature of the ADC can automatically remove offset and offset drift from the external signal conditioning; see the External Chopping section. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com CONVERSION CONTROL Pulse Convert Command The conversions of the ADS1258 are controlled by the START pin. Conversions begin when the START pin is taken high and conversions are stopped when the START pin is taken low. For continuous conversions, tie the START pin high. The START pin can also be tied low and the conversions controlled by the PULSE convert command. The PULSE convert command converts one channel (only) for each command sent. In this way, channel conversions can be stepped without the need to toggle the START pin. Figure 54 also shows the start of conversions with the rising edge of the START pin. If the START pin is taken high, and then low prior to completion of the conversion cycle (8 τCLK before DRDY asserts low), only the current channel is converted and the device enters the standby or sleep modes waiting for a new start condition. Figure 55 shows the START pin to DRDY timing. The same function of conversion control is possible using the Pulse Convert command (with the START pin low). In this operation, the data from one channel is converted with each Pulse Convert command. The Pulse convert command takes effect when the command byte is completely shifted in (eighth falling edge of SCLK). After conversion, if more than one channel is enabled (Auto-Scan mode), the converter indexes to the next selected channel after completing the conversion. START Pin As shown in Figure 53, when the START pin is taken high, conversions start beginning with the current channel. The device continues to convert all of the programmed channels, in a continuous loop, until the START pin is taken low. When this occurs, the conversion in process completes, and the device enters the standby or sleep mode waiting for a new start condition. When DRDY asserts low, the conversion data is ready. Figure 55 shows the START pin to DRDY timing. The order in which channel data is converted is described in Table 12. When the last selected channel in the program list has been converted, the device continues conversions starting with the highest priority channel. If there is only one channel selected in the Auto-Scan mode, the converter remains fixed on one channel. A write operation to any register sets the channel pointer to the highest priority channel (see Table 13). In Fixed-Channel mode, the channel pointer remains fixed. Data Ready, Index to Next Channel Converting Idle Converting DRDY START Pin or Pulse Convert Command Figure 54. Pulse Conversion, Auto-Scan Mode DRDY tSDSU tDRHD Data Ready, Index to Next Channel Idle Mode Converting Idle DRDY START Pin SYMBOL MIN UNIT tSDSU START to DRDY Setup Time to Halt Further Conversions 8 tCLK tDRHD DRDY to START Hold Time to Complete Current Conversion 8 tCLK START Pin Figure 53. Conversion Control, Auto-Scan Mode DESCRIPTION Figure 55. START Pin and DRDY Timing Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 27 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com GPIO Linked START Pin Control OPERATING MODES The START pin can be contolled directly by software by connecting externally a GPIO port pin to the START pin. (Note that an external pull-down resistor is recommended to keep the GPIO from floating until the GPIO is configured as an output). For this mode of control, the START pin is effectively controlled by writing to the GPIO Data Register (GPIOD), with the write operation setting or resetting the appropriate bit. The data takes effect on the eighth falling edge of the data byte write. The START pin can then be controlled by the serial interface. The operating modes of the ADS1258 are defined in three basic states: Converting Mode, Idle Mode, and Power-Down mode. In Converting mode, the device is actively converting channel data. The device power dissipation is the highest in this mode. This mode is divided into two sub-modes: Auto-Scan and Fixed-Channel. Initial Delay As seen in Figure 56, when a start convert condition occurs, the first reading from ADS1258 is delayed for a number of clock cycles. This delay allows fully settled data to occur at the first data read. Data reads thereafter are available at the full data rate. The number of clock cycles delayed before the first reading is valid depends on the data rate setting, and whether exiting the Standby or Sleep Mode. Table 11 lists the delayed clock cycles versus data rate. Fully−Settled Data DRDY The next mode is the Idle mode. In this mode, the device is not converting channel data. The device remains active, waiting for input to start conversions. The power consumption is reduced from that of the Converting mode. This mode also has two sub-modes: Standby and Sleep. The last mode is Power-Down mode. In this mode, all functions of the converter are disabled to reduce power consumption to a minimum. CONVERTING MODES The ADS1258 has two converting modes: Auto-Scan and Fixed-Channel. In Auto-Scan mode, the channels to be measured are pre-selected in the address register settings. When a convert condition is present, the converter automatically measures and sequences through the channels either in a continuous loop or pulse-step fashion, depending on the trigger condition. In Fixed-Channel mode, the channel address is selected in the address register settings prior to acquiring channel data. When a convert condition is present, the device converts a single channel, either continuously or in pulse-step fashion, depending on the trigger condition. The data rate in this mode is higher than in Auto-Scan Mode since the input channels are not indexed for each reading. Initial Delay Start Condition Figure 56. Start Condition to First Data The selection of converting modes is set with bit MUXMOD of register CONFIG0. Table 11. Start Condition to DRDY Delay, Chop = 0, DLY[2:0] = 000 INITIAL DELAY (Standby Mode) (fCLK cycles) DRATE[1:0] 28 Fixed-Channel Auto-Scan INITIAL DELAY (Sleep Mode) (fCLK cycles) Fixed-Channel Auto-Scan 11 802 708 866 772 10 1186 1092 1250 1156 01 2722 2628 2786 2692 00 8866 8772 8930 8836 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com Auto-Scan Mode The ADS1258 provides 16 analog inputs, which can be configured in combinations of eight differential inputs or 16 single-ended inputs, and provides an additional five internal system measurements. Taken together, the device allows a total of 29 possible channel combinations. The converter automatically scans and measures the selected channels, either in a continuous loop or pulse-step fashion, under the control of the START pin or Start command software. The channels are selected for measurement in registers MUXDIF, MUXSG0, MUXSG1, and SYSRED. A write command to any register resets the internal channel pointer to the highest priority channel (see Table 13). DRDY asserts low when the channel data is ready; see Figure 54 and Figure 53. At the same time, the converter indexes to the next selected channel and, if the START pin is high, starts a new channel conversion. Otherwise, if pulse converting, the device enters the Idle mode. For example, if channels 3, 4, 7, and 8 are selected for measurement in the list, the ADS1258 converts the channels in that order, skipping all other channels. After channel 8 is converted, the device starts over, beginning at the top of the channel list, channel 3. The following guidelines can be used when selecting input channels for Auto-Scan measurement: 1. For differential measurements, adjacent input pins (AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, etc.) are pre-set as differential pairs. Even number channels from each pair represent the positive input to the ADC and odd number channels within a pair represent the negative input (for example, AIN0/AIN1: AIN0 is the positive channel, AIN1 is the negative channel.) 2. For single-ended measurements use AIN0 through AIN15 as single-ended inputs and AINCOM is the shared common input among them. Note: AINCOM does not need to be at ground potential. For example, AINCOM can be tied to VREFP or VREFN; or any potential between (AVSS – 100mV) and (AVDD + 100mV). 3. Combinations of differential, single-ended inputs, and internal system registers can be used in a scan. Fixed-Channel Mode In this mode, any of the 16 analog input channels (AIN0–AIN15) can be selected for the positive ADC input and any analog input channels can be selected for the negative ADC input. New channel configurations must be selected by the MUXSCH register prior to converting a different channel. Note that the AINCOM input and the internal system registers cannot be referenced in this mode. Idle Modes When the START pin is taken low, the device completes the conversion of the current channel and then enters one of the Idle modes, Standby or Sleep. In the Standby mode, the internal biasing of the converter is reduced. This state provides the fastest wake-up response when re-entering the run state. In Sleep mode, the internal biasing is reduced further to provide lower power consumption than the Standby mode. This mode has a slower wake-up response when re-entering the Converting mode (see Table 11). Selection of these modes is set under bit IDLMOD of register CONFIG1. POWER-DOWN MODE In power-down mode, both the analog and digital circuitry are completely disabled. SERIAL INTERFACE The ADS1258 is operated via an SPI-compatible serial interface by writing data to the configuration registers, using commands to control the converter and finally reading back the channel data. The interface consists of four signals: CS, SCLK, DIN, and DOUT. Chip Select (CS) CS is an input that is used to select the device for serial communication. CS is active low. When CS is high, read or write commands in progress are aborted and the serial interface is reset. Additionally, DOUT tri-states and inputs on DIN are ignored. DRDY indicates when data is ready, independent of CS. The converter may be operated using CS to actively select and deselect the device, or with CS tied low (always selected). CS must stay low for the entire read or write operation. When operating with CS tied low, the number of SCLK pulses must be carefully controlled to avoid false command transmission. Serial Clock (SCLK) Operation The serial clock (SCLK) is an input which is used to clock data into (DIN) and out of (DOUT) the ADS1258. This input is a Schmitt-trigger input that has a high degree of noise immunity. However, it is recommended to keep SCLK as clean as possible to prevent glitches from inadvertently shifting the data. Data is shifted into DIN on the rising edge of SCLK and data is shifted out of DOUT on the falling edge of SCLK. If SCLK is held inactive for 4096 or 256 fCLK cycles (SPIRST bit of register CONFIG0), read or Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 29 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com write operations in progress will terminate and the SPI interface resets. This timeout feature can be used to recover lost communication when a serial interface transmission is interrupted or inadvertently glitched. may be read at any time without concern to DRDY. The NEW bit of the STATUS byte indicates that the data register has been refreshed with new converter data since the last read operation. The data is shifted out MSB first after the STATUS byte. Data Input (DIN) and Data Output (DOUT) Operation It should be noted that on system power-up, if the ADS1258 interface signals are floating or undefined, the interface could wake in an unknown state. This condition is remedied by resetting the interface in three ways: toggle the RESET pin low then high; toggle the CS pin high then low; or hold SCLK inactive for 218 + 4096 fCLK cycles. The data input pin (DIN) is used to input data to the ADS1258. The data output pin (DOUT) is used to output data from the ADS1258. Data on DIN is shifted into the converter on the rising edge of SCLK while data is shifted out on DOUT on the falling edge of SCLK. DOUT is tri-stated when CS is high to allow multiple devices to share the line. Channel Data Read Direct Channel data can be accessed from the ADS1258 in two ways: Direct data read or data read with register format. With Direct read, the DIN input pin is held inactive (high or low) for at least the first three SCLK transitions. When the first three bits are 000 or 111, the device detects a direct data read and continues to output conversion data. After the device defects this read format, commands are ignored until either CS is toggled, an SPI timeout occurs or the device is reset. The Channel Data Read command does not have this requirement. SPI Bus Sharing The ADS1258 can be connected to a shared SPI bus. DOUT tri-states when CS is deselected (high). When the ADS1258 is connected to a shared bus, data can be read only by the Channel Data Read command format. COMMUNICATION PROTOCOL Communicating to the ADS1258 involves shifting data into the device (via the DIN pin) or shifting data out of the device (via the DOUT pin) under control of the SCLK input. Concurrent with the first SCLK transition, channel data is output on the DOUT output pin. A total of 24 or 32 SCLK transitions complete the data read operation. The number of shifts depend on whether the status byte is enabled. The data must be completely shifted out before the next occurrence of DRDY or the remaining data will be corrupted. It is recommended to monitor DRDY to synchronize the start of the read operation to avoid data corruption. Before DRDY asserts low, the MSB of the Status byte or the MSB of the data is output on DOUT (CS = '0'), as shown in Figure 57. In this format, reading the data a second time within the same DRDY frame returns data = 0. Reading DATA DRDY goes low to indicate that data for one channel are ready. The channel data may be read via a direct data read (Channel Data Read Direct) or the data may be read in a register format (Channel Data Read Register). A direct data read requires the data to be read before the next occurrence of DRDY or the data for that channel are overwritten with new data from the next channel. This type of data read requires synchronization with DRDY to avoid this conflict. When reading data in the register format, the data DRDY CS (3) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCLK Status Byte(1) DOUT Data Byte 1 (MSB) Data Byte 3 (MSB) DIN (hold inactive) (2) NOTES: (1) Optional for Auto-Scan mode, disabled for Fixed-Channel mode. See Table 13, Status Byte. (2) After the channel data read operation, CS must be toggled or an SPI timeout must occur before sending commands. (3) No SCLK activity. Figure 57. Channel Data Read Direct (No Command) 30 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com COMMAND DESCRIPTION SCLK falling edge (command byte completed), the MSB of the channel data is restarted on DOUT. The user clocks the data on the following rising edge of SCLK. A total of 40 SCLK transitions complete the data read operation. Unlike the direct read mode, the channel data can be read during a DRDY transition without data corruption. This mode is recommended when DRDY is not used and the data is polled to detect for the occurrence of new data or when CS is tied low to avoid the necessity for an SPI timeout that otherwise occurs when reading data directly. This option avoids conflicts with DRDY, as shown in Figure 58. Commands may be sent to the ADS1258 with CS tied low. However, after the Channel Data Read Direct operation, it is necessary to toggle CS or an SPI timeout must occur to reset the interface before sending a command. Channel Data Read Command To read channel data in this mode (register format), the first three bits of the command byte to be shifted into the device are 001. The MUL bit must be set because this command is a multiple byte read. The remaining bits are don’t care but still must be clocked to the device. During this time, ignore any data that appear on DOUT until the command completes. This data should be ignored. Beginning with the eighth CS 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCLK DIN DOUT Command Byte 1 Don’t Care Don’t Care(1) Don’t Care Data(2) Data(2) NOTE: (1) After the prescribed number of registers are read, then one or more additional commands can be issued in succession. (2) Four bytes for channel data register read. See Table 13, Status Byte. One or more bytes for register data read, depending on MUL bit. Figure 58. Register and Channel Data (Register Format) Read Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 31 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com Register Read Command Beginning with the eighth SCLK rising edge (command byte completed), the MSB of the data is shifted in. The remaining seven SCLK rising edges complete the write to a single register. If MUL = '1', the data to the next register can be written by supplying additional SCLKs. The operation terminates when the last register is accessed (address = 09h), as shown in Figure 59. To read register data, the first three bits of the command byte to be shifted into the device are 010. These bits are followed by the multiple register read bit (MUL). If MUL = '1', then multiple registers can be read in sequence beyond the desired register. If MUL = '0', only data from the addressed register can be read. The last four bits of the command word are the beginning register address bits. During this time, the invalid data may appear on DOUT until the command is completed. This data should be ignored. Beginning with the eighth falling edge of SCLK (command byte completed), the MSB of the register data is output on DOUT. The remaining eight SCLK transitions complete the read of a single register. If MUL = '1', the data from the next register can be read in sequence by supplying additional SCLKs. The operation terminates when the last register is accessed (address = 09h); see Figure 58. CONTROL COMMANDS Pulse Convert Command (See Conversion Control section) Reset Command The Reset command resets the ADC. All registers are reset to their default values. A conversion in process will continue but will be invalid when completed (DRDY low). This conversion data should be discarded. Note that the SPI interface may require reset for this command, or any command, to function. To ensure device reset under a possible locked SPI interface condition, do one of the following: 1) toggle CS high then low and send the reset command; or 2) hold SCLK inactive for 256/fCLK or 4096/fCLK and send the reset command. The control commands are illustrated in Figure 60. Register Write Command To write register data, the first three bits of the command byte to be shifted into the device are 011. These bits are followed by the multiple register read bit (MUL). If MUL = '1', then multiple registers can be written in sequence beyond the desired register. If MUL = '0', only data to the addressed register can be written. The remaining four bits of the command word are the beginning register address bits. During this time, the invalid data may appear on DOUT until the command is completed. This data should be ignored. CS 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCLK DIN Command Byte Register Data(1) Register Data(1)(2) NOTE: (1) One or more bytes depending on MUL bit. (2) After the prescribed number of registers are read, then one or more additional commands can be issued in succession. Figure 59. Register Write Operation CS 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SCLK DIN Command 1 Command 2(1) Command 3(1) NOTE: (1) One or more commands can be issued in succession. Figure 60. Control Command Operation 32 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com CHANNEL DATA The data read operation outputs either four bytes (one byte for status and three bytes for data), or three bytes for data only. The selection of 4-byte or 3-byte data read is set by the bit STAT in register CONFIG0 (see Table 17, Status Byte, for options). In the 4-byte read, the first byte is the status byte and the following three bytes are the data bytes. The MSB (Data23) of the data is shifted out first. Table 12. CHANNEL DATA FORMAT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1 BYTE STATUS NEW OVF SUPPLY CHID4 CHID3 CHID2 CHID1 CHID0 2 MSB Data23 Data22 Data21 Data20 Data19 Data18 Data17 Data16 3 MSB-1 Data15 Data14 Data13 Data12 Data11 Data10 Data9 Data8 4 LSB Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data0 STATUS BYTE BIT STATUS.7, NEW The NEW bit is set when the results of a Channel Data Read Command returns new channel data. The bit remains set indefinitely until the channel data is read. When the channel data is read again before the converter updates with new data, the previous data is output and the NEW bit is cleared. If the channel data is not read before the next conversion update, the data from the previous conversion is lost. As shown in Figure 61, the NEW bit emulates the operation of the DRDY output pin. To emulate the function of the DRDY output pin in software, the user reads data at a rate faster than the converter's data rate. The user then polls the NEW bit to detect for new channel data. 0 = Channel data has not been updated since the last read operation. 1 = Channel data has been updated since the last read operation. DRDY NEW Bit Data Reads (register format) Figure 61. NEW Bit Operation BIT STATUS.6 OVF When this bit is set, this indicates the differential voltage applied to the ADC inputs have exceeded the range of the converter |VIN| > 1.06VREF. During over-range, the output code of the converter clips to either positive FS (VIN ≥ 1.06 × VREF) or negative FS (VIN ≤ –1.06 × VREF). This bit, with the MSB of the data, can be used to detect positive or negative over-range conditions. Note that because of averaging incorporated within the digital filter, the absence of this bit does not assure that the modulator of the ADC has not saturated due to possible transient input overload conditions. BIT STATUS.5 SUPPLY This bit indicates that the analog power-supply voltage (AVDD – AVSS) is below a preset limit. The SUPPLY bit is set when the value falls below 4.3V (typically) and is reset when the value rises 50mV higher (typically) than the lower trip point. The output data of the ADC may not be valid under low power-supply conditions. BITS CHID[4:0] CHANNEL ID BITS The Channel ID bits indicate the measurement channel of the acquired data. Note that for Fixed-Channel mode, the Channel ID bits are undefined. See Table 13 for the channel ID, the measurement priority, and the channel description for Auto-Scan Mode. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 33 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com BITS DATA[23:0] OF DATA BYTES The ADC output data are 24 bits wide (DATA[23:0]). DATA23 is the most significant bit (MSB) and DATA0 is the least significant bit (LSB). The data is coded in binary twos complement format. Table 13. Channel ID and Measurement Order (Auto-Scan Mode) 34 BITS CHID[4:0] PRIORITY CHANNEL DESCRIPTION 00h 1 (Highest) DIFF0 (AIN0–AIN1) Differential 0 01h 2 DIFF1 (AIN2–AIN3) Differential 1 02h 3 DIFF2 (AIN4–AIN5) Differential 2 03h 4 DIFF3 (AIN6–AIN7) Differential 3 04h 5 DIFF4 (AIN8– AIN9) Differential 4 05h 6 DIFF5 (AIN10–AIN11) Differential 5 06h 7 DIFF6 (AIN12–AIN13) Differential 6 07h 8 DIFF7 (AIN14–AIN15) Differential 7 08h 9 AIN0 Single-Ended 0 09h 10 AIN1 Single-Ended 1 0Ah 11 AIN2 Single-Ended 2 0Bh 12 AIN3 Single-Ended 3 0Ch 13 AIN4 Single-Ended 4 0Dh 14 AIN5 Single-Ended 5 0Eh 15 AIN6 Single-Ended 6 0Fh 16 AIN7 Single-Ended 7 10h 17 AIN8 Single-Ended 8 11h 18 AIN9 Single-Ended 9 12h 19 AIN10 Single-Ended 10 13h 20 AIN11 Single-Ended 11 14h 21 AIN12 Single-Ended 12 15h 22 AIN13 Single-Ended 13 16h 23 AIN14 Single-Ended 14 17h 24 AIN15 Single-Ended 15 18h 25 OFFSET OFFSET 1Ah 26 VCC AVDD – AVSS Supplies Temperature 1Bh 27 TEMP 1Ch 28 GAIN Gain 1Dh 29 (Lowest) REF External Reference Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com COMMAND AND REGISTER DEFINITIONS Commands are used to read channel data, access the configuration registers, and control the conversion process. If the command is a register read or write operation, one or more data bytes follow the command byte. If bit MUL = 1 in the command byte, then multiple registers can be read or written in one command operation (see the MUL bit). Commands can be sent back-to-back without toggling CS; however, after a channel Data Read Direct operation, CS must be toggled or an SPI timeout must occur before sending a command. The data read by command does not require CS to be toggled. The command byte consists of three fields: the Command Bits(C[2:0]), multiple register access bit (MUL), and the Register Address Bits (A[3:0]); see the Command Byte register. Table 14. Command Byte 7 6 5 4 3 2 1 0 C2 C1 C0 MUL A3 A2 A1 A0 Bits 7–5 C[2:0] Command bits. These bits code the command within the command byte. C[2:0] DESCRIPTION COMMENTS 000 Channel Data Read Direct (no command) 001 Channel Data Read Command (register format) 010 Register Read Command 011 Register Write Command 100 Pulse Convert Command 101 Reserved 110 Reset Command 111 Channel Data Read Direct (no command) Bit 4 Toggle CS or allow SPI timeout before sending command Set MUL = 1; status byte always included in data A[3:0] = '0000' MUL, A[3:0] are don't care MUL, A[3:0] don't care Toggle CS or allow SPI timeout before sending command MUL Multiple Register Access This bit enables multiple register access. This option allows writing or reading of more than one register in a single command operation. If only one register is to be read or written, set MUL = '0'. For multiple register access, set MUL = '1'. The read or write operation begins at the addressed register. The ADS1258 automatically increments the register address for each register data byte subsequently read or written. The multiple register read or write operations complete after register address = 09h (device ID register) has been accessed. 0 = Disable Multiple Register Access 1 = Enable Multiple Register Access The multiple register access is terminated in one of three ways: 1. The user takes CS high. This action resets the SPI interface. 2. The user holds SCLK inactive for 4096 fCLK cycles. This action resets the SPI interface. 3. Register address = 09h has been accessed. This completes the command and the ADS1258 is then ready for a new command. Note for the Channel Data Read command, this bit must be set to read the four data bytes (one status byte and three data bytes). Bits 3–0 A[3:0] Register Address Bits These bits are the register addresses for a register read or write operation; see Table 15. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 35 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com REGISTERS Table 15. Register Map ADDRESS Bits A[3:0] REGISTER NAME DEFAULT VALUE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00h CONFIG0 0Ah 0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0 01h CONFIG1 83h IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0 02h MUXSCH 00h AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0 03h MUXDIF 00h DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0 04h MUXSG0 FFh AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 05h MUXSG1 FFh AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 06h SYSRED 00h 0 0 REF GAIN TEMP VCC 0 OFFSET 07h GPIOC FFh CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0 08h GPIOD 00h DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 09h ID 8Bh ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Table 16. CONFIG0: CONFIGURATION REGISTER 0 (Address = 00h) 7 6 5 4 3 2 1 0 0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0 Default = 0Ah. Bit 7 Must be 0 (default) Bit 6 SPIRST SPI Interface Reset Timer This bit sets the number of fCLK cycles in which SCLK is inactive the SPI interface will reset. This places a lower limit on the frequency of SCLK in which to read or write data to the device. The SPI interface only is reset and not the device itself. When the SPI interface is reset, it is ready for a new command. 0 = Reset when SCLK inactive for 4096fCLK cycles (256µs, fCLK = 16MHz) (default). 1 = Reset when SCLK inactive for 256fCLK cycles (16µs, fCLK = 16MHz). Bit 5 MUXMOD This bit sets either the Auto-Scan or Fixed-Channel mode of operation. 0 = Auto-Scan Mode (default) In Auto-Scan mode, the input channel selections are eight differential channels (DIFF0–DIFF7) and 16 single-ended channels (AIN0–AIN15). Additionally, five internal monitor readings can be selected. These selections are made in registers MUXDIF, MUXSG0, MUXSG1, and SYSRED. In this mode, settings in register MUXSCH have no effect. See the Auto-Scan Mode section for more details. 1 = Fixed-Channel Mode In Fixed-Channel mode, any of the analog input channels may be selected for the positive measurement and the negative measurement channels. The inputs are selected in register MUXSCH. In this mode, registers MUXDIF, MUXSG0, MUXSG1, and SYSRED have no effect. Note that it is not possible to select the internal monitor readings in this mode. Bit 4 BYPAS This bit selects either the internal or external connection from the multiplexer output to the ADC input. 0 = ADC inputs use internal multiplexer connection (default). 1 = ADC inputs use external ADC inputs (ADCINP and ADCINN). Note that the Temperature, VCC, Gain, and Reference internal monitor readings automatically use the internal connection, regardless of the BYPAS setting. The Offset reading uses the setting of BYPAS. 36 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com Bit 3 CLKENB This bit enables the clock output on pin CLKIO. The clock output originates from the device crystal oscillator and PLL circuit. 0 = Clock output on CLKIO disabled. 1 = Clock output on CLKIO enabled (default). Note: If the CLKSEL pin is set to '1', the CLKIO pin is a clock input only. In this case, setting this bit has no effect. Bit 2 CHOP This bit enables the chopping feature on the external multiplexer loop. 0 = Chopping Disabled (default) 1 = Chopping Enabled The chopping feature corrects for offset originating from components used in the external multiplexer loop; see the External Chopping section. Note that for Internal System readings (Temperature, VCC, Gain, and Reference), the CHOP bit must be 0. Bit 1 STAT Status Byte Enable When reading channel data from the ADS1258, a status byte is normally included with the conversion data. However, in some ADS1258 operating modes, the status byte can be disabled. Table 17, Status Byte, shows the modes of operation and the data read formats in which the status byte can be disabled. 0 = Status Byte Disabled 1 = Status Byte Enabled (default) Bit 0 Must be '0' Table 17. Status Byte CHANNEL DATA READ COMMAND CHANNEL DATA READ DIRECT Auto-Scan Always Enabled Enabled/Disabled by STAT Bit Fixed-Channel Always Enabled (Byte is Undefined) Always Disabled MODE Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 37 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com Table 18. CONFIG1: CONFIGURATION REGISTER 1 (Address = 01h) 7 6 5 4 3 2 1 0 IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0 Default = 83h. Bit 7 IDLMOD This bit selects the Idle mode when the device is not converting, Standby or Sleep. The Sleep mode offers lower power consumption but has a longer wake-up time to re-enter the run mode; see the Idle Modes section. 0 = Select Standby Mode 1 = Select Sleep Mode (default) Bits 6–4 DLY[2:0] These bits set the amount of time the converter will delay after indexing to a new channel but before starting a new conversion. This value should be set large enough to allow for the full settling of external filtering or buffering circuits used between the MUXOUTP, MUXOUTN, and ADCINP, ADCINN pins; see the Switch Time Delay section. (default = 000) Bits 3–2 SBCS[1:0] These bits set the sensor bias current source. 0 = Sensor Bias Current Source Off (default) 1 = 1.5µA Source 3 = 24µA Source Bits 1–0 DRATE[1:0] These bits set the data rate of the converter. Slower reading rates yield increased resolution; see Table 6. The actual data rates shown in the table can be slower, depending on the use of Switch Time Delay or the Chop feature. See the Switch Time Delay section. The reading rate scales with the master clock frequency. DRATE[1:0] DATA RATE AUTO-SCAN MODE (SPS) DATA RATE FIXED-CHANNEL MODE (SPS) 11 23739 125000 10 15123 31250 01 6168 7813 00 1831 1953 fCLK = 16MHz, Chop = 0, Delay = 0. 38 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com Table 19. MUXSCH: MULTIPLEXER FIXED-CHANNEL REGISTER (Address = 02h) 7 6 5 4 3 2 1 0 AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0 Default = 00h. This register selects the input channels of the multiplexer to be used for the Fixed-Channel mode. The MUXMOD bit in register CONFIG0 must be set to '1'. In this mode, bits AINN[3:0] select the analog input channel for the negative ADC input, and bits AINP[3:0] select the analog input channel for the positive ADC input. See the Fixed-Channel Mode section. Table 20. MUXDIF: MULTIPLEXER DIFFERENTIAL INPUT SELECT REGISTER (Address = 03h) 7 6 5 4 3 2 1 0 DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0 Default = 00h. Table 21. MUXSG0: MULTIPLEXER SINGLE-ENDED INPUT SELECT REGISTER 0 (Address = 04h) 7 6 5 4 3 2 1 0 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 Default = FFh. Table 22. MUXSG1: MULTIPLEXER SINGLE-ENDED INPUT SELECT REGISTER 1 (Address = 05h) 7 6 5 4 3 2 1 0 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 Default = FFh. Table 23. SYSRED: SYSTEM READING SELECT REGISTER (Address = 06h) 7 6 5 4 3 2 1 0 0 0 REF GAIN TEMP VCC 0 OFFSET Default = 00h. These four registers select the input channels and the internal readings for measurement in Auto-Scan mode. For differential channel selections (DIFF0…DIFF7), adjacent input pins (AIN0/AIN1, AIN2/AIN3, etc.) are pre-set as differential inputs. All single-ended inputs are measured with respect to the AINCOM input. AINCOM may be set to any level within ±100mV of the analog supply range. Channels not selected are skipped in the measurement sequence. Writing to any of these four registers resets the internal channel pointer to the channel with the highest priority (see Table 13). Note that the bits indicated as '0' must be set to 0. 0 = Channel not selected within a reading sequence. 1 = Channel selected within a reading sequence. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 39 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com Table 24. GPIOC: GPIO CONFIGURATION REGISTER (Address = 07h) 7 6 5 4 3 2 1 0 CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0 Default = FFh. This register configures the GPIO pins as inputs or as outputs. Note that the default configurations of the port pins are inputs and as such they should not be left floating. See the GPIO Digital Port section. 0 = GPIO is an output; 1 = GPIO is an input (default). CIO[7:0] GPIO Configuration Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 CIO7, CIO6, CIO5, CIO4, CIO3, CIO2, CIO1, CIO0, Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Configuration Bit Configuration Bit Configuration Bit Configuration Bit Configuration Bit Configuration Bit Configuration Bit Configuration Bit for for for for for for for for Pin GPIO7 Pin GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin GPIO2 Pin GPIO1 Pin GPIO0 Table 25. GPIOD: GPIO DATA REGISTER (Address = 08h) 7 6 5 4 3 2 1 0 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 Default = 00h. This register is used to read and write data to the GPIO port pins. When reading this register, the data returned corresponds to the state of the GPIO external pins, whether they are programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the GPIOD has no effect. See the GPIO Digital Port section. 0 = GPIO is logic low (default); 1 = GPIO is logic high. DIO[7:0] GPIO Data Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 DIO7, DIO6, DIO5, DIO4, DIO3, DIO2, DIO1, DIO0, Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Data Data Data Data Data Data Data Data bit bit bit bit bit bit bit bit for Pin for Pin for Pin for Pin for Pin for Pin for Pin for Pin GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Table 26. ID: DEVICE ID REGISTER (Address = 09h) 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Default = 8Bh. Bits 7–0 ID[7:0] Factory-programmed ID bits. Read-only. NOTE: except for ID4, the ID byte is subject to change at any time without notice. Bit 4 ID4 0 = ADS1258 (24-bit ADC) 1 = ADS1158 (16-bit ADC) 40 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com APPLICATIONS HARDWARE CONSIDERATIONS AVDD The following summarizes the design and layout considerations when using the ADS1258: a. Power Supplies: The converter accepts a single +5V supply (AVDD = +5V and AVSS = AGND) or dual, bipolar supplies (typically AVDD = +2.5V, AVSS = –2.5V). Dual supply operation accommodates true bipolar input signals, within a ±2.5V range. Note that the maximum negative input voltage to the multiplexer is limited to AVSS – 100mV, and the maximum positive input voltage is limited to AVDD + 100mV. The range for the digital power supply (DVDD) is 2.7V to 5.25V. For all supplies, use a 10μF tantalum capacitor, bypassed with a 0.1μF ceramic capacitor, placed close to the device pins. Alternatively, a single 10μF ceramic capacitor can be used. The supplies should be relatively free from noise and should not be shared with devices that produce voltage spikes (such as relays, LED display drivers, etc.). If a switching power supply is used, the voltage ripple should be low (< 2mV). The analog and digital power supplies may be sequenced in any order. b. Analog (Multiplexer) Inputs: The 16-channel analog input multiplexer can accommodate 16 single-ended inputs, eight differential input pairs, or combinations of either. These options permit freedom in choosing the input channels. The channels do not have to be used consecutively. Unassigned channels are skipped by the device. In the Fixed-Channel mode, any of the analog inputs (AIN0 to AIN15) can be addressed for the positive input and for the negative input. The full-scale range of the device is 2.13VREF, but the absolute analog input voltage is limited to 100mV beyond the analog supply rails. Input signals exceeding the analog supply rails (for example, ±10V) must be divided prior to the multiplexer inputs. c. Input Overload Protection: Overdriving the multiplexer inputs may affect the conversions of other channels. In the case of input overload, external Schottky diode clamps and series resistor are recommended, as shown in Figure 61. BAT54SWTI 10kΩ Input AINx typ. AVSS Figure 62. Input Overload Protection d. ADC Inputs: The external multiplexer loop of the ADS1258 allows for the inclusion of signal conditioning between the output of the multiplexer and the input of the ADC. Typically, an amplifier is used to provide gain, buffering, and/or filtering to the input signal. For best performance, the ADC inputs should be driven differentially. A differential in/differential out or a single-ended-to-differential driver is recommended. If the driver uses higher supply voltages than the device itself (for example, ±15V), attention should be paid to power-supply sequencing and potential over-voltage fault conditions. Protection resistors and/or external clamp diodes may be used to protect the ADC inputs. A 1nF or higher capacitor should be used directly across the ADC inputs. e. Reference Inputs: It is recommended to use a 10μF tantalum with a 0.1μF ceramic capacitor directly across the reference pins, VREFP and VREFN. The reference inputs should be driven by a low-impedance source. For rated performance, the reference should have less than 3μVRMS broadband noise. For references with higher noise, external filtering may be necessary. Note that when exiting the sleep mode, the device begins to draw a small current through the reference pins. Under this condition, the transient response of the reference driver should be fast enough to settle completely before the first reading is taken, or simply discard the first several readings. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 41 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com f. Clock Source: The ADS1258 requires a clock signal for operation. The clock can originate from either the crystal oscillator or from an external clock source. The internal oscillator uses a PLL circuit and an external 32.768kHz crystal to generate a 15.7MHz master clock. The PLL requires a 22nF capacitor from the PLLCAP pin to AVSS. The crystal and load capacitors should be placed close to the pins as possible and kept away from other traces with AC components. A buffered output of the 15.7MHz clock can be used to drive other converters or controllers. An external clock source can be used up to 16MHz. For best performance, the clock of the SPI interface controller and the converter itself should be on the same domain. This configuration requires that the ratio of the SCLK to device clock must be limited to 1,1/2,1/4, 1/8, etc. g. Digital Inputs: It is recommended to source terminate the digital inputs and outputs of the device with a 50Ω (typical) series resistor. The resistors should be placed close to the driving end of the source (output pins, oscillator, logic gates, DSP, etc). This placement helps to reduce the ringing and overshoot on the digital lines. h. Hardware Pins: START, DRDY, RESET, and PWDN. These pins allow direct pin control of the ADS1258. The equivalent of the START and DRDY pins is provided via commands through the SPI interface; these pins may be left unused. The device also has a RESET command. The PWDN pin places the ADC into very low-power state where the device is inactive. i. SPI Interface: The ADS1258 has an SPI-compatible interface. This interface consists of four signal lines: SCLK, DIN, DOUT, and CS. When CS is high, the DIN input is ignored and the DOUT output tri-states. See Chip Select (CS ) for more details. The SPI interface can be operated in a minimum configuration without the use of CS (tie CS low; see the Serial Interface and Communication Protocol sections). j. GPIO: The ADS1258 has eight, userprogrammable digital I/O pins. These pins are controlled by register settings. The register setting is default to inputs. If these pins are not used, tie them high or low (do not float input pins) or configure them as outputs. k. QFN Package: See Application Note SLUA271, 42 QFN/SON PCB Attachment for PCB layout recommendations, available for download at www.ti.com. The exposed thermal pad of the ADS1258 should be connected electrically to AVSS. CONFIGURATION GUIDE Configuration of the ADS1258 involves setting the configuration registers via the SPI interface. After the device is configured for operation, channel data is read from the device through the same SPI interface. The following is a suggested procedure for configuring the device: 1. Reset the SPI Interface: Before using the SPI interface, it may be necessary to recover the SPI interface. To reset the interface, set CS high or disable SCLK for 4096 (256) fCLK cycles. 2. Stop the Converter: Set the START pin low to stop the converter. Although not necessary for configuration, this command stops the channel scanning sequence which then points to the first channel after configuration. 3. Reset the Converter: The reset pin can be pulsed low or a Reset command can be sent. Although not necessary for configuration, reset re-initializes the device into a known state. 4. Configure the Registers: The registers are configured by writing to them either sequentially or as a group. The user may configure the software in either mode. Any write to the Auto-Scan channel-select registers resets the channel pointer to the channel of highest priority. 5. Verify Register Data: The register data may be read back for verification of device communications. 6. Start the Converter: The converter can be started with the START pin or with a Pulse Convert command sent through the interface. 7. Read Channel Data: The DRDY asserts low when data is ready. The channel data can be read at that time. If DRDY is not used, the updated channel data can be checked by reading the NEW bit in the status byte. The status byte also indicates the origin of the channel data. If the data for a given channel is not read before DRDY asserts low again, the data for that channel is lost and replaced with new channel data. Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com DIGITAL INTERFACE CONNECTIONS The ADS1258 SPI-compatible interface easily connects to a wide variety of microcontrollers and DSPs. Figure 63 shows the basic connection to TI's MSP430 family of low-power microcontrollers. Figure 64 shows the connection to microcontrollers with an SPI interface such as the 68HC11 family, or TI's MSC12xx family. Note that the MSC12xx includes a high-resolution ADC; the ADS1258 can be used to provide additional channels of measurement or add higher-speed connections. Finally, Figure 65 shows how to connect the ADS1258 to a TMS320x DSP. ADS1258 TMS320R2811 DIN SPISIMO DOUT SPISOMI DRDY XINT1 SCLK SPICLK CS(1) SPISTA (1) CS may be tied low. Figure 65. Connection to a TMS320R2811 DSP ADS1258 MSP430 GPIO Connections DIN P1.3 DOUT P1.2 DRDY P1.0 SCLK P1.6 CS(1) P1.4 The ADS1258 has eight general purpose input/output (GPIO) pins. Each pin can be configured as an input or an output. Note that pins configured as inputs should not float. The pins can be used to read key pads, drive LED indicator, etc., by reading and writing the GPIO data register (GPIOD). See Figure 66. (1) CS may be tied low. 3.3V Figure 63. Connection to MSP430 Microcontroller 10kΩ ADS1258 GPIOx (Input) ADS1258 Key Pad MSC12xx or 68HC11 3.3V LED Indicator DIN MOSI DOUT MISO DRDY INT SCLK SCK CS(1) 470 GPIOx (Output) 4.7kΩ IO (1) CS may be tied low. Figure 66. GPIO Connections Figure 64. Connection to Microcontrollers with an SPI Interface Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 43 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com ANALOG INPUT CONNECTIONS Figure 67 shows the ADS1258 interfacing to high-level ±10V inputs, commonly used in industrial environments. In this case, bipolar power supplies are used, avoiding the need for input signal level-shifting otherwise required when a single supply is used. The input resistors serve both to reduce the level of the 10V input signal to within the ADC range and also protect the inputs from inadvertent signal over-voltage up to 30V. The external amplifiers convert the single-ended inputs to a fully differential output to drive the ADC inputs. Driving the inputs differentially maintains good linearity performance. The 2.2nF capacitor at the ADC inputs is required to bypass the ADC sampling currents. The 2.5V reference, REF3125, is filtered and buffered to provide a low-noise reference input to the ADC. The chop feature of the ADC can be used to reduce offset and offset drift of the amplifiers. For ±1V input signals, the input resistor divider can be removed and replaced with a series protection resistor. For 20mA input signals, the input resistor divider is replaced by a 50Ω resistor, connected from each input to AINCOM. − 2.5V When using Auto-Scan mode to sequence through the channels, the switch time delay feature (programmable by registers) can be used to provide additional settling time of the external components. Figure 68 illustrates the ADS1258 interfacing to multiple pressure sensors having a resistor bridge output. Each sensor is excited by the +5V single supply that also powers the ADS1258 and likewise is used as the ADS1258 reference input; the 6% input overrange capability accommodates input levels at or above VREF. The ratiometric connection provides cancellation of excitation voltage drift and noise. For best performance, the +5V supply should be free from glitches or transients. The 5V supply input amplifiers (two OPA365s) form a differential input/differential output buffer with the gain set to 10. The chop feature of the ADS1258 is used to reduce offset and offset drift to very low levels. The 2.2nF capacitor at the ADC inputs is required to bypass the ADC sampling currents. The 47Ω resistors isolate the op-amp outputs from the filter capacitor. +2.5V + 0 .1µF 10µF 1 0µF 0.1µF + +2.5V +2 .5V A VS S AV DD 9.09kΩ ± 10V OP A350 A IN0 … A INCOM 10 µF − 2.5V + 10 0µF A DCINN 1kΩ + 0.47µF 0.1µF R EF N A DCINP A IN15 MU XOUTP 9.09kΩ ± 10V 10 kΩ REF 3125 0 .1µF AD S1258 MU XOUTN … 1kΩ 100Ω RE FP − 2.5V NOTE : 0.1µF ca pacitors no t shown. 2 .2n F 47Ω +2.5 V 10kΩ 20m A Input 1 0kΩ A INx OP A365 +2.5V 47 Ω 50Ω − 2.5 V O PA365 − 2.5V Figure 67. Multichannel, ±10V Single-Ended Input, Bipolar Supply Operation 44 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com +5V RFI + 0.1mF 10mF 2kW RFI AVSS AIN0 AVDD 2kW RFI REFP AIN1 0.1mF REFN ADS1258 ADCINN ADCINP AINCOM MUXOUTP AIN15 MUXOUTN AIN14 2kW RFI 10mF ¼ ¼ ¼ 2kW RFI + RFI +5V 2.2nF 47W OPA365 R2 10kW NOTE: G = 1 + 2R2/R1. 0.1mF supply bypass capacitor not shown. R1 2.2kW R2 10kW 47W OPA365 Figure 68. Bridge Input, Single-Supply Operation Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 45 ADS1258 SBAS297G – JUNE 2005 – REVISED MARCH 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (October 2010) to Revision G • Page Updated bit descriptions for Table 26 ................................................................................................................................. 40 Changes from Revision E (October 2007) to Revision F Page • Updated document format to current standards ................................................................................................................... 1 • Added new row and notes to Temperature Sensor Reading Coefficient parameter ............................................................ 3 • Changed Figure 3 ................................................................................................................................................................. 8 • Added more approved crystals to Table 4 .......................................................................................................................... 17 • Changed Equation 10 ......................................................................................................................................................... 26 • Added comment to Register Read Command in Command Bits table .............................................................................. 35 46 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1258 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS1258IRTCR ACTIVE VQFN RTC 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 ADS1258 ADS1258IRTCRG4 ACTIVE VQFN RTC 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 ADS1258 ADS1258IRTCT ACTIVE VQFN RTC 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 ADS1258 ADS1258IRTCTG4 ACTIVE VQFN RTC 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 ADS1258 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 OTHER QUALIFIED VERSIONS OF ADS1258 : • Enhanced Product: ADS1258-EP NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1258IRTCR VQFN RTC 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS1258IRTCT VQFN RTC 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1258IRTCR VQFN RTC 48 2500 336.6 336.6 28.6 ADS1258IRTCT VQFN RTC 48 250 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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