28LV64A 64K (8K x 8) Low Voltage CMOS EEPROM 30 NC 32 Vcc 31 WE 2 RDY/BSY 1 NU 29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 20 19 18 17 16 15 21 I/O6 14 Vcc WE NC A8 A6 5 A9 A5 6 A11 A4 7 A3 8 OE A10 A2 9 A1 10 CE A0 11 I/O7 NC 12 I/O6 I/O0 13 I/O5 I/O4 I/O3 BLOCK DIAGRAM The Microchip Technology Inc. 28LV64A is a CMOS 64K non-volatile electrically Erasable PROM organized as 8K words by 8 bits. The 28LV64A is accessed like a static RAM for the read or write cycles without the need of external components. During a “byte write”, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in ‘wired-or’ systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications. 1988 Microchip Technology Inc. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 • Pin 1 indicator on PLCC on top of package DESCRIPTION Powered by ICminer.com Electronic-Library Service CopyRight 2003 •1 2 3 4 5 6 7 8 9 10 11 12 13 14 PLCC RDY/BSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS DIP/SOIC • 2.7V to 3.6V Supply • Read Access Time—300 ns • CMOS Technology for Low Power Dissipation - 8 mA Active - 50 µA CMOS Standby Current • Byte Write Time—3 ms • Data Retention >200 years • High Endurance - Minimum 100,000 Erase/Write Cycles • Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches • Data Polling • Ready/Busy • Chip Clear Operation • Enhanced Data Protection - VCC Detector - Pulse Filter - Write Inhibit • Electronic Signature for Device Identification • Organized 8Kx8 JEDEC Standard Pinout - 28-pin Dual-In-Line Package - 32-pin Chip Carrier (Leadless or Plastic) • Available for Extended Temperature Ranges: - Commercial: 0˚C to +70˚C - Industrial: -40˚C to +85˚C 4 A7 3 A12 PACKAGE TYPES I/O1 I/O2 Vss NU I/O3 I/O4 I/O5 FEATURES Preliminary I/O0...................I/O7 VSS VCC Data Protection Circuitry Chip Enable/ Output Enable Control Logic CE OE WE Rdy/ Busy A0 I I I I I I I I I I I A12 Auto Erase/Write Timing Data Poll Input/Output Buffers Program Voltage Generation L a t c h e s Y Decoder Y Gating X Decoder 64K bit Cell Matrix DS21113D-page 1 28LV64A 1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: PIN FUCTION TABLE Name MAXIMUM RATINGS* VCC and input voltages w.r.t. VSS ...... -0.6V to + 6.25V Function A0 - A12 Address Inputs CE Chip Enable to +13.5V OE Output Enable Voltage on A9 w.r.t. VSS ....................... -0.6V to +13.5V WE Write Enable Output Voltage w.r.t. VSS .................-0.6V to VCC+0.6V I/O0 - I/O7 Data Inputs/Outputs Storage temperature .......................... -65˚C to +150˚C RDY/Busy Ready/Busy Ambient temp. with power applied......-55°C to +125°C VCC + Power Supply VSS Ground NC No Connect; No Internal Connection NU Not Used; No External Connection is Allowed Voltage on OE w.r.t. VSS ...................... -0.6V *Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: READ/WRITE OPERATION DC CHARACTERISTICS VCC = 2.7 to 3.6V Commercial (C): Tamb = 0°C to 70°C Industrial (I): Tamb = -40°C to 85°C Parameter Input Voltages Input Leakage Input Capacitance Output Voltages Output Leakage Output Capacitance Power Supply Current, Activity Power Supply Current, Standby Status Symbol Min Logic “1” Logic “2” — — VIH VIL ILI CIN 2.0 Logic “1” Logic “0” VOH VOL 2.0 — — ILO COUT TTL input ICC TTL input ICC(S)TTL TTL input ICC(S)TTL CMOS input ICC(S)CMOS Max Units 0.6 5 6 V V µA pF 0.3 V V — — 5 12 µA pF — 8 mA — 2 3 100 mA mA µA — — Conditions VIN = 0V to VCC+1 Vin = 0V; Tamb = 25°C; f = 1 MHz (Note 1) IOH = -100µA IOL = 1.0 mA I0L = 2.0 mA for RDY/Busy VOUT = 0V to VCC+0.1V VOUT = 0V; Tamb = 25°C; f = 1 MHz (Note 1) f = 5 MHz (Note 2) IO = OmA VCC = 3.3 CE = VIL CE = VIH (0°C to 70°C°) CE = VIH (-40°C to 85°C°) CE = VCC -3.0 to VCC+1 OE = WE = VCC All other inputs equal VCC or VSS Note 1: Not 100% tested. 2: AC power supply current above 5 MHz: 2 mA/Mhz. DS21113D-page 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Preliminary 1988 Microchip Technology Inc. 28LV64A TABLE 1-3: READ OPERATION AC CHARACTERISTICS AC Testing Waveform: Output Load: Input Rise and Fall Times: Ambient Temperature: Parameter Sym VIH = 2.0V; VIL = 0.6V; VOH = VOL = VCC/2 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0°C to +70°C Industrial (I) : Tamb = -40°C to +85°C 28LV64-30 Units Conditions Min Max tACC — 300 ns OE = CE = VIL CE to Output Delay tCE — 300 ns OE = VIL OE to Output Delay tOE — 150 ns CE = VIL CE or OE High to Output Float tOFF 0 60 ns (Note 1) Output Hold from Address, CE or OE, whichever occurs first. tOH 0 — ns (Note 1) Endurance — 10M — cycles Address to Output Delay 25°C, Vcc = 5.0V, Block Mode (Note 2) Note 1: Not 100% tested. 2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website. FIGURE 1-1: READ WAVEFORMS VIH Address Address Valid VIL VIH CE VIL t CE(2) VIH OE VIL VOH Data t OE(2) High Z t OFF(1,3) t OH Valid Output High Z VOL t ACC VIH WE VIL Notes: (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on tCE (3) This parameter is sampled and is not 100% tested 1988 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 Preliminary DS21113D-page 3 28LV64A TABLE 1-4: BYTE WRITE AC CHARACTERISTICS AC Testing Waveform: Output Load: Input Rise/Fall Times: Ambient Temperature: Parameter VIH = 2.0V; VIL = 0.6V; VOH = VOL = VCC/2 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0°C to +70°C Industrial (I) : Tamb = -40°C to +85°C Sym Min Max Units Address Set-Up Time tAS 10 ns Address Hold Time tAH 100 ns Data Set-Up Time tDS 120 ns Data Hold Time tDH 10 ns Write Pulse Width tWPL 150 ns OE Hold Time tOEH 10 ns OE Set-Up Time tOES 10 ns Data Valid Time tDV 1000 ns Time to Device Busy tDB 50 ns Write Cycle Time (28LV64A) tWC 3 ms Remarks (Note 1) (Note 2) 1.5 ms typical Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the positive edge of CE or WE, whichever occurs first. 2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH after the positive edge of WE or CE, whichever occurs first. FIGURE 1-2: PROGRAMMING WAVEFORMS Address CE, WE VIH VIL VIH tAS tAH tWPL VIL Data In tDV VIH tDS tDH VIL tOES OE VIH VIL tOEH VOH Rdy/Busy VOL DS21113D-page 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Busy twc Preliminary tDB Ready 1988 Microchip Technology Inc. 28LV64A FIGURE 1-3: DATA POLLING WAVEFORMS VIH Last Written Address Valid Address Valid Address VIL t ACC VIH CE t CE VIL t WPH VIH t WPL WE VIL t OE VIH OE VIL t DV VIH Data In Valid Data VIL I/O7 Out True Data Out t WC FIGURE 1-4: CHIP CLEAR WAVEFORMS VIH CE VIL VH OE VIH tS tH tW VIH WE tW = 10ms tS = tH = 1µs VH = 12.0V ±0.5V VIL TABLE 1-5: SUPPLEMENTARY CONTROL Mode Chip Clear Extra Row Read Extra Row Write Note: VH = 12.0V ± 0.5V 1988 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 CE OE VIL VIL VH VIL VIH Preliminary WE AI VCC I/OI VIH X A9 = VH A9 = VH VCC VCC VCC Data Out Data In DS21113D-page 5 28LV64A 2.0 DEVICE OPERATION 2.4 The Microchip Technology Inc. 28LV64A has four basic modes of operation—read, standby, write inhibit, and byte write—as outlined in the following table. Operation Mode CE OE WE I/O Read Standby Write Inhibit Write Inhibit Write Inhibit Byte Write Byte Clear L H H X X L L X X L X H H X X X H L DOUT High Z High Z High Z High Z DIN Rdy/Busy(1) H H H H H L 2.1 Read Mode The 28LV64A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and is used to gate data to the output pins independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the output tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC-tOE. 2.2 Standby Mode The 28LV64A is placed in the standby mode by applying a high signal to the CE input. When in the standby mode, the outputs are in a high impedance state, independent of the OE input. 2.3 The 28LV64A has a write cycle similar to that of a static RAM. The write cycle is completely self-timed and initiated by a low going pulse on the WE pin. On the falling edge of WE, the address information is latched. On rising edge, the data and the control pins (CE and OE) are latched. The Ready/Busy pin goes to a logic low level indicating that the 28LV64A is in a write cycle which signals the microprocessor host that the system bus is free for other activity. When Ready/Busy goes back to a high, the 28LV64A has completed writing and is ready to accept another cycle. 2.5 Automatic Before Each "Write" Note: (1) Open drain output. Data Protection Write Mode Data Polling The 28LV64A features Data polling to signal the completion of a byte write cycle. During a write cycle, an attempted read of the last byte written results in the data complement of I/O7 (I/O0 to I/O6 can not be determined). After completion of the write cycle, true data is available. Data polling allows a simple read/compare operation to determine the status of the chip eliminating the need for external hardware. 2.6 Electronic Signature for Device Identification An extra row of 32 bytes of EEPROM memory is available to the user for device identification. By raising A9 to 12V ±0.5V and using address locations 1FEO to 1FFF, the additional bytes can be written to or read from in the same manner as the regular memory array. 2.7 Chip Clear All data may be cleared to 1's in a chip clear cycle by raising OE to 12 volts and bringing the WE and CE low. This procedure clears all data, except for the extra row. In order to ensure data integrity, especially during critical power-up and power-down transitions, the following enhanced data protection circuits are incorporated: First, an internal VCC detect (2.0 volts typical) will inhibit the initiation of non-volatile programming operation when VCC is less than the VCC detect circuit trip. Second, holding WE or CE high or OE low, inhibits a write cycle during power-on and power-off (VCC). DS21113D-page 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Preliminary 1988 Microchip Technology Inc. 28LV64A 28LV64A Product Identification System To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices. 28LV64A – F T – 20 I /P Package: Temperature Range: Access Time: L = Plastic Leaded Chip Carrier (PLCC) P = Plastic DIP SO = Plastic Small Outline IC Blank = 0°C to +70°C I = -40°C to +85°C 20 = 200 ns 30 - 300 ns Shipping: Blank = Tube T = Tape and Reel “L” and “SO” Option: Blank = twc = 1ms F = twc = 200µs Device: 1988 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 24LV64A 8K x 8 CMOS EEPROM DS21113D-page 7 WORLDWIDE SALES AND SERVICE AMERICAS AMERICAS (continued) Corporate Office Toronto Singapore Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850 Atlanta Microchip Asia Pacific Unit 2101, Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas Microchip Technology Inc. 4570 Westgrove Drive, Suite 160 Addison, TX 75248 Tel: 972-818-7423 Fax: 972-818-2924 Dayton Microchip Technology Inc. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan’an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Italy 11/15/99 Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. 1999 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003