28C64A 64K (8K x 8) CMOS EEPROM 30 NC 2 RDY/BSY 1 NU 32 Vcc 31 WE 4 A7 3 A12 29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 20 19 18 17 21 I/O6 16 Vcc WE NC A8 A6 5 A9 A5 6 A11 A4 7 A3 8 OE A10 A2 9 A1 10 CE A0 11 I/O7 NC 12 I/O6 I/O0 13 I/O5 I/O4 I/O3 15 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 •1 2 3 4 5 6 7 8 9 10 11 12 13 14 PLCC DESCRIPTION RDY/BSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS DIP/SOIC • Fast Read Access Time—150 ns • CMOS Technology for Low Power Dissipation - 30 mA Active - 100 µA Standby • Fast Byte Write Time—200 µs or 1 ms • Data Retention >200 years • High Endurance - Minimum 100,000 Erase/Write Cycles • Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches • Data Polling • Ready/Busy • Chip Clear Operation • Enhanced Data Protection - VCC Detector - Pulse Filter - Write Inhibit • Electronic Signature for Device Identification • 5-Volt-Only Operation • Organized 8Kx8 JEDEC Standard Pinout - 28-pin Dual-In-Line Package - 32-pin PLCC Package - 28-pin SOIC Package • Available for Extended Temperature Ranges: - Commercial: 0˚C to +70˚C - Industrial: -40°C to +85°C PACKAGE TYPES I/O1 I/O2 Vss NU I/O3 I/O4 I/O5 FEATURES • Pin 1 indicator on PLCC on top of package BLOCK DIAGRAM I/O0 VSS VCC Data Protection Circuitry Chip Enable/ Output Enable Control Logic CE OE WE Rdy/ Busy I/O7 Auto Erase/Write Timing Data Poll Input/Output Buffers Program Voltage Generation A0 L a t c h e s Y Decoder Y Gating X Decoder 16K bit Cell Matrix A12 The Microchip Technology Inc. 28C64A is a CMOS 64K nonvolatile electrically Erasable PROM. The 28C64A is accessed like a static RAM for the read or write cycles without the need of external components. During a “byte write”, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/ Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in wiredor systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is complete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reliability are required. A complete family of packages is offered to provide the utmost flexibility in applications. 1998 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 DS11109J-page 1 28C64A 1.0 ELECTRICAL CHARACTERISTICS 1.1 MAXIMUM RATINGS* TABLE 1-1: PIN FUNCTION TABLE Name Function VCC and input voltagesw.r.t. V SS ....... -0.6V to + 6.25V A0 - A12 Voltage on OE w.r.t. VSS ..................... . -0.6V to +13.5V CE Chip Enable OE Output Enable WE Wr ite Enable . -0.6V to +13.5V Voltage on A9w.r.t. V SS ...................... Output Voltage w.r.t. VSS..................-0.6V to V CC+0.6V Storage temperature ......................... . -65˚C to +125˚C Ambient temp. with power applied........ -50˚C to +95˚C *Notice: Stresses ab ove those listed unde r “Maxi mum Ratings” may cause pe r manent damage to the e dvice. This is a stressrating only and functional operation of the device at those or any other conditions above those indicated in the ope ration listings of this specification is not implied. Exposure to maximum r ating conditions for extended per iods may affect device reliabilit y. TABLE 1-2: Address Inputs I/O0 - I/O7 Data Inputs/Outputs RDY/Busy Ready/Busy VCC +5V Power Supply VSS Ground NC No Connect; No Inter nal Connection NU Not Used; No Exter nal Connection is All owed READ/WRITE OPERATION DC CHARACTERISTIC VCC = +5V ±10% Commercial (C): Tamb = 0˚C to +70˚C Industr ial (I): Tamb = -40˚C to +85˚C Parameter Status Symbol Min Max Units Input Voltages Logic ‘1’ Logic ‘0’ VIH VIL 2.0 -0.1 Vcc+1 0.8 V V Input Leakage — I LI -10 10 µA VIN = -0.1V to Vcc +1 Input Capacitance — C IN — 10 pF V IN = 0V; Tamb = 25˚C; f = 1 MHz (Note 2) Logic ‘1’ Logic ‘0’ VOH VOL 2.4 0.45 V V IOH = -400 µA IOL = 2.1 mA Output Leakage — I LO -10 10 µA VOUT = -0.1V to Vcc +0.1V Output Capacitance — C OUT — 12 pF V IN = 0V; Tamb = 25˚C; f = 1 MHz (Note 2) TTL input ICC — 30 mA f = 5 MHz (Note 1) VCC = 5.5V — 2 3 100 mA mA µA CE = V IH (0˚C to +70˚C) CE = V IH (-40˚C to +85˚C) CE = V CC-0.3 to Vcc +1 OE = WE = Vcc All other inputs equal V CC or VSS Output Voltages Power Supply Current, Acti ve Power Supply Current, Standby TTL input ICC(S)TTL TTL input ICC(S)TTL CMOS input ICC(S)CMOS Conditions Note 1: AC power supply current above 5MHz: 2mA/MHz. 2: Not 100% tested. DS11109J-page 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 1998 Microchip Technology Inc. 28C64A TABLE 1-3: READ OPERATION AC CHARACTERISTICS AC Testing Waveform: Output Load: Input Rise and Fall Times: Ambient Temperature: VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C 28C64A-15 Parameter 28C64A-20 28C64A-25 Symbol Min Max Min Max Min Max Units Conditions Address to Output Delay tACC — 150 — 200 — 250 ns OE = CE = VIL CE to Output Delay tCE — 150 — 200 — 250 ns OE = VIL OE to Output Delay tOE — 70 — 80 — 100 ns CE = VIL CE or OE High to Output Float tOFF 0 50 0 55 0 70 ns (Note 1) Output Hold from Address, CE or OE, whichever occurs first. tOH 0 — 0 — 0 — ns (Note 1) Endurance — 1M — 1M — 1M — cycles 25°C, Vcc = 5.0V, Block Mode (Note 2) Note 1: Not 100% tested. 2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website. FIGURE 1-1: READ WAVEFORMS VIH Address Address Valid VIL VIH CE VIL t CE(2) VIH OE VIL VOH Data t OE(2) High Z t OFF(1,3) t OH Valid Output High Z VOL t ACC VIH WE VIL Notes: (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed up to t CE - tOE after the falling edge of CE without impact on tCE (3) This parameter is sampled and is not 100% tested 1998 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 DS11109J-page 3 28C64A TABLE 1-4: BYTE WRITE AC CHARACTERISTICS AC Testing Waveform: Output Load: Input Rise/Fall Times: Ambient Temperature: Parameter VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V 1 TTL Load + 100 pF 20 ns Commercial (C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Symbol Min Max Units Remarks Address Set-Up Time tAS 10 — ns Address Hold Time tAH 50 — ns Data Set-Up Time tDS 50 — ns Data Hold Time tDH 10 — ns Write Pulse Width tWPL 100 — ns Write Pulse High Time tWPH 50 — ns OE Hold Time tOEH 10 — ns OE Set-Up Time tOES 10 — ns Data Valid Time tDV — 1000 ns Time to Device Busy tDB 2 50 ns Write Cycle Time (28C64A) tWC — 1 ms 0.5 ms typical Write Cycle Time (28C64AF) tWC — 200 µs 100 µs typical Note 1 Note 2 Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the positive edge WE, whichever occurs first. 2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH after the positive edge of WE or CE, whichever occurs first. FIGURE 1-2: PROGRAMMING WAVEFORMS VIH Address VIL VIH t AS t AH t WPL CE, WE VIL t DV Data In t DS t DH VIH VIL t OES VIH OE VIL t OEH VOH Rdy/Busy Busy VOL DS11109J-page 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t WC Ready t DB 1998 Microchip Technology Inc. 28C64A FIGURE 1-3: DATA POLLING WAVEFORMS VIH Last Written Address Valid Address Valid Address VIL t ACC VIH CE t CE VIL t WPH VIH t WPL WE VIL t OE VIH OE VIL t DV VIH Data In Valid Data VIL I/O7 Out True Data Out t WC FIGURE 1-4: CHIP CLEAR WAVEFORMS VIH CE VIL VH OE VIH tS tH tW VIH WE tW = 10ms tS = tH = 1µs VH = 12.0V ±0.5V VIL TABLE 1-5: SUPPLEMENTARY CONTROL CE OE WE A9 VCC Chip Clear VIL VIH VIL X VCC Extra Row Read VIL VIL VIH A9 = VH VCC Data Out Extra Row Write * VIH * A9 = VH VCC Data In Mode Note: VH = 12.0V±0.5V. I/OI *Pulsed per programming waveforms. 1998 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 DS11109J-page 5 28C64A 2.0 DEVICE OPERATION 2.4 The Microchip Technology Inc. 28C64A has four basic modes of operation—read, standby, write inhibit, and byte write—as outlined in the following table. CE OE WE I/O Rdy/Busy (1) Read L L H DOUT H Standby H X X High Z H Write Inhibit H X X High Z H Write Inhibit X L X High Z H Write Inhibit X X H High Z H Byte Write L H L DIN L Operation Mode Byte Clear Automatic Before Each “Write” Note 1: Open drain output. 2: X = Any TTL level. 2.1 Read Mode The 28C64A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and is used to gate data to the output pins independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the output tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC-tOE. 2.2 Standby Mode Write Mode The 28C64A has a write cycle similar to that of a Static RAM. The write cycle is completely self-timed and initiated by a low going pulse on the WE pin. On the falling edge of WE, the address information is latched. On rising edge, the data and the control pins (CE and OE) are latched. The Ready/Busy pin goes to a logic low level indicating that the 28C64A is in a write cycle which signals the microprocessor host that the system bus is free for other activity. When Ready/Busy goes back to a high, the 28C64A has completed writing and is ready to accept another cycle. 2.5 Data Polling The 28C64A features Data polling to signal the completion of a byte write cycle. During a write cycle, an attempted read of the last byte written results in the data complement of I/O7 (I/O0 to I/O6 are indeterminable). After completion of the write cycle, true data is available. Data polling allows a simple read/compare operation to determine the status of the chip eliminating the need for external hardware. 2.6 Electronic Signature for Device Identification An extra row of 32 bytes of EEPROM memory is available to the user for device identification. By raising A9 to 12V ±0.5V and using address locations 1FEO to 1FFF, the additional bytes can be written to or read from in the same manner as the regular memory array. 2.7 Chip Clear All data may be cleared to 1's in a chip clear cycle by raising OE to 12 volts and bringing the WE and CE low. This procedure clears all data, except for the extra row. The 28C64A is placed in the standby mode by applying a high signal to the CE input. When in the standby mode, the outputs are in a high impedance state, independent of the OE input. 2.3 Data Protection In order to ensure data integrity, especially during critical power-up and power-down transitions, the following enhanced data protection circuits are incorporated: First, an internal VCC detect (3.3 volts typical) will inhibit the initiation of non-volatile programming operation when VCC is less than the VCC detect circuit trip. Second, there is a WE filtering circuit that prevents WE pulses of less than 10 ns duration from initiating a write cycle. Third, holding WE or CE high or OE low, inhibits a write cycle during power-on and power-off (VCC). DS11109J-page 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 1998 Microchip Technology Inc. 28C64A 28C64A Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 28C64A F T – 15 I /P Package: Temperature Range: Access Time: L = Plastic Leaded Chip Carrier (PLCC) P = Plastic DIP (600 mil) SO = Plastic Small Outline IC (600 mil) Blank = 0°C to +70°C I = -40°C to +85°C 15 20 25 150 ns 200 ns 250 ns Shipping: Blank T Option: Blank = twc = 1ms F = twc = 200 µs Device: 1998 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 28C64A Tube Tape and Reel “L” and “SO” 8K x 8 CMOS EEPROM DS11109J-page 7 WORLDWIDE SALES AND SERVICE AMERICAS AMERICAS (continued) Corporate Office Toronto Singapore Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850 Atlanta Microchip Asia Pacific Unit 2101, Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas Microchip Technology Inc. 4570 Westgrove Drive, Suite 160 Addison, TX 75248 Tel: 972-818-7423 Fax: 972-818-2924 Dayton Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 Detroit Microchip Technology Inc. Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 New York Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 ASIA/PACIFIC Hong Kong ASIA/PACIFIC (continued) Taiwan, R.O.C Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE Beijing United Kingdom Microchip Technology, Beijing Unit 915, 6 Chaoyangmen Bei Dajie Dong Erhuan Road, Dongcheng District New China Hong Kong Manhattan Building Beijing 100027 PRC Tel: 86-10-85282100 Fax: 86-10-85282104 Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5858 Fax: 44-118 921-5835 India Denmark Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062 Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 Japan France Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Arizona Microchip Technology SARL Parc d’Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Korea Germany Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 München, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Shanghai Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan’an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Italy 11/15/99 Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. 1999 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003