MAXIM MAX2063ETM+

19-5303; Rev 0; 6/10
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
Features
The MAX2063 high-linearity, dual digital variable-gain
amplifier (VGA) operates in the 50MHz to 1000MHz
frequency range. Each digital attenuator is controlled
as a slave peripheral using either the SPIK-compatible
interface or a 5-bit parallel bus with 31dB total adjustment range in 1dB steps. An added feature allows
“rapid-fire” gain selection between each of four steps,
preprogrammed by the user through the SPI-compatible
interface. A separate 2-pin control allows the user to
quickly access any one of four customized attenuation
states without reprogramming the SPI bus.
S Independently Controlled Dual Paths
Since each of the stages has its own external RF input
and RF output, this component can be configured
to either optimize noise figure (amplifier configured
first) or OIP3 (amplifier configured last). The device’s
performance features include 24dB of amplifier gain
(amplifier only), 5.6dB noise figure (NF) at maximum
gain (including attenuator insertion losses), and a high
OIP3 level of +41dBm. Each of these features makes the
device an ideal VGA for multipath receiver and transmitter
applications.
S Supports Four “Rapid-Fire” Preprogrammed
Attenuator States
Quickly Access Any One of Four Customized Attenuation States Without Reprogramming the
SPI Bus
Ideal for Fast-Attack, High-Level Blocker
Protection
Prevents ADC Overdrive Condition
In addition, the device operates from a single +5V
supply with full performance, or a +3.3V supply for an
enhanced power-savings mode with lower performance.
This device is available in a compact 48-pin thin QFN
package (7mm x 7mm) with an exposed pad. Electrical
performance is guaranteed over the extended temperature range, from TC = -40NC to +85NC.
Applications
S 50MHz to 1000MHz RF Frequency Range
S Pin-Compatible Family Includes
MAX2062 (Analog/Digital VGA)
MAX2064 (Analog-Only VGA)
S 21.3dB (typ) Maximum Gain
S 0.25dB Gain Flatness Over 100MHz Bandwidth
S 31dB Gain Range
S 58dB Path Isolation at 200MHz
S Excellent Linearity at 200MHz
+41dBm OIP3
+56dBm OIP2
+19dBm Output 1dB Compression Point
S 5.6dB Typical Noise Figure
S 25ns Digital Switching Time
S Very Low Distortion VGA Amplitude Overshoot/
Undershoot of 0.05dB
S Single +5V Supply (or +3.3V Operation)
S Amplifier Power-Down Mode for TDD Applications
IF and RF Gain Stages
Temperature-Compensation Circuits
Cellular Band WCDMA and cdma2000M Base
Stations
GSM 850/GSM 900 EDGE Base Stations
WiMAXK and LTE Base Stations and Customer
Premise Equipment
Fixed Broadband Wireless Access
Wireless Local Loop
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX2063ETM+
PART
-40NC to +85NC
48 Thin QFN-EP*
MAX2063ETM+T
-40NC to +85NC
48 Thin QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
Military Systems
SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of Telecommunications
Industry Association.
WiMAX is a trademark of WiMAX Forum.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX2063
General Description
MAX2063
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
ABSOLUTE MAXIMUM RATINGS
VCC_AMP_1, VCC_AMP_2, VCC_RG to GND...........-0.3V
STA_A_1, STA_A_2, STA_B_1, STA_B_2, PD_1,
PD_2, AMPSET .................................................-0.3V
DAT, CS, CLK, DA_SP..........................................-0.3V
D0_1, D1_1, D2_1, D3_1, D4_1, D0_2, D1_2,
D2_2, D3_2, D4_2 . ...........................................-0.3V
AMP_IN_1, AMP_IN_2........................................+0.95V
AMP_OUT_1, AMP_OUT_2...................................-0.3V
D_ATT_IN_1, D_ATT_IN_2, D_ATT_OUT_1,
D_ATT_OUT_2 . .................................................... 0V
REG_OUT..............................................................-0.3V
to +5.5V
to +3.6V
to +3.6V
to +3.6V
to +1.2V
to +5.5V
to +3.6V
to +3.6V
RF Input Power (D_ATT_IN_1, D_ATT_IN_2)................ +20dBm
RF Input Power (AMP_IN_1, AMP_IN_2)....................... +18dBm
qJC (Notes 1, 2).......................................................... +12.3NC/W
qJA (Notes 2, 3)............................................................. +38NC/W
Continuous Power Dissipation (Note 1)...............................5.3W
Operating Case Temperature Range (Note 4)... -40NC to +85NC
Junction Temperature......................................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Note 1: Based on junction temperature TJ = TC + (BJC x VCC x ICC). This formula can be used when the temperature of the
exposed pad is known while the device is soldered down to a PCB. See the Applications Information section for details.
The junction temperature must not exceed +150NC.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Note 3: Junction temperature TJ = TA + (BJA x VCC x ICC). This formula can be used when the ambient temperature of the PCB is
known. The junction temperature must not exceed +150NC.
Note 4: TC is the temperature on the exposed pad of the package. TA is the ambient temperature of the device and PCB.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
+5V SUPPLY DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = +4.75V to +5.25V, AMPSET = 0, PD_1 = PD_2 = 0, TC =
-40NC to +85NC. Typical values are at VCC_ = +5.0V and TC = +25NC, unless otherwise noted.)
PARAMETER
Supply Voltage
Supply Current
Power-Down Current
SYMBOL
CONDITIONS
VCC
MIN
TYP
MAX
UNITS
4.75
5
5.25
V
148
205
mA
5.2
8
mA
0.5
V
IDC
IDCPD
PD_1 = PD_2 = 1, VIH = 3.3V
Input Low Voltage
VIL
Input High Voltage
VIH
1.7
3.465
V
Input Logic Current
IIH, IIL
-1
+1
FA
+3.3V SUPPLY DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = +3.135V to +3.465V, AMPSET = 1, PD_1 = PD_2 = 0, TC
= -40NC to +85NC. Typical values are at VCC_ = +3.3V and TC = +25NC, unless otherwise noted.)
PARAMETER
SYMBOL
Supply Voltage
VCC
Supply Current
IDC
Power-Down Current
IDCPD
Input Low Voltage
VIL
Input High Voltage
VIH
2
CONDITIONS
MIN
TYP
MAX
3.135
3.3
3.465
V
88
145
mA
PD_1 = PD_2 = 1, VIH = 3.3V
4.3
1.7
UNITS
8
mA
0.5
V
3.465
V
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
PARAMETER
RF Frequency
SYMBOL
fRF
CONDITIONS
MIN
(Note 5)
TYP
50
MAX
UNITS
1000
MHz
+5V SUPPLY AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = +4.75V to +5.25V, attenuators are set for maximum gain,
RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz ≤ fRF ≤ 500MHz, TC = -40NC to +85NC. Typical
values are at maximum gain setting, VCC_ = +5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6)
PARAMETER
Small-Signal Gain
SYMBOL
G
CONDITIONS
fRF = 100MHz
21.7
fRF = 200MHz
21.3
fRF = 350MHz, TC = +25NC
21.0
20.8
fRF = 750MHz
19.9
fRF = 900MHz
18.3
NF
From 100MHz to 200MHz
0.35
Any 100MHz frequency band from
200MHz to 500MHz
0.25
fRF = 50MHz
5.2
fRF = 100MHz
5.4
fRF = 200MHz
5.6
fRF = 350MHz
5.8
fRF = 450MHz
5.9
fRF = 750MHz
6.4
fRF = 900MHz
Total Attenuation Range
Path Isolation
18
fRF = 450MHz
-0.006
Gain Flatness vs. Frequency
Output Second-Order Intercept
Point (Minimum Attenuation)
TYP
22.0
Gain vs. Temperature
Noise Figure
MIN
fRF = 50MHz
OIP2
MAX
UNITS
23
dB
dB/NC
dB
dB
6.7
30.8
dB
POUT = 0dBm/tone, Df = 1MHz, f1 + f2
51.6
dBm
RF input 1 amplified power measured at
RF output 2 relative to RF output 1, all
unused ports terminated to 50I
48.8
RF input 2 amplified power measured at
RF output 1 relative to RF output 2, all
unused ports terminated to 50I
49.4
dB
3
MAX2063
RECOMMENDED AC OPERATING CONDITIONS
MAX2063
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
+5V SUPPLY AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = +4.75V to +5.25V, attenuators are set for maximum gain,
RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz ≤ fRF ≤ 500MHz, TC = -40NC to +85NC. Typical
values are at maximum gain setting, VCC_ = +5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6)
PARAMETER
Output Third-Order Intercept
Point
SYMBOL
OIP3
CONDITIONS
MIN
TYP
POUT = 0dBm/tone,
Df = 1MHz, fRF = 50MHz
47.1
POUT = 0dBm/tone,
Df = 1MHz, fRF = 100MHz
43.9
POUT = 0dBm/tone,
Df = 1MHz, fRF = 200MHz
41.0
POUT = 0dBm/tone,
Df = 1MHz, fRF = 350MHz
37.0
POUT = 0dBm/tone,
Df = 1MHz, fRF = 450MHz
35.2
POUT = 0dBm/tone,
Df = 1MHz, fRF = 750MHz
28.7
POUT = 0dBm/tone,
Df = 1MHz, fRF = 900MHz
26.5
MAX
UNITS
dBm
Output -1dB Compression Point
P1dB
(Note 7)
18.8
dBm
Second Harmonic
HD2
POUT = +3dBm
-54.8
dBc
Third Harmonic
HD3
POUT = +3dBm
-72.9
dBc
Group Delay
Includes EV kit PCB delays
0.87
ns
Amplifier Power-Down Time
PD_1 or PD_2 from 0 to 1, amplifier DC
supply current settles to within 0.1mA
0.5
Fs
Amplifier Power-Up Time
PD_1 or PD_2 from 1 to 0, amplifier DC
supply current settles to within 1%
0.5
Fs
50I source
23.3
dB
50I load
24.4
dB
3.0
dB
Input Return Loss
Output Return Loss
RLIN
RLOUT
DIGITAL ATTENUATOR (each path, unless otherwise noted)
Insertion Loss
IL
Input Second-Order Intercept
Point
IIP2
PRF1 = 0dBm PRF2 = 0dBm (minimum
attenuation), Df = 1MHz, f1 + f2
53.1
dBm
Input Third-Order Intercept
Point
IIP3
PIN1 = 0dBm PIN2 = 0dBm (minimum
attenuation), Df = 1MHz
43.2
dBm
30.8
dB
1
dB
Relative Attenuation Accuracy
0.11
dB
Absolute Attenuation Accuracy
0.23
dB
Attenuation Range
Step Size
Insertion Phase Step
4
fRF = 170MHz
0dB to 16dB
-0.4
0dB to 24dB
0.6
0dB to 31dB
0.9
Degrees
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = +4.75V to +5.25V, attenuators are set for maximum gain,
RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz ≤ fRF ≤ 500MHz, TC = -40NC to +85NC. Typical
values are at maximum gain setting, VCC_ = +5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Amplitude Overshoot/
Undershoot
Between any
two states
Elapsed time = 15ns
1.0
Elapsed time = 40ns
0.05
Switching Speed
RF settled to
within Q0.1dB
31dB to 0dB
25
0dB to 31dB
21
Input Return Loss
Output Return Loss
RLIN
RLOUT
MAX
UNITS
dB
ns
50I source
21.6
dB
50I load
21.2
dB
SERIAL PERIPHERAL INTERFACE (SPI)
Maximum Clock Speed
fCLK
20
MHz
Data-to-Clock Setup Time
tCS
2
ns
Data-to-Clock Hold Time
tCH
2.5
ns
Clock-to-CS Setup Time
tES
3
ns
CS Positive Pulse Width
tEW
7
ns
CS Setup Time
tEWS
3.5
ns
Clock Pulse Width
tCW
5
ns
+3.3V SUPPLY AC ELECTRICAL CHARACTERISTIC
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = +3.3V, attenuators are set for maximum gain, RF ports
are driven from 50I sources, AMPSET = 1, PD_1 = PD_2 = 0, 100MHz ≤ fRF ≤ 500MHz, TC = -40NC to +85NC. Typical values are at
maximum gain setting, VCC_ = +3.3V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6)
PARAMETER
Small-Signal Gain
Output Third-Order Intercept
Point
Noise Figure
SYMBOL
CONDITIONS
G
OIP3
POUT = 0dBm/tone
NF
Total Attenuation Range
Path Isolation
Output -1dB Compression Point
P1dB
MIN
TYP
MAX
UNITS
20.9
dB
29.6
dBm
5.9
dB
30.8
dB
RF input 1 amplified power measured at
RF output 2 relative to RF output 1, all
unused ports terminated to 50I
48.8
RF input 2 amplified power measured at
RF output 1 relative to RF output 2, all
unused ports terminated to 50I
49.1
(Note 7)
13.4
dB
dBm
Note 5: Operation outside this range is possible, but with degraded performance of some parameters. See the Typical Operating
Characteristics.
Note 6: All limits include external component losses. Output measurements are performed at the RF output port of the Typical
Application Circuit.
Note 7: It is advisable not to continuously operate RF input 1 or RF input 2 above +15dBm.
5
MAX2063
+5V SUPPLY AC ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5V, attenuators are set for maximimum gain, RF ports are
driven from 50ω sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. VCC
GAIN vs. RF FREQUENCY
22
140
22
GAIN (dB)
TC = +25°C
150
MAX2063 toc03
24
MAX2063 toc02
TC = -40°C
160
GAIN (dB)
SUPPLY CURRENT (mA)
TC = -40°C
GAIN vs. RF FREQUENCY
24
MAX2063 toc01
170
20
TC = +85°C
TC = +25°C
VCC = 4.75V, 5.00V, 5.25V
20
18
18
TC = +85°C
130
4.750
4.875
5.000
5.125
16
5.250
16
50
450
650
850
1050
450
650
850
RF FREQUENCY (MHz)
GAIN OVER ATTENUATOR SETTING
vs. RF FREQUENCY
ATTENUATOR RELATIVE
ERROR vs. RF FREQUENCY
ATTENUATOR ABSOLUTE
ERROR vs. RF FREQUENCY
0.25
0
-0.25
-0.50
250
450
650
850
0.75
ABSOLUTE ERROR (dB)
RELATIVE ERROR (dB)
-5
0.50
ERROR FROM 23dB TO 24dB
250
450
650
850
1050
25dB
24dB
50
250
1dB
4dB
-40
31dB
-50
400
600
RF FREQUENCY (MHz)
800
1000
650
850
0
MAX2063 toc08
OUTPUT MATCH OVER ATTENUATOR SETTING (dB)
-20
2dB
450
RF FREQUENCY (MHz)
OUTPUT MATCH OVER ATTENUATOR
SETTING vs. RF FREQUENCY
MAX2063 toc07
INPUT MATCH OVER ATTENUATOR SETTING (dB)
-0.50
-1.00
50
0dB
8dB
200
-0.25
RF FREQUENCY (MHz)
16dB
0
0
-1.00
1050
0
-30
0.25
-0.75
INPUT MATCH OVER ATTENUATOR
SETTING vs. RF FREQUENCY
-10
0.50
-0.75
RF FREQUENCY (MHz)
-10
16dB, 31dB
2dB
-20
1dB, 4dB, 8dB
-30
0dB
-40
0
1050
MAX2063 toc06
0.75
5
1.00
MAX2063 toc05
MAX2063 toc04
1.00
-15
6
250
50
RF FREQUENCY (MHz)
15
50
250
VCC (V)
25
GAIN OVER ATTENUATOR SETTING (dB)
MAX2063
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
200
400
600
RF FREQUENCY (MHz)
800
1000
1050
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
ATTEN 31dB
-60
-70
-80
450
650
850
1050
40
30
20
10
0
-10
65
55
45
35
25
-30
50
250
450
650
850
50
1050
CH1 TO CH2
35
7
6
5
4
25
8
6
450
650
850
1050
4
TC = -40°C
3
50
RF FREQUENCY (MHz)
250
450
650
850
1050
650
850
1050
OUTPUT P1dB vs. RF FREQUENCY
MAX2063 toc15
TC = -40°C
450
22
18
TC = +85°C
16
VCC = 5.25V
20
OUTPUT P1dB (dBm)
OUTPUT P1dB (dBm)
250
RF FREQUENCY (MHz)
OUTPUT P1dB vs. RF FREQUENCY
14
50
RF FREQUENCY (MHz)
22
20
VCC = 4.75V, 5.00V, 5.25V
5
3
250
1050
7
TC = +25°C
CH2 TO CH1
850
9
NOISE FIGURE (dB)
55
TC = +85°C
8
650
NOISE FIGURE vs. RF FREQUENCY
NOISE FIGURE vs. RF FREQUENCY
NOISE FIGURE (dB)
65
450
RF FREQUENCY (MHz)
9
MAX2063 toc12
RELATIVE POWERS AT RF OUTPUTS
50
250
RF FREQUENCY (MHz)
75
CH2 TO CH1
CH1 TO CH2
-20
CHANNEL ISOLATION vs. RF FREQUENCY
(MINIMUM GAIN)
CHANNEL ISOLATION (dB)
RELATIVE POWERS AT RF OUTPUTS
MAX2063 toc11
POSITIVE PHASE = ELECTRICALLY SHORTER
RF FREQUENCY (MHz)
45
75
MAX2063 toc14
250
REFERENCED TO HIGH GAIN STATE
MAX2063 toc16
50
50
CHANNEL ISOLATION (dB)
-50
60
CHANNEL ISOLATION vs. RF FREQUENCY
(MAXIMUM GAIN)
MAX2063 toc10
ATTEN 0dB
ATTENUATOR PHASE CHANGE
BETWEEN STATES vs. RF FREQUENCY
MAX2063 toc13
-40
ATTENUATOR PHASE CHANGE BETWEEN STATES (DEGREES)
-30
MAX2063 toc09
REVERSE GAIN OVER ATTENUATOR SETTING (dB)
REVERSE GAIN OVER ATTENUATOR
SETTING vs. RF FREQUENCY
18
VCC = 4.75V
VCC = 5.00V
16
14
TC = +25°C
12
12
50
250
450
650
RF FREQUENCY (MHz)
850
1050
50
250
450
650
850
1050
RF FREQUENCY (MHz)
7
MAX2063
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5V, attenuators are set for maximimum gain, RF ports are
driven from 50ω sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5V, attenuators are set for maximimum gain, RF ports are
driven from 50ω sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25°C, unless otherwise noted.)
TC = +85°C
25
35
VCC = 4.75V
30
650
850
1050
250
RF FREQUENCY (MHz)
650
850
0
1050
50
TC = -40°C
POUT = 3dBm
VCC = 5.25V
2ND HARMONIC (dBc)
TC = +85°C
40
VCC = 5.00V
50
VCC = 4.75V
850
1050
3RD HARMONIC vs. RF FREQUENCY
250
50
650
850
TC = -40°C
0
1050
TC = +25°C
70
TC = +85°C
POUT = 3dBm
90
3RD HARMONIC (dBc)
TC = -40°C
80
MAX2063 toc19
TC = +25°C
4
VCC = 5.25V
12
16
20
24
28
3RD HARMONIC vs. ATTENUATOR STATE
VCC = 5.00V
80
8
ATTENUATOR STATE (dB)
3RD HARMONIC vs. RF FREQUENCY
60
80
70
VCC = 4.75V
POUT = 3dBm
RF = 350MHz
TC = -40°C
75
TC = +25°C
TC = +85°C
70
60
50
65
50
50
250
450
650
RF FREQUENCY (MHz)
8
450
100
MAX2063 toc23
90
POUT = 3dBm
RF = 350MHz
55
RF FREQUENCY (MHz)
POUT = 3dBm
28
40
50
RF FREQUENCY (MHz)
100
24
45
3RD HARMONIC (dBc)
650
20
60
MAX2063 toc24
450
16
TC = +85°C
30
250
12
65
TC = +25°C
30
8
2ND HARMONIC vs. ATTENUATOR STATE
60
40
50
4
ATTENUATOR STATE (dB)
2ND HARMONIC vs. RF FREQUENCY
70
MAX2063 toc20
POUT = 3dBm
60
450
RF FREQUENCY (MHz)
2ND HARMONIC vs. RF FREQUENCY
70
TC = +25°C, LSB, USB
30
50
2ND HARMONIC (dBc)
450
MAX2063 toc21
250
35
TC = +85°C, LSB, USB
20
50
40
25
20
2ND HARMONIC (dBc)
TC = -40°C, LSB, USB
MAX2063 toc22
30
VCC = 5.25V
POUT = 0dBm/TONE
RF = 350MHz
MAX2063 toc25
TC = +25°C
35
40
45
OUTPUT IP3 (dBm)
TC = -40°C
POUT = 0dBm/TONE
VCC = 5.00V
45
OUTPUT IP3 (dBm)
OUTPUT IP3 (dBm)
MAX2063 toc17
POUT = 0dBm/TONE
45
40
OUTPUT IP3 vs. ATTENUATOR STATE
OUTPUT IP3 vs. RF FREQUENCY
50
MAX2063 toc18
OUTPUT IP3 vs. RF FREQUENCY
50
3RD HARMONIC (dBc)
MAX2063
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
850
1050
50
250
450
650
RF FREQUENCY (MHz)
850
1050
0
4
8
12
16
20
ATTENUATOR STATE (dB)
24
28
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
OUTPUT IP2 (dBm)
TC = +25°C
40
TC = -40°C
30
TC = +85°C
55
VCC = 5.00V
50
VCC = 4.75V
40
250
450
650
850
1050
250
50
RF FREQUENCY (MHz)
450
650
850
4
8
16
20
24
28
0
-1
GAIN (dB)
TC = -40°C
TC = +25°C
-3
MAX2063 toc30
-1
12
ATTENUATOR STATE (dB)
GAIN vs. RF FREQUENCY
(ATTENUATOR ONLY)
MAX2063 toc29
0
-4
0
1050
RF FREQUENCY (MHz)
GAIN vs. RF FREQUENCY
(ATTENUATOR ONLY)
-2
TC = -40°C TC = +25°C
40
20
50
50
45
30
20
POUT = 0dBm/TONE
RF = 350MHz
MAX2063 toc28
60
50
GAIN (dB)
OUTPUT IP2 (dBm)
60
POUT = 0dBm/TONE
VCC = 5.25V
60
OUTPUT IP2 (dBm)
POUT = 0dBm/TONE
MAX2063 toc26
TC = +85°C
OUTPUT IP2 vs. ATTENUATOR STATE
OUTPUT IP2 vs. RF FREQUENCY
70
MAX2063 toc27
OUTPUT IP2 vs. RF FREQUENCY
70
-2
-3
VCC = 4.75V, 5.00V, 5.25V
-4
TC = +85°C
-5
-5
50
250
450
650
RF FREQUENCY (MHz)
850
1050
50
250
450
650
850
1050
RF FREQUENCY (MHz)
9
MAX2063
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5V, attenuators are set for maximimum gain, RF ports are
driven from 50ω sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25°C, unless otherwise noted.)
Typical Operating Characteristics
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.3V, attenuators are set for maximimum gain, RF ports are
driven from 50ω sources, AMPSET = 1, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25°C, unless otherwise noted.)
VCC = 3.3V
TC = -40°C
22
GAIN (dB)
90
20
TC = +85°C
80
18
70
VCC = 3.3V
20
VCC = 3.135V
18
TC = +85°C
3.2
3.3
3.4
16
3.5
16
250
50
VCC (V)
450
650
850
1050
8dB
0dB
-20
-30
2dB
4dB
1dB
-40
31dB
-50
50
250
450
650
850
OUTPUT MATCH OVER ATTENUATOR SETTING (dB)
VCC = 3.3V
16dB
0
VCC = 3.3V
-10
16dB, 31dB
1dB
2dB
-20
-30
8dB
4dB
0dB
-40
50
1050
250
NOISE FIGURE vs. RF FREQUENCY
MAX2063 toc36
7
6
TC = +25°C
4
850
9
8
VCC = 3.135V
NOISE FIGURE (dB)
NOISE FIGURE (dB)
TC = +85°C
5
650
1050
NOISE FIGURE vs. RF FREQUENCY
VCC = 3.3V
8
450
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
9
650
OUTPUT MATCH OVER ATTENUATOR
SETTING vs. RF FREQUENCY
MAX2063 toc34
INPUT MATCH OVER ATTENUATOR SETTING (dB)
0
450
RF FREQUENCY (MHz)
INPUT MATCH OVER ATTENUATOR
SETTING vs. RF FREQUENCY
-10
250
50
RF FREQUENCY (MHz)
MAX2063 toc37
3.1
MAX2063 toc35
60
7
6
VCC = 3.3V
5
VCC = 3.465V
4
TC = -40°C
3
3
2
50
250
450
650
RF FREQUENCY (MHz)
10
VCC = 3.465V
22
TC = +25°C
GAIN (dB)
TC = +25°C
100
GAIN vs. RF FREQUENCY
24
MAX2063 toc32
MAX2063 toc31
TC = -40°C
110
GAIN vs. RF FREQUENCY
24
MAX2063 toc33
SUPPLY CURRENT vs. VCC
120
SUPPLY CURRENT (mA)
MAX2063
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
850
1050
2
50
250
450
650
RF FREQUENCY (MHz)
850
1050
850
1050
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
14
VCC = 3.465V
10
450
650
850
10
6
1050
250
50
RF FREQUENCY (MHz)
450
MAX2063 toc41
34
TC = -40°C LSB, USB
32
OUTPUT IP3 (dBm)
40
VCC = 3.465V
VCC = 3.3V
VCC = 3.135V
VCC = 3.3V
POUT = 0dBm/TONE
RF = 350MHz
450
650
850
26
8
12
16
20
24
50
28
250
450
650
850
1050
RF FREQUENCY (MHz)
2ND HARMONIC vs. ATTENUATOR STATE
80
MAX9888 toc44
VCC = 3.465V
50
VCC = 3.3V
40
VCC = 3.3V
POUT = 3dBm
RF = 350MHz
70
2ND HARMONIC (dBc)
70
TC = +85°C
40
ATTENUATOR STATE (dB)
POUT = 3dBm
30
TC = +25°C
50
TC = -40°C
2ND HARMONIC vs. RF FREQUENCY
60
60
20
4
RF FREQUENCY (MHz)
80
1050
30
0
1050
VCC = 3.3V
POUT = 3dBm
70
22
250
850
2ND HARMONIC vs. RF FREQUENCY
TC = +85°C LSB, USB
10
650
80
TC = +25°C LSB, USB
28
450
RF FREQUENCY (MHz)
24
50
250
50
1050
30
20
2ND HARMONIC (dBc)
OUTPUT IP3 (dBm)
850
OUTPUT IP3 vs. ATTENUATOR STATE
POUT = 0dBm/TONE
30
650
RF FREQUENCY (MHz)
OUTPUT IP3 vs. RF FREQUENCY
50
TC = +25°C
TC = +85°C
2ND HARMONIC (dBc)
250
30
VCC = 3.135V
MAX2063 toc42
50
TC = -40°C
20
8
6
40
MAX9888 toc43
8
12
POUT = 0dBm/TONE
VCC = 3.3V
MAX2063 toc45
TC = +85°C
10
VCC = 3.3V
OUTPUT IP3 (dBm)
12
50
MAX2063 toc39
TC = -40°C
OUTPUT P1dB (dBm)
OUTPUT P1dB (dBm)
14
MAX2063 toc38
VCC = 3.3V
TC = +25°C
OUTPUT IP3 vs. RF FREQUENCY
OUTPUT P1dB vs. RF FREQUENCY
16
MAX2063 toc40
OUTPUT P1dB vs. RF FREQUENCY
16
TC = +85°C
60
TC = +25°C
50
40
VCC = 3.135V
TC = -40°C
20
50
250
450
650
RF FREQUENCY (MHz)
850
1050
30
0
4
8
12
16
20
24
28
ATTENUATOR STATE (dB)
11
MAX2063
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.3V, attenuators are set for maximimum gain, RF ports are
driven from 50ω sources, AMPSET = 1, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.3V, attenuators are set for maximimum gain, RF ports are
driven from 50ω sources, AMPSET = 1, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, TC = +25°C, unless otherwise noted.)
3RD HARMONIC vs. RF FREQUENCY
MAX2063 toc46
VCC = 3.3V
POUT = 3dBm
TC = -40°C
TC = +25°C
60
50
40
250
VCC = 3.465V
VCC = 3.135V
60
VCC = 3.3V
50
TC = +85°C
50
70
450
650
850
40
1050
250
50
RF FREQUENCY (MHz)
MAX2063 toc48
70
TC = +85°C
850
1050
60
TC = +25°C
VCC = 3.3V
POUT = 0dBm/TONE
60
OUTPUT IP2 (dBm)
55
50
40
TC = +25°C
30
TC = -40°C
TC = +85°C
20
50
0
4
8
12
16
20
24
250
50
28
60
70
MAX2063 toc50
POUT = 0dBm/TONE
850
1050
OUTPUT IP2 (dBm)
VCC = 3.3V
40
RF = 350MHZ
VCC = 3.3V
POUT = 0dBm/TONE
60
VCC = 3.465V
50
650
OUTPUT IP2 vs. ATTENUATOR STATE
OUTPUT IP2 vs. RF FREQUENCY
70
450
RF FREQUENCY (MHz)
ATTENUATOR STATE (dB)
MAX2063 toc51
3RD HARMONIC (dBc)
VCC = 3.3V
POUT = 3dBm
RF = 350MHz
TC = -40°C
65
650
OUTPUT IP2 vs. RF FREQUENCY
3RD HARMONIC vs. ATTENUATOR STATE
70
450
RF FREQUENCY (MHz)
MAX2063 toc49
70
POUT = 3dBm
MAX2063 toc47
3RD HARMONIC vs. RF FREQUENCY
80
3RD HARMONIC (dBc)
3RD HARMONIC (dBc)
80
OUTPUT IP2 (dBm)
MAX2063
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
TC = +85°C
50
TC = -40°C
TC = +25°C
40
30
VCC = 3.135V
30
20
50
250
450
650
RF FREQUENCY (MHz)
12
850
1050
0
4
8
12
16
20
ATTENUATOR STATE (dB)
24
28
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
GND
AMP_IN_2
PD_2
GND
AMP_OUT_2
REG_OUT
AMPSET
AMP_OUT_1
GND
PD_1
AMP_IN_1
GND
TOP VIEW
36 35 34 33 32 31 30 29 28 27 26 25
VCC_AMP_1
37
GND
38
GND
39
GND
40
GND
41
D4_1
42
24
ACTIVE
BIAS
AMP
ACTIVE
BIAS
AMP
EXPOSED
PAD
MAX2063
VCC_AMP_2
23
GND
22
GND
21
DA_SP
20
GND
19
D4_2
18
D_ATT_OUT_2
D_ATT_OUT_1
43
D3_1
44
17
D3_2
D2_1
45
16
D2_2
15
D1_2
14
D0_2
13
GND
7
8
9
10 11 12
GND
6
D_ATT_IN_2
5
STA_A_2
4
VCC_RG
3
STA_B_2
2
CS
1
CLK
+
DIGITAL
ATTENUATOR
2
SPI
DAT
48
STA_B_1
47
GND
STA_A_1
D0_1
D_ATT_IN_1
46
GND
D1_1
DIGITAL
ATTENUATOR
1
THIN QFN
(7mm O 7mm)
Pin Description
PIN
NAME
FUNCTION
1, 12, 13, 20,
22, 23, 25,
28, 33, 36,
38–41, 48
GND
2
D_ATT_IN_1
3
STA_A_1
4
STA_B_1
5
DAT
SPI Data Digital Input
6
CLK
SPI Clock Digital Input
7
CS
Ground
5-Bit Digital Attenuator RF Input (50I), Path 1. Requires a DC-blocking capacitor.
Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 1
State A
State B
Digital Attenuator 1
Logic = 0
Logic = 0
Preprogrammed State 1
Logic = 1
Logic = 0
Preprogrammed State 2
Logic = 0
Logic = 1
Preprogrammed State 3
Logic = 1
Logic = 1
Preprogrammed State 4
SPI Chip-Select Digital Input
13
MAX2063
Pin Configuration
MAX2063
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
Pin Description (continued)
PIN
14
NAME
8
VCC_RG
9
STA_B_2
10
STA_A_2
FUNCTION
Regulator Supply Input. Connect to a 3.3V or 5V external power supply. VCC_RG powers all
circuits except for the driver amplifiers. Bypass with a 10nF capacitor as close as possible to
the pin.
Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 2
State A
State B
Digital Attenuator 2
Logic = 0
Logic = 0
Preprogrammed State 1
Logic = 1
Logic = 0
Preprogrammed State 2
Logic = 0
Logic = 1
Preprogrammed State 3
Logic = 1
Logic = 1
Preprogrammed State 4
11
D_ATT_IN_2
14
D0_2
1dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
5-Bit Digital Attenuator Input (50I), Path 2. Requires a DC-blocking capacitor.
15
D1_2
2dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
16
D2_2
4dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
17
D3_2
8dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
18
D_ATT_OUT_2
19
D4_2
21
DA_SP
24
VCC_AMP_2
Driver Amplifier Supply Voltage Input, Path 2. Bypass with a 10nF capacitor as close as
possible to the pin.
26
AMP_IN_2
Driver Amplifier Input (50I), Path 2. Connect to D_ATT_OUT_2 through a 1000pF capacitor.
27
PD_2
29
AMP_OUT_2
30
REG_OUT
31
AMPSET
32
AMP_OUT_1
5-Bit Digital Attenuator Output (50I), Path 2. Requires a DC-blocking capacitor. Connect to
AMP_IN_2 through a 1000pF capacitor.
16dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable.
Digital Attenuator Serial/Parallel Control Select. Set DA_SP to 1 to select serial control. Set
DA_SP to 0 to select parallel control.
Power-Down, Path 2. See Table 2 for operation details.
Driver Amplifier Output (50I), Path 2. Connect a pullup inductor from AMP_OUT_2 to VCC_.
Regulator Output. Bypass with a 1FF capacitor.
Driver Amplifier Bias Setting for 3.3V Operation. Set to logic 1 for 3.3V on pins VCC_AMP1 and
VCC_AMP2. Set to logic 0 for 5V.
Driver Amplifier Output (50I), Path 1. Connect a pullup inductor from AMP_OUT_1 to VCC_.
34
PD_1
35
AMP_IN_1
Power-Down, Path 1. See Table 2 for operation details.
Driver Amplifier Input (50I), Path 1. Connect to D_ATT_OUT_1 through a 1000pF capacitor.
37
VCC_AMP_1
Driver Amplifier Supply Voltage Input, Path 1. Bypass with a 10nF capacitor as close as
possible to the pin.
42
D4_1
43
D_ATT_OUT_1
44
D3_1
8dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
45
D2_1
4dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
46
D1_1
2dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
47
D0_1
1dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
—
EP
16dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable, path 1.
5-Bit Digital Attenuator Output (50I), Path 1. Requires a DC-blocking capacitor. Connect to
AMP_IN_1 through a 1000pF capacitor.
Exposed Pad. Internally connected to GND. Connect to a large PCB ground plane for proper
RF performance and enhanced thermal dissipation.
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
The MAX2063 high-linearity digital VGA is a generalpurpose, high-performance amplifier designed to
interface with 50I systems operating in the 50MHz to
1000MHz frequency range. Each channel of the device
integrates one digital attenuator to provide 31dB of total
gain control, as well as a driver amplifier optimized to
provide high gain, high output IP3, low NF, and low
power consumption.
Each digital attenuator is controlled as a slave
peripheral using either the SPI-compatible interface or
a 5-bit parallel bus with 31dB total adjustment range
in 1dB steps. An added feature allows “rapid-fire” gain
selection between each of four steps, preprogrammed
by the user through the SPI-compatible interface. A
separate 2-pin control allows the user to quickly access
any one of four customized attenuation states without
reprogramming the SPI bus.
Because each of the two stages in the separate
signal paths has its own RF input and RF output, this
component can be configured to either optimize NF
(amplifier configured first) or OIP3 (amplifier configured
last). The device’s performance features include 24dB
of amplifier gain (amplifier only), 5.6dB NF at maximum
gain (includes attenuator insertion losses), and a high
OIP3 level of +41dBm. Each of these features makes
the device an ideal VGA for multipath receiver and
transmitter applications.
5-Bit Digital Attenuator Control
The device integrates two 5-bit digital attenuators to
achieve a high level of dynamic range. Each digital
attenuator has a 31dB control range, a 1dB step size,
and can be programmed either through a dedicated
5-bit parallel bus or through the 3-wire SPI. See the
Applications Information section and Table 1 for attenuator programming details. The attenuators can be used
for both static and dynamic power control.
Table 1. Control Logic
DA_SP
DIGITAL ATTENUATOR
0
Parallel controlled
1
SPI controlled (control voltages show up on the
parallel control pins)
Table 2. Operating Modes
RESULT
All on
AMP1 off
AMP2 on
AMP1 on
AMP2 off
All off
VCC_ (V)
AMPSET
PD_1
PD_2
5
0
0
0
3.3
1
0
0
5
0
1
0
3.3
1
1
0
5
0
0
1
3.3
1
0
1
5
0
1
1
3.3
1
1
1
Applications Information
Operating Modes
The device features an optional +3.3V supply voltage operation with reduced linearity performance. The AMPSET pin
needs to be biased accordingly in each mode, as listed in
Table 2. In addition, the driver amplifiers can be shut down
independently to conserve DC power. See the biasing
scheme outlined in Table 2 for details.
SPI Interface and Attenuator Settings
The attenuators can be programmed through the 3-wire
SPI/MICROWIREK-compatible serial interface using
5-bit words. Fifty-six bits of data are shifted in MSB first
and framed by CS. The first 28 bits set the first attenuator, and the following 28 bits set the second attenuator.
When CS is low, the clock is active and data is shifted on
the rising edge of the clock. When CS transitions high,
the data is latched and the attenuator setting changes
(Figure 1). See Table 3 for details on the SPI data format.
Driver Amplifiers
The device includes two high-performance drivers with
a fixed gain of 24dB. Each driver amplifier circuit is
optimized for high linearity for the 50MHz to 1000MHz
frequency range.
MICROWIRE is a trademark of National Semiconductor Corp.
15
MAX2063
Detailed Description
MAX2063
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
D0:D7
1st Digital Attenuator Programming
Reserved. Set to logic 0.
2nd Digital Attenuator Programming
D28:D35 Reserved. Set to logic 0.
D8:D12
Preprogrammed Attenuation State 1
D36:D40 Preprogrammed Attenuation State 1
D8 = 1dB bit, D9 = 2dB bit, D10 = 4dB bit,
D11 = 8dB bit, D12 = 16dB bit
D13:D17 Preprogrammed Attenuation State 2
D41:D45 Preprogrammed Attenuation State 2
D13 = 1dB bit, D14 = 2dB bit, D15 = 4dB bit,
D16 = 8dB bit, D17 = 16dB bit
D18:D22 Preprogrammed Attenuation State 3
D46:D50 Preprogrammed Attenuation State 3
D18 = 1dB bit, D19 = 2dB bit, D20 = 4dB bit,
D21 = 8dB bit, D22 = 16dB bit
D36 = 1dB bit, D37 = 2dB bit, D38 = 4dB bit,
D39 = 8dB bit, D40 = 16dB bit
D41 = 1dB bit, D42 = 2dB bit, D43 = 4dB bit,
D44 = 8dB bit, D45 = 16dB bit
D46 = 1dB bit, D47 = 2dB bit, D48 = 4dB bit,
D49 = 8dB bit, D50 = 16dB bit
D23:D27 Preprogrammed Attenuation State 4
D51:D55 Preprogrammed Attenuation State 4
D23 = 1dB bit, D24 = 2dB bit, D25 = 4dB bit,
D26 = 8dB bit, D27 = 16dB bit
D51 = 1dB bit, D52 = 2dB bit, D53 = 4dB bit,
D54 = 8dB bit, D55 = 16dB bit
MSB
DATA
LSB
DN
D(N-1)
D1
D0
CLOCK
tCW
tCS
CS
tCH
tES
tEWS
tEW
NOTES: DATA ENTERED ON CLOCK RISING EDGE.
ATTENUATOR REGISTER STATE CHANGE ON CS RISING EDGE.
N = NUMBER OF DATA BITS.
Figure 1. SPI Timing Diagram
16
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
FUNCTION
BIT
D55 (MSB)
2nd Digital Attenuator
State 4
2nd Digital Attenuator
State 3
2nd Digital Attenuator
State 2
2nd Digital Attenuator
State 1
MAX2063
Table 3. SPI Data Format
DESCRIPTION
16dB step (MSB of the 5-bit word used to program the digital attenuator state 4)
D54
8dB step
D53
4dB step
D52
2dB step
D51
1dB step
D50
16dB step (MSB of the 5-bit word used to program the digital attenuator state 3)
D49
8dB step
D48
4dB step
D47
2dB step
D46
1dB step
D45
16dB step (MSB of the 5-bit word used to program the digital attenuator state 2)
D44
8dB step
D43
4dB step
D42
2dB step
D41
1dB step
D40
16dB step (MSB of the 5-bit word used to program the digital attenuator state 1)
D39
8dB step
D38
4dB step
D37
2dB step
D36
1dB step
D35
D34
D33
Reserved
D32
D31
Bits D[35:28] are reserved. Set to logic 0.
D30
D29
D28
1st Digital Attenuator
State 4
1st Digital Attenuator
State 3
1st Digital Attenuator
State 2
D27
16dB step (MSB of the 5-bit word used to program the digital attenuator state 4)
D26
8dB step
D25
4dB step
D24
2dB step
D23
1dB step
D22
16dB step (MSB of the 5-bit word used to program the digital attenuator state 3)
D21
8dB step
D20
4dB step
D19
2dB step
D18
1dB step
D17
16dB step (MSB of the 5-bit word used to program the digital attenuator state 2)
D16
8dB step
D15
4dB step
D14
2dB step
D13
1dB step
17
MAX2063
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
Table 3. SPI Data Format (continued)
FUNCTION
BIT
1st Digital Attenuator
State 1
DESCRIPTION
D12
16dB step (MSB of the 5-bit word used to program the digital attenuator state 1)
D11
8dB step
D10
4dB step
D9
2dB step
D8
1dB step
D7
D6
D5
Reserved
D4
D3
Bits D[7:0] are reserved. Set to logic 0.
D2
D1
D0 (LSB)
Digital Attenuator Settings Using
the Parallel Control Bus
To capitalize on its fast 25ns switching capability, the
device offers a supplemental 5-bit parallel control interface for each attenuator. The two buses of the digital
logic attenuator-control pins (D0_ _–D4_ _) enable the
attenuator stages (Table 4).
Direct access to these 5-bit buses enables the user to
avoid any programming delays associated with the SPI
interface. One of the limitations of any SPI bus is the
speed at which commands can be clocked into each
peripheral device. By offering direct access to the 5-bit
parallel interface, the user can quickly shift between
digital attenuator states as needed for critical “fastattack” automatic gain-control (AGC) applications.
Note that when the digital attenuators are controlled
by the SPI bus, the control voltages of each digital
attenuator show on the five parallel control pins (pins
14–17, 19 for digital attenuator 2, and pins 42, 44–47 for
digital attenuator 1). When the digital attenuators are in
SPI mode, the parallel control pins must be open.
“Rapid-Fire” Preprogrammed
Attenuation States
The device has an added feature that provides
“rapid-fire” gain selection between four preprogrammed
attenuation steps. As with the supplemental 5-bit buses
previously mentioned, this “rapid-fire” gain selection
allows the user to quickly access any one of four
customized digital attenuation states without incurring
18
the delays associated with reprogramming the device
through the SPI bus.
The switching speed is comparable to that achieved
using the supplemental 5-bit parallel buses. However,
by employing this specific feature, the digital attenuator
I/O is further reduced by a factor of either 5 or 2.5 (5
control bits vs. 1 or 2, respectively), depending on the
number of states desired.
The user can employ the STA_A_1 and STA_B_1
(STA_A_2 and STA_B_2 for attenuator 2) logic input pins
to apply each step as required (see Tables 5 and 6).
Toggling just the STA_A_1 pin (1 control bit) yields two
preprogrammed attenuation states; toggling both the
STA_A_1 and STA_B_1 pins together (2 control bits)
yields four preprogrammed attenuation states.
As an example, assume that the AGC application
requires a static attenuation adjustment to trim out
gain inconsistencies within a receiver lineup. The same
AGC circuit can also be called upon to dynamically
attenuate an unwanted blocker signal that could desense
the receiver and lead to an ADC overdrive condition. In
this example, the device would be preprogrammed
(through the SPI bus) with two customized attenuation
states—one to address the static gain-trim adjustment,
the second to counter the unwanted blocker condition.
Toggling just the STA_A_1 control bit enables the
user to switch quickly between the static and dynamic
attenuation settings with only one I/O pin.
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
The pin configuration of the device is optimized to facilitate a very compact physical layout of the device and its
associated discrete components. The exposed pad (EP)
of the device’s 48-pin thin QFN-EP package provides a
low thermal-resistance path to the die. It is important that
the PCB on which the device is mounted be designed
to conduct heat from the EP. In addition, provide the EP
with a low inductance path to electrical ground. The EP
MUST be soldered to a ground plane on the PCB, either
directly or through an array of plated via holes.
Power-Supply Sequencing
The sequence to be used is:
Table 7 lists typical application circuit component values.
1) Power supply
2) Control lines
Table 4. Digital Attenuator Settings (Parallel Control, DA_SP = 0)
INPUT
LOGIC = 0 (OR GROUND)
LOGIC = 1
D0_ _
Disable 1dB attenuator
Enable 1dB attenuator
D1_ _
Disable 2dB attenuator
Enable 2dB attenuator
D2_ _
Disable 4dB attenuator
Enable 4dB attenuator
D3_ _
Disable 8dB attenuator
Enable 8dB attenuator
D4_ _
Disable 16dB attenuator
Enable 16dB attenuator
Table 5. Programmed Attenuation State Settings for Attenuator 1 (DA_SP = 1)
STA_A_1
STA_B_1
0
0
Preprogrammed attenuation state 1
SETTING FOR DIGITAL ATTENUATOR 1*
1
0
Preprogrammed attenuation state 2
0
1
Preprogrammed attenuation state 3
1
1
Preprogrammed attenuation state 4
*Defined by SPI programming bits D8:D27 (see Table 3 for details).
Table 6. Programmed Attenuation State Settings for Attenuator 2 (DA_SP = 1)
STA_A_2
STA_B_2
0
0
Preprogrammed attenuation state 1
SETTING FOR DIGITAL ATTENUATOR 2*
1
0
Preprogrammed attenuation state 2
0
1
Preprogrammed attenuation state 3
1
1
Preprogrammed attenuation state 4
*Defined by SPI programming bits D36:D55 (see Table 3 for details).
19
MAX2063
Layout Considerations
If desired, the user can also program two additional
attenuation states by using the STA_B_1 control bit as a
second I/O pin. These two additional attenuation settings
are useful for software-defined radio applications where
multiple static gain settings are needed to account for
different frequencies of operation, or where multiple
dynamic attenuation settings are needed to account for
different blocker levels (as defined by multiple wireless
standards).
MAX2063
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
Table 7. Typical Application Circuit Component Values
20
DESIGNATION
QTY
DECRIPTION
COMPONENT SUPPLIER
C1, C2, C6, C8,
C9, C13
6
1000pF capacitors (0402)
Murata GRM1555C1H102J
Murata North America Electronics, Inc.
C4, C7, C11,
C14, C16
5
10nF capacitors (0402)
Murata GRM155R71E103K
Murata North America Electronics, Inc.
C15
1
1mF capacitor (0603)
Murata GRM188R71C105K
Murata North America Electronics, Inc.
L1, L2
2
820nH inductors (1008)
Coilcraft 1008CS-821XJLC
Coilcraft, Inc.
U1
1
VGA (48-pin thin QFN-EP, 7mm x 7mm)
Maxim MAX2063ETM+
Maxim Integrated Products, Inc.
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
RF
OUTPUT 1
C7
C6
RF
OUTPUT 2
C14
VCC
C13
L1
L2
GND
GND
AMP_IN_2
PD_2
GND
AMP_OUT_2
REG_OUT
AMPSET
AMP_OUT_1
GND
PD_1
MAX2063
18
17
44
45
DIGITAL
ATTENUATOR
1
46
47
16
DIGITAL
ATTENUATOR
2
SPI
15
14
13
48
2
1
GND
+
3
4
5
C1
RF
INPUT 1
6
7
8
9
GND
C11
C9
GND
DA_SP
GND
D4_2
D_ATT_OUT_2
D3_2
D2_2
D1_2
D0_2
GND
10 11 12
C8
VCC
C16
Chip Information
PROCESS: SiGe BiCMOS
19
VCC
VCC_AMP_2
GND
D0_1
42
43
20
EXPOSED
PAD
D_ATT_IN_2
D1_1
41
STA_A_2
D2_1
21
STA_B_2
D3_1
22
40
CS
D_ATT_OUT_1
23
ACTIVE
BIAS
AMP
VCC_RG
D4_1
39
AMP
CLK
GND
ACTIVE
BIAS
DAT
GND
38
STA_B_1
GND
GND
24
37
STA_A_1
C4
C2
36 35 34 33 32 31 30 29 28 27 26 25
VCC_AMP_1
D_ATT_IN_1
VCC
AMP_IN_1
GND
C15
RF
INPUT 2
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
48 Thin QFN-EP
T4877+7
21-0144
90-0133
21
MAX2063
Typical Application Circuit
MAX2063
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
Revision History
REVISION
NUMBER
REVISION
DATE
0
6/10
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
22
© 2010
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.