Octal, 12-/16-Bit, I2C, denseDACs with 5 ppm/°C On-Chip Reference AD5629R/AD5669R Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AD5629R/AD5669R A 1.25V/2.5V REF BUFFER LDAC INPUT REGISTER DAC REGISTER STRING DAC A INPUT REGISTER DAC REGISTER STRING DAC B INPUT REGISTER DAC REGISTER STRING DAC C SCL VOUTA BUFFER VOUTB BUFFER SDA E A VREFIN/VREFOUT A VOUTC BUFFER INPUT REGISTER DAC REGISTER STRING DAC D VOUTD BUFFER INPUT REGISTER DAC REGISTER STRING DAC E VOUTE BUFFER A0 INPUT REGISTER DAC REGISTER STRING DAC F VOUTF BUFFER APPLICATIONS Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources INPUT REGISTER DAC REGISTER STRING DAC G INPUT REGISTER DAC REGISTER STRING DAC H VOUTG BUFFER POWER-ON RESET LDAC CLR VOUTH POWER-DOWN LOGIC GND Figure 1. GENERAL DESCRIPTION The AD5629R/AD5669R devices are low power, octal, 12-/16bit, buffered voltage-output DACs. All devices are guaranteed monotonic by design. The AD5629R/AD5669R have an on-chip reference with an internal gain of 2. The AD5629R-1/AD5669R-1 have a 1.25 V, 5 ppm/°C reference, giving a full-scale output range of 2.5 V. The AD5629R-2/AD5629R-3 and the AD5669R-2/AD5669R-3 have a 2.5 V 5 ppm/°C reference, giving a full-scale output range of 5 V depending on the option selected. Devices with 1.25 V reference selected operate from a single 2.7 V to 5.5 V supply. Devices with 2.5 V reference selected operate from 4.5 V to 5.5 V. The on-chip reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write. Rev. B The parts incorporate a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5629R-1/AD5629R-2, AD5669R-1/AD5669R-2) or midscale (AD5629R-3/AD5669R-3) and remains powered up at this level until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 400 nA at 5 V and provides software-selectable output loads while in power-down mode for any or all DAC channels. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Octal, 12-/16-bit DACs. On-chip 1.25 V/2.5 V, 5 ppm/°C reference. Available in 16-lead LFCSP and TSSOP, and 16-ball WLCSP. Power-on reset to 0 V or midscale. Power-down capability. When powered down, the DAC typically consumes 200 nA at 3 V and 400 nA at 5 V. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 08819-001 E A VDD INTERFACE LOGIC Low power octal DACs AD5629R: 12 bits AD5669R: 16 bits 2.6 mm × 2.6 mm 16-ball WLCSP 4 mm × 4 mm 16-lead LFCSP and 16-lead TSSOP On-chip 1.25 V/2.5 V, 5 ppm/°C reference Power down to 400 nA at 5 V, 200 nA at 3 V 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale or midscale 3 power-down functions Hardware LDAC and CLR functions I2C-compatible serial interface supports standard (100 kHz) and fast (400 kHz) modes AD5629R/AD5669R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Resistor String ............................................................................. 21 Applications ....................................................................................... 1 Internal Reference ...................................................................... 21 Functional Block Diagram .............................................................. 1 Output Amplifier........................................................................ 22 General Description ......................................................................... 1 Serial Interface ............................................................................ 22 Product Highlights ........................................................................... 1 Write Operation.......................................................................... 22 Revision History ............................................................................... 2 Read Operation........................................................................... 22 Specifications..................................................................................... 3 Input Shift Register .................................................................... 23 AC Characteristics........................................................................ 6 Multiple Byte Operation ............................................................ 23 2 I C Timing Characteristics .......................................................... 7 Internal Reference Register ....................................................... 24 Absolute Maximum Ratings............................................................ 9 Power-On Reset .......................................................................... 24 ESD Caution .................................................................................. 9 Power-Down Modes .................................................................. 25 Pin Configuration and Function Descriptions ........................... 10 Clear Code Register ................................................................... 25 Typical Performance Characteristics ........................................... 12 LDAC Function .......................................................................... 27 Terminology .................................................................................... 19 Power Supply Bypassing and Grounding ................................ 27 Theory of Operation ...................................................................... 21 Outline Dimensions ....................................................................... 28 Digital-to-Analog Converter (DAC) Section ......................... 21 Ordering Guide .......................................................................... 30 REVISION HISTORY 2/13—Rev. A to Rev. B Added 16-Ball WLCSP ....................................................... Universal Changes to Features Section............................................................. 1 Added Figure 5, Renumbered Sequentially .................................10 Moved Table 6 ..................................................................................11 Changes to Figure 25 and Figure 26 ..............................................15 Added Figure 58...............................................................................29 Changes to Ordering Guide ...........................................................30 12/10—Rev. 0 to Rev. A Changes to Features, General Description, and Product Highlights Sections ........................................................................... 1 Changes to AD5629R Relative Accuracy Parameter, Reference Output (1.25 V) Reference Input Range Parameter, and Reference Output (2.5 V) Reference Input Range Parameter (Table 1) ...... 3 Changes to Relative Accuracy Parameter, Reference Tempco Parameter (Table 2) ...........................................................................5 Changes to Output Voltage Settling Time Parameter (Table 3) ..6 Changes to Table 5.............................................................................9 Changes to CLR Pin Description (Table 6) ................................. 10 Added Figure 32 and Figure 33 .................................................... 15 Added Figure 46 ............................................................................. 17 Changes to Internal Reference Section ........................................ 20 Changes to Power-On Reset Section ........................................... 23 Changes to Clear Code Register Section ..................................... 24 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 28 10/10—Revision 0: Initial Version Rev. B | Page 2 of 32 Data Sheet AD5629R/AD5669R SPECIFICATIONS VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE 2 AD5629R Resolution Relative Accuracy Differential Nonlinearity AD5669R Resolution Relative Accuracy Differential Nonlinearity A Grade 1 Min Typ Max B Grade1 Min Typ Max 12 12 DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT (1.25 V) Output Voltage Reference Input Range Output Impedance REFERENCE OUTPUT (2.5 V) Output Voltage Reference Input Range Output Impedance ±1 ±0.25 Bits LSB LSB ±32 ±1 ±8 ±16 ±1 Bits LSB LSB 19 6 ±2 −0.2 19 ±4 ±0.25 ±8 6 ±2 −0.2 16 ±2.5 ±6 –80 DC Crosstalk (Internal Reference) OUTPUT CHARACTERISTICS 3 Output Voltage Range Capacitive Load Stability ±0.5 ±0.5 16 Zero-Code Error Zero-Code Error Drift Full-Scale Error Gain Error Gain Temperature Coefficient Offset Error DC Power Supply Rejection Ratio DC Crosstalk (External Reference) Unit −1 ±1 ±2.5 ±6 –80 ±19 −1 ±1 ±19 mV µV/°C % FSR % FSR ppm mV dB 10 10 µV 5 10 25 5 10 25 µV/mA µV µV 10 10 µV/mA 0 VDD 0 2 10 0.5 30 4 40 0 50 VDD 40 0 14.6 1.247 1.253 1.247 ±5 ±15 7.5 7.5 2.505 ±15 7.5 2.495 ±5 7.5 V nF nF Ω mA µs See Figure 6 Guaranteed monotonic by design (see Figure 8) See Figure 5 Guaranteed monotonic by design (see Figure 7) All 0s loaded to DAC register (see Figure 18) All 1s loaded to DAC register (see Figure 19) Of FSR/°C VDD ± 10% Due to full-scale output change, RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) Due to full-scale output change, RL = 2 kΩ to GND or VDD Due to load current change RL = ∞ RL = 2 kΩ VDD = 5 V Coming out of power-down mode, VDD = 5 V 50 VDD µA V kΩ VREFIN = VDD = 5.5 V (per DAC channel) 1.253 ±15 µA ppm/°C TA = 25°C LFCSP, TSSOP WLCSP 14.6 ±15 2.495 VDD 2 10 0.5 30 4 Test Conditions/Comments kΩ 2.505 ±10 Rev. B | Page 3 of 32 µA ppm/°C kΩ TA = 25°C AD5629R/AD5669R Parameter LOGIC INPUTS3 Input Current Input Low Voltage, VINL Input High Voltage, VINH Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 4.5 V to 5.5 V IDD (All Power-Down Modes) 5 VDD = 4.5 V to 5.5 V Data Sheet A Grade 1 Min Typ Max B Grade1 Min Typ Max ±3 0.8 2 Unit Test Conditions/Comments ±3 0.8 µA V V pF All digital inputs VDD = 5 V VDD = 5 V 5.5 V 2 3 4.5 3 5.5 4.5 1.3 2 1.8 2.5 1.3 2 1.8 2.5 mA mA All digital inputs at 0 or VDD, DAC active, excludes load current VIH = VDD and VIL = GND Internal reference off Internal reference on 0.4 1 0.4 1 µA VIH = VDD and VIL = GND Temperature range is −40°C to +105°C, typical at 25°C. Linearity calculated using a reduced code range of the AD5629R (Code 32 to Code 4064) and the AD5669R (Code 512 to 65,024). Output unloaded. Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. 1 2 3 Rev. B | Page 4 of 32 Data Sheet AD5629R/AD5669R VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE 2 AD5629R Resolution Relative Accuracy Differential Nonlinearity AD5669R Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Zero-Code Error Drift Full-Scale Error Gain Error Gain Temperature Coefficient Offset Error DC Power Supply Rejection Ratio DC Crosstalk (External Reference) A Grade 1 Min Typ Max B Grade1 Min Typ Max 12 12 ±4 ±0.25 ±8 ±32 ±1 19 16 ±0.5 ±1 ±0.25 ±8 ±16 ±1 19 16 6 ±2 −0.2 ±2.5 ±6 –80 DC Crosstalk (Internal Reference) OUTPUT CHARACTERISTICS Output Voltage Range Capacitive Load Stability ±0.5 6 ±2 −0.2 −1 ±1 ±2.5 ±6 –80 ±19 −1 ±1 ±19 Unit Conditions/Comments Bits LSB LSB See Figure 6 Guaranteed monotonic by design (see Figure 8) Bits LSB LSB mV µV/°C % FSR % FSR ppm mV dB 10 10 µV 5 10 25 5 10 25 µV/mA µV µV 10 10 µV/mA See Figure 5 Guaranteed monotonic by design (see Figure 7) All 0s loaded to DAC register (see Figure 18) All 1s loaded to DAC register (see Figure 19) Of FSR/°C VDD ± 10% Due to full-scale output change, RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) Due to full-scale output change, RL = 2 kΩ to GND or VDD Due to load current change 3 DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT Output Voltage AD5629R/AD5669R Reference Tempco3 Reference Output Impedance LOGIC INPUTS3 Input Current Input Low Voltage, VINL Input High Voltage, VINH Pin Capacitance 0 VDD 0 VDD 2 10 0.5 30 4 40 0 2 10 0.5 30 4 50 VDD 40 0 14.6 1.247 14.6 1.253 1.247 ±5 ±15 7.5 ±15 7.5 ±3 0.8 2 50 VDD µA RL = ∞ RL = 2 kΩ VDD = 3 V Coming out of power-down mode, VDD = 3 V VREFIN = VDD = 3.6 V (per DAC channel) kΩ 1.253 ±15 V ppm/°C TA = 25°C LFCSP, TSSOP WLCSP kΩ ±3 0.8 2 3 V nF nF Ω mA µs 3 Rev. B | Page 5 of 32 µA V V pF All digital inputs VDD = 3 V VDD = 3 V AD5629R/AD5669R Parameter POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) 5 VDD = 2.7 V to 3.6 V Data Sheet A Grade 1 Min Typ Max B Grade1 Min Typ Max Unit Conditions/Comments 2.7 2.7 3.6 V 3.6 1.0 1.8 1.5 2.25 1.0 1.7 1.5 2.25 mA mA All digital inputs at 0 or VDD, DAC active, excludes load current VIH = VDD and VIL = GND Internal reference off Internal reference on 0.2 1 0.2 1 µA VIH = VDD and VIL = GND Temperature range is −40°C to +105°C, typical at 25°C. Linearity calculated using a reduced code range of the AD5629R (Code 32 to Code 4064) and the AD5669R (Code 512 to 65,024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. 1 2 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1, 2 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Reference Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Min Typ 2.5 1.2 4 19 0.1 −90 0.2 0.4 0.8 320 −80 120 100 Max 7 Unit µs V/µs nV-s nV-s nV-s dB nV-s nV-s nV-s kHz dB nV/√Hz nV/√Hz Conditions/Comments 3 ¼ to ¾ scale settling to ±2 LSB 1 LSB change around major carry (see Figure 35) From Code 59904 to Code 59903 VREFIN = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz VREFIN = 2 V ± 0.2 V p-p VREFIN = 2 V ± 0.1 V p-p, frequency = 10 kHz DAC code = 0x8400, 1 kHz DAC code = 0x8400, 10 kHz Guaranteed by design and characterization; not production tested. See the Terminology section. 3 Temperature range is −40°C to +105°C, typical at 25°C. 1 2 Rev. B | Page 6 of 32 Data Sheet AD5629R/AD5669R I2C TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 400 kHz, unless otherwise noted. Table 4. Parameter fSCL 1 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t11A t12 t13 t14 t15 tSP 2 Conditions Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Min 4 0.6 4.7 1.3 250 100 0 0 4.7 0.6 4 0.6 4.7 1.3 4 0.6 Max 100 400 3.45 0.9 1000 300 300 300 1000 300 1000 300 300 300 Unit kHz kHz μs μs μs μs ns ns μs μs μs μs μs μs μs μs μs μs ns ns ns ns ns ns ns Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode 10 10 300 ns ns ns ns ns ns Fast mode Standard mode Fast mode Fast mode 300 20 20 0 ns ns ns ns 50 Description Serial clock frequency tHIGH, SCL high time tLOW, SCL low time tSU;DAT, data setup time tHD;DAT, data hold time tSU;STA, setup time for a repeated start condition tHD;STA, hold time (repeated) start condition tBUF, bus-free time between a stop and a start condition tSU;STO, setup time for a stop condition tRDA, rise time of SDA signal tFDA, fall time of SDA signal tRCL, rise time of SCL signal tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit tFCL, fall time of SCL signal LDAC pulse width low Falling edge of ninth SCL clock pulse of last byte of a valid write to the LDAC falling edge CLR pulse width low Pulse width of spike suppressed The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC behavior of the part. 2 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode. 1 Rev. B | Page 7 of 32 AD5629R/AD5669R Data Sheet t11 t12 t6 t2 SCL t1 t6 t4 t5 t3 t8 t10 t9 SDA t7 P S S P t14 t15 CLR *ASYNCHRONOUS LDAC UPDATE MODE. Figure 2. Serial Write Operation Rev. B | Page 8 of 32 08819-002 t13 LDAC* Data Sheet AD5629R/AD5669R ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND Digital Input Voltage to GND VOUT to GND VREFIN/VREFOUT to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ MAX) Power Dissipation Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 16-Lead LFCSP (4-Layer Board) Reflow Soldering Peak Temperature Pb Free Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +105°C −65°C to +150°C +150°C (TJ MAX − TA)/θJA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 112.6°C/W 30.4°C/W 260°C Rev. B | Page 9 of 32 AD5629R/AD5669R Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW (Not to Scale) 10 VOUTD 9 CLR 7 VOUTF NOTES 1. EXPOSED PAD MUST BE TIED TO GND. 16 SCL A0 2 15 SDA 14 GND 13 VOUTB 12 VOUTD VDD VOUTH 8 VOUTG 5 VREFIN/VREFOUT 6 VOUTE 4 LDAC 1 3 VOUTA 4 AD5629R/ AD5669R VOUTC 5 TOP VIEW (Not to Scale) VOUTE 6 11 VOUTF VOUTG 7 10 VOUTH VREFIN/VREFOUT 8 9 CLR 08819-003 VOUTC 3 12 GND 11 VOUTB Figure 4. 16-Lead TSSOP (RU-16) Figure 3. 16-Lead LFCSP (CP-16-17) BALL A1 INDICATOR 1 GND 2 3 4 SCL SDA A0 A VOUTB LDAC VDD VOUTA B VOUTF VOUTD VOUTE VOUTC C VOUTH CLR VREF VOUTG D TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 5. 16-Ball WLCSP Rev. B | Page 10 of 32 08819-105 VDD 1 VOUTA 2 08819-004 13 SDA 14 SCL 16 A0 15 LDAC AD5629R/AD5669R Data Sheet AD5629R/AD5669R Table 6. Pin Function Descriptions LFCSP Pin No. TSSOP WLCSP Mnemonic Description 15 1 B2 LDAC 16 1 2 3 A4 B3 A0 VDD 2 3 4 5 6 4 5 6 7 8 B4 B1 C4 C2 D3 VOUTA VOUTC VOUTE VOUTG VREFIN/VREFOUT 7 9 D2 CLR 8 9 10 11 12 13 10 11 12 13 14 15 C3 C1 D4 D1 A1 A3 VOUTH VOUTF VOUTD VOUTB GND SDA 14 16 A4 SCL 17 N/A N/A Exposed Pad (EPAD) Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low. Address Input. Sets the least significant bit of the 7-bit slave address. Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. The AD5629R/AD5669R have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero scale, midscale, or full scale. The default setting clears the output to 0 V. Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Parts. Serial Data Input. This is used in conjunction with the SCL line to clock data into or out of the 32-bit input shift register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 32-bit input shift register. The exposed pad must be tied to GND. Rev. B | Page 11 of 32 AD5629R/AD5669R Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 10 0.20 VDD = 5V EXT REF = 5V TA = 25°C 8 VDD = 5V EXT REF = 5V 0.15 TA = 25°C 6 0.10 2 DNL (LSB) INL (LSB) 4 0 –2 0.05 0 –0.05 –4 –0.10 –6 0 10k 20k 30k 40k 50k 60k 65535 CODES –0.20 08819-106 –10 0 1500 2000 2500 3000 3500 4095 Figure 9. DNL AD5629R—External Reference 10 VDD = 5V EXT REF = 5V TA = 25°C 0.8 1000 CODES Figure 6. INL AD5669R—External Reference 1.0 500 08819-111 –0.15 –8 VDD = 5V INT REF = 2.5V TA = 25°C 0.6 5 0.2 INL (LSB) INL (LSB) 0.4 0 –0.2 0 –0.4 –5 –0.6 0 500 1000 1500 2000 2500 3000 3500 4095 CODES –10 08819-108 –1.0 0 30k 40k 50k 60k 65535 Figure 10. INL AD5669R-2—Internal Reference 1.0 VDD = 5V EXT REF = 5V TA = 25°C 0.8 20k CODES Figure 7. INL AD5629R—External Reference 1.0 10k 08819-112 –0.8 VDD = 5V INT REF = 2.5V TA = 25°C 0.6 0.5 INL (LSB) 0.2 0 –0.2 0 –0.4 –0.5 –0.6 –1.0 0 10k 20k 30k 40k 50k CODES 60k 65535 Figure 8. DNL AD5669R—External Reference –1.0 0 500 1000 1500 2000 2500 3000 3500 CODES Figure 11. INL AD5629R-2—Internal Reference Rev. B | Page 12 of 32 4095 08819-114 –0.8 08819-109 DNL (LSB) 0.4 Data Sheet 1.0 AD5629R/AD5669R 1.0 VDD = 5V INT REF = 2.5V TA = 25°C 0.5 INL (LSB) 0 –0.5 0 –0.5 0 10k 20k 30k 40k 50k 60k 65535 CODES –1.0 08819-115 –1.0 0 1000 1500 2000 2500 3000 3500 4095 CODES Figure 12. DNL AD5669R-2—Internal Reference Figure 15. INL AD5629R-1—Internal Reference 0.20 1.0 VDD = 5V INT REF = 2.5V 0.15 TA = 25°C VDD = 3V INT REF = 1.25V TA = 25°C 0.10 0.5 0.05 DNL (LSB) DNL (LSB) 500 08819-120 DNL (LSB) 0.5 VDD = 3V INT REF = 1.25V TA = 25°C 0 –0.05 –0.10 0 –0.5 0 500 1000 1500 2000 2500 3000 3500 4095 CODES –1.0 08819-117 –0.20 0 30k 40k 50k 60k 65535 Figure 16. DNL AD5669R-1—Internal Reference 0.20 VDD = 3V INT REF = 1.25V TA = 25°C 8 20k CODES Figure 13. DNL AD5629R-2— Internal Reference 10 10k 08819-121 –0.15 VDD = 3V INT REF = 1.25V TA = 25°C 0.15 6 0.10 DNL (LSB) 2 0 –2 0.05 0 –0.05 –4 –0.10 –6 –10 0 10k 20k 30k 40k 50k 60k 65535 CODES Figure 14. INL AD5669R-1—Internal Reference –0.20 0 500 1000 1500 2000 2500 3000 3500 CODES Figure 17. DNL AD5629R-1—Internal Reference Rev. B | Page 13 of 32 4095 08819-123 –0.15 –8 08819-118 INL (LSB) 4 AD5629R/AD5669R Data Sheet 0 1.95 VDD = 5V TA = 25°C 1.90 –0.05 OFFSET ERROR ERROR (mV) ERROR (% FSR) 1.85 –0.10 FULL-SCALE ERROR –0.15 –0.20 1.80 1.75 1.70 ZERO-CODE ERROR GAIN ERROR 1.65 –0.25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 1.55 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) Figure 18. Gain Error and Full-Scale Error vs. Temperature 08819-127 –25 08819-124 1.60 –0.30 –40 Figure 21. Zero-Code Error and Offset Error vs. Supply Voltage 21 6 VDD = 5V 18 5 OFFSET ERROR NUMBER OF HITS 15 ERROR (mV) 4 ZERO-CODE ERROR 3 2 12 9 6 1 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 0 0.85 0.90 0.95 1.00 IDD WITH EXTERNAL REFERENCE (mA) 1.05 08819-128 –25 08819-125 0 –40 3 Figure 22. IDD Histogram with External Reference Figure 19. Zero-Code Error and Offset Error vs. Temperature 18 –0.16 TA = 25°C FULL-SCALE ERROR –0.17 16 –0.18 14 NUMBER OF HITS –0.20 –0.21 –0.22 –0.23 10 8 6 GAIN ERROR 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) 0 1.65 1.70 1.75 1.80 1.85 IDD WITH INTERNAL REFERENCE (mA) Figure 23. IDD Histogram with Internal Reference Figure 20. Gain Error and Full-Scale Error vs. Supply Voltage Rev. B | Page 14 of 32 1.90 08819-129 2 –0.25 –0.26 2.7 12 4 –0.24 08819-126 ERROR (% FSR) –0.19 Data Sheet AD5629R/AD5669R 0.4 1.8 TA = 25°C TA = 25°C 1.7 0.3 1.6 VDD = 5V 1.5 0.1 VDD = 3V, INT REF = 1.25V 0 IDD (mA) –0.1 1.4 VDD = 3V 1.3 1.2 –0.2 1.1 –0.3 1.0 VDD = 5V, INT REF = 2.5V –0.4 0.9 –8 –6 –4 –2 0 2 4 6 8 10 SOURCE/SINK CURRENT (mA) 0.8 08819-130 –0.5 –10 0 10k 20k 30k 40k 50k 08819-133 ERROR VOLTAGE (V) 0.2 60k DIGITAL CODES (Decimal) Figure 24. Headroom at Rails vs. Source and Sink Figure 27. Supply Current vs. Code 6 2.0 VDD = 5V INT REF = 2.5V 5 TA = 25°C TA = 25°C FULL SCALE 1.9 1.8 3/4 SCALE 3 1.7 IDD (mA) VOUT (V) 4 MIDSCALE 2 VDD = 5.5V 1.6 1.5 VDD = 3.6V 1.4 1/4 SCALE 1.3 1 1.2 0 –0.02 –0.01 0 0.01 0.02 0.03 SOURCE AND SINK CURRENT (A) 1.0 –40 08819-131 –1 –0.03 3.5 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 25. AD5669R-2 Source and Sink Capability 4.0 –25 08819-134 1.1 ZERO CODE Figure 28. Supply Current vs. Temperature 1.48 VDD = 3V INT REF = 1.25V TA = 25°C TA = 25°C 1.46 3.0 FULL SCALE 1.44 1.5 IDD (mA) 3/4 SCALE 2.0 MIDSCALE 1.0 1.42 1.40 1/4 SCALE 0.5 1.38 ZERO CODE 0 1.36 –1.0 –0.03 –0.02 –0.01 0 0.01 0.02 SOURCE AND SINK CURRENT (A) 0.03 Figure 26. AD5669R-1 Source and Sink Capability 1.34 2.7 3.1 3.5 3.9 4.3 4.7 5.1 VDD (V) Figure 29. Supply Current vs. Supply Voltage Rev. B | Page 15 of 32 5.5 08819-135 –0.5 08819-132 VOUT (V) 2.5 AD5629R/AD5669R Data Sheet 5.5 2.3 VDD = 5V 5.0 EXT REF = 5V TA = 25°C 4.5 TA = 25°C 2.1 4.0 1.9 VOLTAGE (V) 1.7 IDD (mA) VDD 3.5 VDD = 5V 1.5 3.0 2.5 VOUTA 2.0 1.5 1.3 1.0 1.1 0.5 VDD = 3V 0 0.7 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VLOGIC (V) 5 –0.0002 0.0002 0.0006 0.0010 TIME (s) Figure 30. Supply Current vs. Logic Input Voltage 6 –0.0006 08819-136 –0.5 –0.0010 08819-139 0.9 Figure 33. Power-On Reset to Midscale 5.5 VDD = 5V EXT REF = 5V TA = 25°C 5.0 4.5 24TH CLK RISING EDGE VDD = 5V EXT REF = 5V TA = 25°C 4.0 3.5 VOLTAGE (V) VOUT (V) 4 3 3.0 2.5 VOUTA 2.0 1.5 2 1.0 0.5 1 0 2 4 6 8 TIME (µs) 08819-137 0 –2 5.0 4.5 5 10 Figure 34. Exiting Power-Down to Midscale VDD = 5V EXT REF = 5V TA = 25°C 4.0 0 TIME (µs) Figure 31. Full-Scale Settling Time, 5 V 5.5 –5 T VDD = 5V EXT REF = 5V TA = 25°C VDD 3.0 VOUTA 2.5 3 2.0 1.5 1.0 24TH CLK RISING EDGE 0.5 VOUTA –0.0006 –0.0002 0.0002 0.0006 TIME (s) 0.0010 Figure 32. Power-On Reset to 0 V 4 CH3 10.0mV B W CH4 5.0V M400ns T 17.0% A CH4 1.50V Figure 35. Digital-to-Analog Glitch Impulse (Negative) Rev. B | Page 16 of 32 08819-141 0 –0.5 –0.0010 08819-138 VOLTAGE (V) 3.5 08819-140 0 –0.5 –10 Data Sheet 0.0010 AD5629R/AD5669R 0.20 VDD = 5V EXT REF = 5V TA = 25°C EXT REF = 2.5V DAC CODE = 0xFF00 0.15 0.10 OUTPUT NOISE (V) GLITCH AMPLITUDE (V) 0.0005 0 –0.0005 0.05 0 –0.05 –0.10 –0.0010 –0.15 1 2 3 4 5 6 7 8 9 TIME (µs) –0.20 0 2 3 4 5 6 7 8 9 10 TIME (s) Figure 36. Analog Crosstalk Figure 39. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference 0.0020 0.20 VDD = 5V EXT REF = 5V TA = 25°C 0.0015 INT REF = 1.25V DAC CODE = 0xFF00 0.15 0.10 0.0010 OUTPUT NOISE (V) GLITCH AMPLITUDE (V) 1 08819-145 0 08819-142 –0.0015 0.0005 0 0.05 0 –0.05 –0.0005 –0.10 –0.0010 –0.15 1 2 3 4 5 6 7 8 TIME (µs) –0.20 0 2 3 4 5 6 7 8 9 10 TIME (s) Figure 37. DAC-to-DAC Crosstalk Figure 40. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference 800 0.06 VDD = 5.5V EXT REF = 5V DAC CODE = 0xFF00 0.04 VDD = 5.5V DAC CODE = 0x8400 OUTPUT NOISE (nV/ Hz) 700 0.02 0 –0.02 –0.04 –0.06 600 500 400 VREF = 2.5V 300 200 100 0 1 2 3 4 5 6 7 8 9 10 TIME (s) 0 100 1k 10k 100k FREQUENCY (Hz) Figure 41. Noise Spectral Density, Internal Reference Figure 38. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Rev. B | Page 17 of 32 1M 08819-147 VREF = 1.25V –0.08 08819-144 OUTPUT VOLTAGE (V) 1 08819-146 0 08819-143 –0.0015 AD5629R/AD5669R Data Sheet 0 10 VDD = 5.5V EXT REF = 5V –20 TA = 25°C VREF = 2V ± 0.1V p-p FREQUENCY = 10kHz –40 0 –10 –60 –80 –30 –40 –50 –100 –60 –120 –70 0 2000 4000 6000 8000 10,000 FREQUENCY (Hz) –80 10 08819-148 –140 CH A CH B CH C CH D CH E CH F CH G CH H –3dB 100 VDD = 5.5V EXT REF = 5V TA = 25°C VREF = 2V ± 0.2V p-p 1k 1k0 100k 1M Figure 45. Multiplying Bandwidth 1.2510 VDD = 5.5V 1.2508 TA = 25°C 8 1.2506 VDD = EXTERNAL REFERENCE = 5V REFERENCE (ppm/°C) 7 SETTLING TIME (µs) 100M FREQUENCY (Hz) Figure 42. Total Harmonic Distortion 9 10M 08819-151 VOUT (dBm) THD (dB) –20 6 5 4 3 VDD = EXTERNAL REFERENCE = 3V 1.2504 1.2502 1.2500 1.2498 1.2496 1.2494 2 1.2492 1 1 2 3 4 5 6 7 8 9 10 CAPACITIVE LOAD (nF) 08819-149 –40 0 Figure 43. Settling Time vs. Capacitive Load 25 08819-152 1.2490 0 105 TEMPERATURE (°C) Figure 46. 1.25 V Reference Temperature Coefficient vs. Temperature 2.503 5.5 EXT REF = 5V 2.502 5.0 4.5 REFERENCE (ppm/°C) 2.501 4.0 3.0 VOUTA 2.5 2.0 1.5 2.500 2.499 2.498 2.497 CLR PULSE 1.0 0 –0.5 –10 2.495 105 –5 0 TIME (µs) Figure 44. Hardware CLR 5 10 25 TEMPERATURE (°C) –40 08819-153 2.496 0.5 08819-150 VOLTAGE (V) 3.5 Figure 47. 2.5 V Reference Temperature Coefficient vs. Temperature Rev. B | Page 18 of 32 Data Sheet AD5629R/AD5669R TERMINOLOGY Relative Accuracy For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. Figure 5, Figure 6, Figure 9, Figure 10, Figure 13, and Figure 14 show plots of typical INL vs. code. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Figure 7, Figure 8, Figure 11, Figure 12, Figure 15, and Figure 16 show plots of typical DNL vs. code. Offset Error Offset error is a measure of the difference between the actual VOUT and the ideal VOUT, expressed in millivolts in the linear region of the transfer function. Offset error is measured on the AD5669R between Code 512 and Code 65024 loaded into the DAC register. It can be negative or positive and is expressed in millivolts. Zero-Code Error Zero-code error is a measure of the output error when zero code (0x0000) is loaded into the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in millivolts. Figure 19 shows a plot of typical zero-code error vs. temperature. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. Zero-Code Error Drift Zero-code error drift is a measure of the change in zero-code error with a change in temperature. It is expressed in µV/°C. Gain Error Drift Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be VREF − 1 LSB. Full-scale error is expressed as a percentage of the full-scale range. Figure 17 shows a plot of typical full-scale error vs. temperature. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). Figure 35 shows a typical digital-to-analog glitch impulse plot. DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. VREF is held at 2 V, and VDD is varied ±10%. It is measured in decibels. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in microvolts. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has on another DAC kept at midscale. It is expressed in microvolts per milliamp. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device, but is measured when the DAC is not being written to. It is specified in nV-s and measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s. Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s or vice versa) while keeping LDAC high and then pulsing LDAC low and monitoring the output of the DAC whose digital code has not changed. The area of the glitch is expressed in nV-s. Rev. B | Page 19 of 32 E A A E A AD5629R/AD5669R Data Sheet DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Total Harmonic Distortion (THD) Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels. E A A Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Rev. B | Page 20 of 32 Data Sheet AD5629R/AD5669R THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) SECTION RESISTOR STRING The AD5629R/AD5669R are fabricated on a CMOS process. The architecture consists of a string of DACs followed by an output buffer amplifier. Each part includes an internal 1.25 V/2.5 V, 5 ppm/°C reference with an internal gain of 2. Figure 48 and Figure 49 show block diagrams of the DAC architecture. The resistor string section is shown in Figure 50. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. VREFIN/VREFOUT R INTERNAL REFERENCE 1 OUTPUT AMPLIFIER GAIN = ×2 REF (+) DAC REGISTER R RESISTOR STRING VOUT REF (–) 08819-045 1CAN BE OVERDRIVEN BY VREFIN/VREFOUT . TO OUTPUT AMPLIFIER R GND Figure 48. DAC Architecture for Internal Reference Configuration R VREFIN/VREFOUT 08819-047 R REF BUFFER R R REF (+) RESISTOR STRING OUTPUT AMPLIFIER GAIN = ×2 Figure 50. Resistor String INTERNAL REFERENCE VOUT GND 08819-046 REF (–) Figure 49. DAC Architecture for External Reference Configuration Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by D VOUT VREFIN N 2 The ideal output voltage when using the internal reference is given by D VOUT 2 V REFOUT N 2 where: D = decimal equivalent of the binary code that is loaded to the DAC register as follows: 0 to 4095 for AD5629R (12 bits). 0 to 65,535 for AD5669R (16 bits). N = the DAC resolution. The AD5629R/AD5669R have an on-chip reference with an internal gain of 2. The AD5629R-1/AD5669R-1 have a 1.25 V, 5 ppm/°C reference, giving a full-scale output of 2.5 V or the AD5629R-2/AD5629R-3/AD5669R-2/AD5629R-3 have a 2.5 V, 5 ppm/°C reference, working between a supply from 4.5 V to 5.5 V giving a full-scale output of 5 V. The on-board reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a write to the control register (see Table 8). The internal reference associated with each part is available at the VREFOUT pin. A buffer is required if the reference output is used to drive external loads. When using the internal reference, it is recommended that a 100 nF capacitor be placed between the reference output and GND for reference stability. Individual channel power-down is not supported while using the internal reference. Rev. B | Page 21 of 32 AD5629R/AD5669R Data Sheet OUTPUT AMPLIFIER The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. The amplifier is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 24 and Figure 25. The slew rate is 1.5 V/μs with a ¼ to ¾ scale settling time of 10 μs. 2. SERIAL INTERFACE The AD5629R/AD5669R have 2-wire I2C-compatible serial interfaces (refer to The I2C-Bus Specification, Version 2.1, January 2000, available from Philips Semiconductor). The AD5629R/AD5669R can be connected to an I2C bus as a slave device under the control of a master device. See Figure 2 for a timing diagram of a typical write sequence. 3. The AD5629R/AD5669R support standard (100 kHz) and fast (400 kHz) modes. High speed operation is only available on selected models. See the Ordering Guide for a full list of models. Support is not provided for 10-bit addressing and general call addressing. WRITE OPERATION When writing to the AD5629R/AD5669R, the user must begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The AD5629R/AD5669R require two bytes of data for the DAC and a command byte that controls various DAC functions. Three bytes of data must, therefore, be written to the DAC, the command byte followed by the most significant data byte and the least significant data byte, as shown in Figure 51. After these data bytes are acknowledged by the AD5629R/AD5669R, a stop condition follows. The AD5629R/AD5669R each have a 7-bit slave address. The parts have a slave address whose five MSBs are 10101, and the two LSBs are set by the state of the A0 address pin, which determines the state of the A0 and A1 address bits. The facility to make hardwired changes to the A0 pin allows the user to incorporate up to three of these devices on one bus, as outlined in Table 7. Table 7. ADDR Pin Settings A0 Pin Connection VDD NC GND A1 0 1 1 A0 0 0 1 READ OPERATION When reading data back from the AD5629R/AD5669R, the user begins with a start command followed by an address byte (R/W = 1), after which the DAC acknowledges that it is prepared to transmit data by pulling SDA low. Two bytes of data are then read from the DAC, which are both acknowledged by the master as shown in Figure 52. A stop condition follows. The 2-wire serial bus protocol operates as follows: The master initiates data transfer by establishing a start condition when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave 1 9 1 9 SCL 1 SDA 0 1 0 1 A1 R/W A0 DB23 DB22 DB21 DB20 DB19 DB18 DB17 ACK. BY AD5629R/AD5669R START BY MASTER DB16 ACK. BY AD5629R/AD5669R FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 1 9 SCL (CONTINUED) SDA (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 FRAME 3 MOST SIGNIFICANT DATA BYTE DB9 DB8 DB7 DB6 ACK. BY AD5629R/AD5669R Figure 51. I2C Write Operation Rev. B | Page 22 of 32 DB5 DB4 DB3 DB2 FRAME 4 LEAST SIGNIFICANT DATA BYTE DB1 DB0 STOP BY ACK. BY AD5629R/AD5669R MASTER 08819-048 1. address corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master brings the SDA line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition. Data Sheet AD5629R/AD5669R 1 9 1 9 SCL 1 SDA 0 1 0 1 A1 A0 DB23 R/W DB22 DB21 DB20 DB19 DB18 DB17 ACK. BY AD5629R/AD5669R START BY MASTER DB16 ACK. BY MASTER FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 1 9 SCL (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 ACK. BY MASTER FRAME 3 MOST SIGNIFICANT DATA BYTE DB5 DB4 DB3 DB2 DB1 FRAME 4 LEAST SIGNIFICANT DATA BYTE DB0 NO ACK. STOP BY MASTER 08819-049 SDA (CONTINUED) Figure 52. I2C Read Operation Table 8. Command Definitions Command C3 C2 C1 0 0 0 0 0 0 0 0 1 C0 0 1 0 INPUT SHIFT REGISTER Description Write to Input Register n Update DAC Register n Write to Input Register n; update all (software LDAC) Write to and update DAC Channel n Power down/power up DAC Load clear code register Load LDAC register Reset (power-on reset) Set up internal REF register Enable multiple byte mode Reserved Reserved Reserved E A A 0 0 0 0 0 1 1 1 – 1 0 1 1 1 1 0 0 0 – 1 1 0 0 1 1 0 0 1 – 1 1 0 1 0 1 0 1 0 – 1 E A A Table 9. Address Commands A3 0 0 0 0 0 0 0 0 1 Address (n) A2 A1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 A0 0 1 0 1 0 1 0 1 1 The input shift register is 24 bits wide. Data is loaded into the device as a 24-bit word under the control of a serial clock input, SCL. The input register contents for this operation is shown in Figure 53 and Figure 54. The eight MSBs make up the command byte. DB23 to DB20 are the command bits, C3, C2, C1, and C0, that control the mode of operation of the device (see Table 9 for details). The last four bits of the first byte are the address bits, A3, A2, A1, and A0, (see Table 9 for details). The rest of the bits are the 16-/12-bit data-word. Selected DAC Channel DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H All DACs The AD5669R data-word comprises the 16-bit input code (see Figure 53) while the AD5629R data word is comprised of 12bits followed by four don’t cares (see Figure 54). MULTIPLE BYTE OPERATION Multiple byte operation is supported on the AD5629R/ AD5669R. Command 1001 is reserved for multiple byte operation (see Table 8) A 2-byte operation is useful for applications that require fast DAC updating and do not need to change the command byte. The S bit (DB22) in the command register can be set to 1 for the 2-byte mode of operation. For standard 3-byte and 4-byte operation, the S bit (DB22) in the command byte should be set to 0. Rev. B | Page 23 of 32 AD5629R/AD5669R Data Sheet INTERNAL REFERENCE REGISTER POWER-ON RESET The internal reference is available on all versions. The on-board reference is off at power-up by default. The on-board reference can be turned off or on by a user-programmable internal REF register by setting Bit DB0 high or low (see Table 10). DB1 selects the internal reference value. Command 1000 is reserved for setting the internal REF register (see Table 8). Table 11 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device. The AD5629R/AD5669R contain a power-on reset circuit that controls the output voltage during power-up. The AD5629R/ AD5669R DAC output powers up to 0 V and the AD5669R-3 DAC output powers up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. There is also a software executable reset function that resets the DAC to the power-on reset code. Command 0111 is reserved for this reset function (see Table 8). Any events on LDAC or CLR during power-on reset are ignored. E C3 C2 C1 C0 A3 COMMAND A2 A1 A0 D15 D14 D13 DAC ADDRESS COMMAND BYTE D12 D11 D10 A A DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE 08819-050 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 E A A DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 C3 C2 C1 COMMAND C0 A2 A3 A1 DAC ADDRESS COMMAND BYTE A0 D11 D10 D9 D8 D7 D6 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D5 D4 D3 D2 D1 D0 X X X X DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE Figure 54. AD5629R Input Register Contents Rev. B | Page 24 of 32 08819-052 Figure 53. AD5669R Input Register Contents Data Sheet AD5629R/AD5669R POWER-DOWN MODES The AD5629R/AD5669R contain four separate modes of operation. Command 0100 is reserved for the power-down function (see Table 8). These modes are software-programmable by setting two bits, Bit DB9 and Bit DB8, in the control register. Table 12 shows how the state of the bits corresponds to the mode of operation of the device. Any or all DACs (DAC H to DAC A) can be powered down to the selected mode by setting the corresponding eight bits (DB7 to DB0) to 1. See Table 13 for the contents of the input shift register during power-down/powerup operation. When both bits are set to 0, the part works normally with its normal power consumption of 1.3 mA at 5 V. However, for the three power-down modes, the supply current falls to 0.4 μA at 5 V (0.2 μA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected internally to GND through either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited (three-state). The output stage is illustrated in Figure 55. AMPLIFIER POWER-DOWN CIRCUITRY RESISTOR NETWORK Figure 55. Output Stage During Power-Down Any combination of DACs can be powered up by setting PD1 and PD0 to 0 (normal operation). The output powers up to the value in the input register (LDAC low) or to the value in the DAC register before powering down (LDAC high). CLEAR CODE REGISTER The AD5629R/AD5669R have a hardware CLR pin that is an asynchronous clear input. The CLR input is falling edge sensitive. Bringing the CLR line low clears the contents of the input register and the DAC registers to the data contained in the user-configurable CLR register and sets the analog outputs accordingly. This function can be used in system calibration to load zero scale, midscale, or full scale to all channels together. These clear code values are user-programmable by setting two bits, Bit DB1 and Bit DB0, in the CLR control register (see Table 15). The default setting clears the outputs to 0 V. Command 0101 is reserved for loading the clear code register (see Table 8). The part exits clear code mode at the end of the next valid write to the part. If CLR is activated during a write sequence, the write is aborted. VOUT 08819-051 RESISTOR STRING DAC The bias generator of the selected DAC(s), output amplifier, resistor string, and other associated linear circuitry is shut down when the power-down mode is activated. The internal reference is powered down only when all channels are powered down. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 μs for VDD = 5 V and for VDD = 3 V. The CLR pulse activation time (the falling edge of CLR to when the output starts to change) is typically 280 ns. However, if outside the DAC linear region, it typically takes 520 ns after executing CLR for the output to start changing (see Figure 44). See Table 14 for the contents of the input shift register during the loading clear code register operation. Table 10. Internal Reference Register Internal REF Register (DB0) 0 1 Action Reference off (default) Reference on Table 11. 32-Bit Input Shift Register Contents for Reference Set-Up Command MSB DB23 1 DB22 DB21 DB20 0 0 0 Command bits (C3 to C0) DB19 DB18 DB17 DB16 X X X X Address bits (A3 to A0)—don’t cares Rev. B | Page 25 of 32 DB15 to DB1 X Don’t cares LSB DB0 1/0 Internal REF on/off AD5629R/AD5669R Data Sheet Table 12. Power-Down Modes of Operation DB9 0 DB8 0 0 1 1 1 0 1 Operating Mode Normal operation Power-down modes 1 kΩ to GND 100 kΩ to GND Three-state Table 13. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function MSB DB23 DB22 DB21 DB20 0 1 0 0 Command bits (C3 to C0) DB19 to DB16 X Address bits (A3 to A0)— don’t cares DB15 to DB10 X Don’t cares DB9 DB8 PD1 PD0 Powerdown mode LSB DB7 to DB1 DB0 DAC H to DAC B DAC A Power-down/power-up channel selection— set bit to 1 to select Table 14. 32-Bit Input Shift Register Contents for Clear Code Function MSB DB23 0 DB22 DB21 DB20 1 0 1 Command bits (C3 to C0) DB19 DB18 DB17 DB16 X X X X Address bits (A3 to A0)—don’t cares Table 15. Clear Code Register DB1 CR1 0 0 1 1 Clear Code Register DB0 CR0 0 1 0 1 Clears to Code 0x0000 0x8000 0xFFFF No operation Rev. B | Page 26 of 32 DB15 to DB2 X Don’t cares LSB DB1 DB0 CR1 CR0 Clear code register Data Sheet AD5629R/AD5669R LDAC FUNCTION POWER SUPPLY BYPASSING AND GROUNDING The outputs of all DACs can be updated simultaneously using the hardware LDAC pin. When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5629R/AD5669R should have separate analog and digital sections. If the AD5629R/ AD5669R are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5629R/AD5669R. Synchronous LDAC The DAC registers are updated after new data is read in. LDAC can be permanently low or pulsed as in Figure 2. Asynchronous LDAC The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register. The power supply to the AD5629R/AD5669R should be bypassed with 10 µF and 0.1 µF capacitors. The capacitors should be as physically close as possible to the device, with the 0.1 µF capacitor ideally right up against the device. The 10 µF capacitors are the tantalum bead type. It is important that the 0.1 µF capacitor have low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic types of capacitors. This 0.1 µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. Alternatively, the outputs of all DACs can be updated simultaneously using the software LDAC function by writing to Input Register n and updating all DAC registers. Command 0011 is reserved for this software LDAC function. An LDAC register gives the user extra flexibility and control over the hardware LDAC pin. Setting the LDAC bit register to 0 for a DAC channel means that this channel’s update is controlled by the LDAC pin. If this bit is set to 1, this channel updates synchronously; that is, the DAC register is updated after new data is read, regardless of the state of the LDAC pin. It effectively sees the LDAC pin as being tied low. See Table 16 for the LDAC register mode of operation. The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. This flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. Writing to the DAC using command 0110 loads the 8-bit LDAC register (DB7 to DB0). The default for each channel is 0, that is, the LDAC pin works normally. Setting the bits to 1 means the DAC channel is updated regardless of the state of the LDAC pin. See Table 17 for the contents of the input shift register during the load LDAC register mode of operation. Table 16. LDAC Register E A Load DAC Register LDAC Bits (DB7 to DB0) LDAC Pin E LDAC Operation E A A 0 1 A A 1/0 X—don’t care E A A Determined by LDAC pin. DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0. E A A E A E A A A Table 17. 32-Bit Input Shift Register Contents for LDAC Register Function E A A MSB DB23 DB22 DB21 DB20 1 1 0 0 Command bits (C3 to C0) LSB DB19 DB18 DB17 DB16 X X X X Address bits (A3 to A0)— don’t cares DB15 to DB8 X Don’t cares DB7 DAC H Rev. B | Page 27 of 32 DB6 DAC G DB5 DB4 DB3 DB2 DB1 DAC F DAC E DAC D DAC C DAC B Setting LDAC bit to 1 overrides LDAC pin E A E A A A DB0 DAC A AD5629R/AD5669R Data Sheet OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 0.35 0.30 0.25 16 13 0.65 BSC PIN 1 INDICATOR 12 1 EXPOSED PAD 2.70 2.60 SQ 2.50 4 9 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.20 MIN BOTTOM VIEW 08-16-2010-C 0.80 0.75 0.70 5 8 0.45 0.40 0.35 TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. Figure 56. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 57. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. B | Page 28 of 32 0.75 0.60 0.45 Data Sheet AD5629R/AD5669R 2.645 2.605 SQ 2.565 4 3 2 1 A BALL A1 IDENTIFIER B 1.50 REF C D 0.50 REF SEATING PLANE BOTTOM VIEW (BALL SIDE UP) SIDE VIEW COPLANARITY 0.05 0.340 0.320 0.300 0.270 0.240 0.210 Figure 58. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-16) Dimensions shown in millimeters Rev. B | Page 29 of 32 08-16-2011-A 0.650 0.595 0.540 TOP VIEW (BALL SIDE DOWN) AD5629R/AD5669R Data Sheet ORDERING GUIDE Model 1 AD5629RARUZ-1 AD5629RARUZ-1-RL7 AD5629RBRUZ-2 AD5629RBRUZ-2-RL7 AD5629RACPZ-2-RL7 AD5629RACPZ-3-RL7 AD5629RBCPZ-1-RL7 AD5629RBCPZ-2-RL7 AD5629RBCBZ-1-RL7 AD5669RARUZ-1 AD5669RARUZ-1-RL7 AD5669RBRUZ-2 AD5669RBRUZ-2-RL7 AD5669RACPZ-2-RL7 AD5669RACPZ-3-RL7 AD5669RBCPZ-1-RL7 AD5669RBCPZ-2-RL7 AD5669RBCPZ-1500R7 AD5669RBCPZ-2500R7 AD5669RBCBZ-1-RL7 EVAL-AD5629RSDZ EVAL-AD5669RSDZ 15F15F 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead WLCSP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead WLCSP Evaluation Board Evaluation Board Z = RoHS Compliant Part. Rev. B | Page 30 of 32 Package Option RU-16 RU-16 RU-16 RU-16 CP-16-17 CP-16-17 CP-16-17 CP-16-17 CB-16-16 RU-16 RU-16 RU-16 RU-16 CP-16-17 CP-16-17 CP-16-17 CP-16-17 CP-16-17 CP-16-17 CB-16-16 Power-On Reset to Code Zero Zero Zero Zero Zero Midscale Zero Zero Zero Zero Zero Zero Zero Zero Midscale Zero Zero Zero Zero Zero Accuracy ±4 LSB INL ±4 LSB INL ±1 LSB INL ±1 LSB INL ±4 LSB INL ±4 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±32 LSB INL ±32 LSB INL ±16 LSB INL ±16 LSB INL ±32 LSB INL ±32 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL Internal Reference 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 2.5 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 2.5 V 1.25 V 2.5 V 1.25 V Data Sheet AD5629R/AD5669R NOTES Rev. B | Page 31 of 32 AD5629R/AD5669R Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08819-0-2/13(B) Rev. B | Page 32 of 32