2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit nanoDACs® with I2C®-Compatible Interface, Tiny SC70 Package AD5602/AD5612/AD5622 FEATURES FUNCTIONAL BLOCK DIAGRAM Single 8-, 10-, 12-bit DACs, 2 LSB INL 6-lead SC70 package Micropower operation: 100 μA max @ 5 V Power-down to <150 nA @ 3 V 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to 0 V with brownout detection 3 power-down functions I2C-compatible serial interface supports standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes On-chip output buffer amplifier, rail-to-rail operation VDD GND AD5602/AD5612/AD5622 POWER-ON RESET DAC REGISTER INPUT CONTROL LOGIC REF(+) 8-/10-/12-BIT DAC OUTPUT BUFFER POWER-DOWN CONTROL LOGIC VOUT RESISTOR NETWORK Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators ADDR SCL 05446-001 APPLICATIONS SDA Figure 1. Table 1. Related Devices Part No. AD5601/AD5611/AD5621 Description 2.7 V to 5.5 V, <100 μA, 8-, 10-, 12-bit nanoDAC with SPI® interface in a tiny SC70 package GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD5602/AD5612/AD5622, members of the nanoDAC family, are single 8-, 10-, 12-bit buffered voltage-out DACs that operate from a single 2.7 V to 5.5 V supply, consuming <100 μA at 5 V. These DACs come in tiny SC70 packages. Each DAC contains an on-chip precision output amplifier that allows railto-rail output swing to be achieved. 1. Available in a 6-lead SC70 package. 2. Maximum 100 μA power consumption, single-supply operation. These parts operate from a single 2.7 V to 5.5 V supply, typically consuming 0.2 mW at 3 V and 0.4 mW at 5 V, making them ideal for battery-powered applications. The AD5602/AD5612/AD5622 use a 2-wire I2C-compatible serial interface that operates in standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes. 3. The on-chip output buffer amplifier allows the output of the DAC to swing rail-to-rail with a typical slew rate of 0.5 V/μs. The references for AD5602/AD5612/AD5622 are derived from the power supply inputs to give the widest dynamic output range. Each part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place to the device. The parts contain a power-down feature that reduces the current consumption of the devices to <150 nA at 3 V and provides software-selectable output loads while in power-down mode. The parts are put into power-down mode over the serial interface. The low power consumption of the AD5602/AD5612/AD5622 in normal operation makes them ideally suited for use in portable battery-operated equipment. The typical power consumption is 0.4 mW at 5 V. 4. Reference derived from the power supply. 5. Standard, fast, and high speed mode I2C interface. 6. Designed for very low power consumption. 7. Power-down capability. When powered down, the DAC typically consumes <150 nA at 3 V. 8. Power-on reset and brownout detection. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD5602/AD5612/AD5622 TABLE OF CONTENTS Features .............................................................................................. 1 Resistor String............................................................................. 15 Applications....................................................................................... 1 Output Amplifier........................................................................ 15 Functional Block Diagram .............................................................. 1 Serial Interface ................................................................................ 16 General Description ......................................................................... 1 Input Register.............................................................................. 16 Product Highlights ........................................................................... 1 Power-On Reset.......................................................................... 17 Revision History ............................................................................... 2 Power-Down Modes .................................................................. 17 Specifications..................................................................................... 3 Write Operation.......................................................................... 18 I2C Timing Specifications............................................................ 4 Read Operation........................................................................... 19 Timing Diagram ........................................................................... 5 High Speed Mode....................................................................... 20 Absolute Maximum Ratings............................................................ 6 Applications..................................................................................... 21 ESD Caution.................................................................................. 6 Choosing a Reference as Power Supply................................... 21 Pin Configuration and Function Descriptions............................. 7 Bipolar Operation....................................................................... 21 Typical Performance Characteristics ............................................. 8 Power Supply Bypassing and Grounding................................ 21 Terminology .................................................................................... 14 Outline Dimensions ....................................................................... 22 Theory of Operation ...................................................................... 15 Ordering Guide .......................................................................... 23 D/A Section................................................................................. 15 REVISION HISTORY 3/06—Rev. A to Rev. B Changes to Table 2............................................................................ 3 Updates to Outline Dimensions ................................................... 22 Changes to Ordering Guide .......................................................... 23 8/05—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 22 6/05—Revision 0: Initial Version Rev. B | Page 2 of 24 AD5602/AD5612/AD5622 SPECIFICATIONS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE Resolution AD5602 AD5612 AD5622 Relative Accuracy 2 AD5602 AD5612 Min A, B, W, Y Versions 1 Typ Max Bits 0.5 ±0.063 0.5 ±0.0004 5 2 0 6 0.5 470 1000 120 2 Output Noise Spectral Density Noise Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short Circuit Current LOGIC INPUTS (SDA, SCL) IIN, Input Current VINL, Input Low Voltage VINH, Input High Voltage CIN, Pin Capacitance VHYST, Input Hysteresis LOGIC OUTPUTS (OPEN DRAIN) VOL, Output Low Voltage Floating-State Leakage Current Floating-State Output Capacitance Test Conditions/Comments DAC output unloaded 8 10 12 AD5622 Differential Nonlinearity2 Zero Code Error Offset Error Full-Scale Error Gain Error Zero Code Error Drift Gain Temperature Coefficient OUTPUT CHARACTERISTICS 3 Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Unit ±0.5 ±0.5 ±4 ±2 ±6 ±1 10 ±10 ±0.037 VDD 10 5 0.2 0.5 15 LSB LSB LSB LSB LSB LSB mV mV mV % of FSR μV/°C ppm of FSR/°C V μs V/μs pF pF nV/Hz nV-s nV-s Ω mA ±1 0.3 × VDD μA V V pF V 0.4 0.6 ±1 V V μA pF 0.7 × VDD 2 0.1 × VDD 2 Rev. B | Page 3 of 24 B, Y versions B, Y versions A version B, Y versions A, W versions Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register Code ¼ to ¾ RL = ∞ RL = 2 kΩ DAC code = midscale, 10 kHz DAC code = midscale, 0.1 Hz to 10 Hz bandwidth 1 LSB change around major carry VDD = 3 V/5 V ISINK = 3 mA ISINK = 6 mA AD5602/AD5612/AD5622 Parameter POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V POWER EFFICIENCY IOUT/IDD Min A, B, W, Y Versions 1 Typ Max 2.7 Unit Test Conditions/Comments 5.5 V 75 60 100 90 μA μA DAC active and excluding load current VIH = VDD and VIL = GND VIH = VDD and VIL = GND 0.3 0.15 1 1 μA μA VIH = VDD and VIL = GND VIH = VDD and VIL = GND % ILOAD = 2 mA, VDD = 5 V 96 1 Temperature ranges for A, B versions: −40°C to +125°C, typical at 25°C. Linearity calculated using a reduced code range 64 to 4032. 3 Guaranteed by design and characterization, not production tested. 2 I2C TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted. 1 Table 3. Parameter fSCL 3 t1 t2 t3 t4 t5 t6 t7 Conditions Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode Standard mode Limit at TMIN, TMAX Min Max 100 400 3.4 1.7 4 0.6 60 120 4.7 1.3 160 320 250 100 10 0 3.45 0 0.9 0 70 0 150 4.7 0.6 160 4 0.6 160 4.7 Unit KHz KHz MHz MHz μs μs ns ns μs μs ns ns ns ns ns μs μs ns ns μs μs ns μs μs ns μs Fast mode 1.3 μs 2 Rev. B | Page 4 of 24 Description Serial clock frequency tHIGH, SCL high time tLOW, SCL low time tSU;DAT, data setup time tHD;DAT, data hold time tSU;STA, set-up time for a repeated start condition tHD;STA, hold time (repeated) start condition tBUF, bus free time between a stop and a start condition AD5602/AD5612/AD5622 Parameter t8 t9 t10 t11 t11A t12 tSP 4 Conditions2 Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Fast mode High speed mode Limit at TMIN, TMAX Min Max 4 0.6 160 1000 300 10 80 20 160 300 300 10 80 20 160 1000 300 10 40 20 80 1000 Unit μs μs ns ns ns ns ns ns ns ns ns ns ns ns ns ns 300 80 160 300 300 40 80 50 10 10 20 10 20 0 0 ns ns ns ns ns ns ns ns ns Description tSU;STO, setup time for a stop condition tRDA, rise time of SDA signal tFDA, fall time of SDA signal tRCL, rise time of SCL signal tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit tFCL, fall time of SCL signal Pulse width of spike suppressed 1 See Figure 2. High speed mode timing specification applies to the AD5602-1/AD5612-1/AD5622-1 only. Standard and fast mode timing specifications apply to the AD5602-1/AD5612-1/AD5622-1 and AD5602-2/AD5612-2/AD5622-2. 2 CB refers to the capacitance on the bus line. 3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 4 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode. TIMING DIAGRAM t11 t12 t6 t2 SCL t1 t6 t4 t5 t3 t8 t10 t9 t7 P S S Figure 2. 2-Wire Serial Interface Timing Diagram Rev. B | Page 5 of 24 P 05446-002 SDA AD5602/AD5612/AD5622 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND Digital Input Voltage to GND VOUT to GND Operating Temperature Range Extended Automotive (W, Y Versions) Extended Industrial (A, B Versions) Storage Temperature Range Maximum Junction Temperature SC70 Package θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD Rating –0.3 V to + 7.0 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.3 V –40°C to +125°C −40°C to +85°C –65°C to +160°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 332°C/W 120°C/W 215°C 220°C 2.0 kV ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 6 of 24 AD5602/AD5612/AD5622 ADDR 1 SCL 2 SDA 3 AD5602/ AD5612/ AD5622 6 VOUT 5 GND 4 VDD TOP VIEW (Not to Scale) 05446-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 Mnemonic ADDR SCL SDA 4 5 6 VDD GND VOUT Description Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 6). Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input register. Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and VDD should be decoupled to GND. Ground. The ground reference point for all circuitry on the part. Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. Rev. B | Page 7 of 24 AD5602/AD5612/AD5622 TYPICAL PERFORMANCE CHARACTERISTICS 0.05 VDD = 5V TA = 25°C 0.6 0.03 0.4 0.02 0.2 0 –0.2 –0.4 0.01 0 –0.01 –0.02 –0.6 –0.03 –0.8 –0.04 0 500 1000 1500 2000 2500 DAC CODE 3000 3500 4000 –0.05 05446-004 –1.0 Figure 4. Typical AD5622 Integral Nonlinearity Error 0 200 400 600 DAC CODE 800 1000 Figure 7. Typical AD5612 Differential Nonlinearity Error 0.15 0.06 VDD = 5V TA = 25°C 0.10 VDD = 5V TA = 25°C 0.04 DNL ERROR (LSB) INL ERROR (LSB) 0.8 05446-048 1.0 VDD = 5V TA = 25°C 0.04 INL ERROR (LSB) 0 –0.05 –0.10 0 –0.02 –0.04 –0.15 0 500 1000 1500 2000 2500 DAC CODE 3000 3500 4000 –0.06 05446-005 –0.20 0.02 Figure 5. Typical AD5622 Differential Nonlinearity Error 50 100 150 DAC CODE 200 250 Figure 8. Typical AD5602 Integral Nonlinearity Error 0.25 0.015 VDD = 5V TA = 25°C 0.20 0 05446-049 DNL ERROR (LSB) 0.05 VDD = 5V TA = 25°C 0.010 0.15 DNL ERROR (LSB) 0.05 0 –0.05 –0.10 –0.15 0.005 0 –0.005 –0.010 –0.25 0 200 400 600 DAC CODE 800 1000 –0.015 0 50 100 150 DAC CODE 200 Figure 9. Typical AD5602 Differential Nonlinearity Error Figure 6. Typical AD5612 Integral Nonlinearity Error Rev. B | Page 8 of 24 250 05446-050 –0.20 05446-047 INL ERROR (LSB) 0.10 AD5602/AD5612/AD5622 1 0.5 VDD = 5V TA = 25°C 0 TA = 25°C 0.4 0.3 –2 –3 –4 MAX DNL 0.2 0.1 0 –5 –0.1 –6 –0.2 0 500 1000 1500 2000 2500 DAC CODE 3000 3500 4000 –0.3 2.7 05446-006 Figure 10. Typical AD5622 Total Unadjusted Error 3.7 4.2 VDD (V) 4.7 5.2 Figure 13. AD5622 DNL Error vs. Supply 0.5 0.8 TA = 25°C MAX INL 0.6 0.4 0.3 INL ERROR (LSB) 0.4 INL ERROR (LSB) 3.2 0.2 0 –0.2 MAX INL = 5V MAX INL = 3V 0.2 0.1 0 –0.1 –0.4 MIN INL –0.8 2.7 3.2 3.7 4.2 VDD (V) MIN INL = 5V –0.2 4.7 5.2 –0.3 –40 05446-007 –0.6 MIN INL = 3V –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 05446-010 –7 MIN DNL 05446-009 DNL ERROR (LSB) TUE (LSB) –1 Figure 14. AD5622 INL Error vs. Temperature (3 V/5 V Supply) Figure 11. AD5622 INL Error vs. Supply 8 0 TA = 25°C 7 MAX TUE 6 –3 5 TUE (LSB) –2 –4 –5 4 3 MIN TUE –6 MAX TUE = 5V MAX TUE = 3V MIN TUE = 5V 2 –7 –8 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2 Figure 12. AD5622 Total Unadjusted Error vs. Supply MIN TUE = 3V 0 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 05446-011 1 05446-008 TUE (LSB) –1 Figure 15. AD5622 Total Unadjusted Error vs. Temperature (3 V/5 V Supply) Rev. B | Page 9 of 24 AD5602/AD5612/AD5622 0.6 1.8 0.5 1.6 OFFSET ERROR = 3V 0.4 1.4 0.3 1.2 0.2 ERROR (mV) MAX DNL = 3V 0.1 0 –0.1 0.8 0.6 OFFSET ERROR = 5V MIN DNL = 5V 0.4 –0.2 0.2 MIN DNL = 3V –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 0 –40 05446-012 –0.3 –40 1.0 Figure 16. AD5622 DNL Error vs. Temperature (3 V/5 V Supply) –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 05446-015 DNL ERROR (LSB) MAX DNL = 5V Figure 19. Offset Error vs. Temperature (3 V/5 V Supply) 4 0.00025 GAIN ERROR = 3V ZERO CODE ERROR = 3V 2 0.00020 ZERO CODE ERROR = 5V ERROR (%FSR) ERROR (mV) 0 –2 –4 FULL-SCALE ERROR = 3V 0.00015 GAIN ERROR = 5V 0.00010 –6 0.00005 0 20 40 60 TEMPERATURE (°C) 80 100 120 0 –40 0.09 ZERO CODE ERROR TA = 25°C 100 120 TA = 25°C 0.07 IDD (µA) –2 –3 –4 –5 0.06 0.05 0.04 0.03 0.02 FULL-SCALE ERROR –7 0.01 3.2 3.7 4.2 VDD (V) 4.7 5.2 05446-014 ERROR (mV) 80 0.08 –1 –8 2.7 20 40 60 TEMPERATURE (°C) 0.10 1 –6 0 Figure 20. Gain Error vs. Temperature (3 V/5 V Supply) Figure 17. Zero Code/Full-Scale Error vs. Temperature (3 V/5 V Supply) 0 –20 05446-016 –20 Figure 18. Zero Code/Full-Scale Error vs. Supply Voltage 0 2.7 3.2 3.7 4.2 VDD (V) 4.7 Figure 21. Supply Current vs. Supply Voltage Rev. B | Page 10 of 24 5.2 05446-017 –10 –40 FULL-SCALE ERROR = 5V 05446-013 –8 AD5602/AD5612/AD5622 12 0.10 10 0.09 0.08 VDD = 5V VIH = VDD VIL = GND TA = 25°C FREQUENCY 8 0.07 VDD = 5V 0.06 IDD (µA) VDD = 3V VIH = VDD VIL = GND TA = 25°C 0.05 VDD = 3V 6 4 0.04 0.03 2 140 IDD (µA) Figure 22. Supply Current vs. Temperature (3 V/5 V Supply) 05446-021 120 0.05885 0.06648 0.06710 0.06773 0.06835 0.06897 0.06960 0.07022 0.07084 0.07147 0.07209 0.07271 0.07334 100 0.05814 20 40 60 80 TEMPERATURE (°C) 0.05742 0 0.05671 –20 05446-018 0 –40 0.05599 0 0.01 0.05456 0.05527 0.02 Figure 25. IDD Histogram (3 V/5 V Supply) 70 0.8 VDD = 5V TA = 25°C TA = 25°C VDD = 5V 60 0.6 50 0.4 DAC LOADED WITH ZERO-SCALE CODE 0.2 0.0 20 –0.2 10 –0.4 0 0 2000 4000 6000 8000 10000 12000 14000 16000 DAC CODE –0.6 DAC LOADED WITH FULL-SCALE CODE –15 –10 –5 0 5 10 15 I (mA) Figure 23. Supply Current vs. Digital Input Code Figure 26. Sink and Source Capability 900 SCL/SDA INCREASING VDD = 5V 800 VDD = 5V TA = 25°C VDD 700 SCL/SDA DECREASING VDD = 5V 500 CH1 SCL/SDA INCREASING VDD = 3V 400 SCL/SDA DECREASING VDD = 3V 300 VOUT = 70mV 200 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VLOGIC (V) 3.5 4.0 4.5 5.0 Figure 24. Supply Current vs. SCL/SDA Logic Voltage CH2 CH1 = 1V/DIV, CH2 = 20mV/DIV, TIME BASE = 20µs/DIV Figure 27. Power-On Reset to 0 V Rev. B | Page 11 of 24 05446-038 100 05446-020 IDD (µA) 600 05446-037 ΔVO (V) 30 05446-019 IDD (µA) VDD = 3V 40 AD5602/AD5612/AD5622 CH1 VDD CH1 VDD = 5V TA = 25°C VDD = 5V TA = 25°C CH2 CH2 05446-042 CH1 = 5V/DIV, CH2 = 1V/DIV, TIME BASE = 2µs/DIV 05446-039 VOUT CH1 = 1V/DIV, CH2 = 3V/DIV, TIME BASE = 50µs/DIV Figure 28. Exiting Power-Down Mode Figure 31. VOUT vs. VDD 2.458 2.456 2.454 2.452 2.450 2.448 2.446 2.444 2.442 VDD = 5V TA = 25°C LOAD = 2kΩ AND 220pF CODE 0x800 TO 0x7FF 10ns/SAMPLE NUMBER 2.440 CH1 = 5V/DIV, CH2 = 1V/DIV, TIME BASE = 2µs/DIV 2.438 05446-040 CH2 2.436 0 100 400 500 Figure 32. Digital-to-Analog Glitch Impulse Figure 29. Full-Scale Settling Time 2.4278 VDD = 5V TA = 25°C LOAD = 2kΩ AND 220pF 10ns/SAMPLE NUMBER 2.4276 VDD = 5V TA = 25°C 2.4274 AMPLITUDE (V) CH2 2.4272 2.4270 2.4268 2.4266 2.4264 CH1 = 5V/DIV, CH2 = 1V/DIV, TIME BASE = 2µs/DIV 05446-041 2.4262 2.4260 0 100 200 300 SAMPLE NUMBER Figure 33. Digital Feedthrough Figure 30. Half-Scale Settling Time Rev. B | Page 12 of 24 400 500 05446-044 CH1 200 300 SAMPLE NUMBER 05446-043 AMPLITUDE (V) CH1 VDD = 5V TA = 25°C AD5602/AD5612/AD5622 CH1 = 5µV/DIV 05446-045 CH1 600 VDD = 5V TA = 25°C UNLOADED OUTPUT 500 400 ZERO SCALE 300 200 FULL SCALE 100 0 100 Figure 34. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth MIDSCALE 1000 10000 FREQUENCY (Hz) Figure 35. Output Noise Spectral Density Rev. B | Page 13 of 24 100000 05446-046 MIDSCALE LOADED OUTPUT NOISE SPECTRAL DENSITY (nV/ Hz) 700 VDD = 5V TA = 25°C AD5602/AD5612/AD5622 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 4. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 5. Zero Code Error Zero-code error is due to a combination of the offset errors in the DAC and output amplifier; it is a measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5602/AD5612/AD5622 because the output of the DAC cannot go below 0 V. Zero-code error is expressed in mV. A plot of zero-code error vs. temperature can be seen in Figure 17. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded to the DAC register; it is expressed in percent of full-scale range. Ideally, the output should be VDD – 1 LSB. A plot of full-scale error vs. temperature can be seen in Figure 17. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Total Unadjusted Error (TUE) Total unadjusted error is a measure of the output error taking all the various errors into account. A typical TUE vs. code plot can be seen in Figure 10. Zero Code Error Drift Zero code error drift is a measure of the change in zero code error with a change in temperature. It is expressed in μV/°C. Gain Error Drift Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 32). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa (see Figure 33). Rev. B | Page 14 of 24 AD5602/AD5612/AD5622 THEORY OF OPERATION D/A SECTION R The AD5602/AD5612/AD5622 DACs are fabricated on a CMOS process. The architecture consists of a string DACs followed by an output buffer amplifier. Figure 36 shows a block diagram of the DAC architecture. R VDD TO OUTPUT AMPLIFIER R REF (+) RESISTOR NETWORK REF (–) VOUT OUTPUT AMPLIFIER 05446-022 DAC REGISTER GND R Figure 36. DAC Architecture Since the input coding to the DAC is straight binary, the ideal output voltage is given by 05446-023 R ⎛ D⎞ VOUT = V DD × ⎜ n ⎟ ⎝2 ⎠ Figure 37. Resistor String Structure OUTPUT AMPLIFIER where: D is the decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 255 (AD5602), 0 to 1023 (AD5612), or 0 to 4095 (AD5622). n is the bit resolution of the DAC. The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 26. The slew rate is 0.5 V/μs with a halfscale settling time of 5 μs with the output unloaded. RESISTOR STRING The resistor string structure is shown in Figure 37. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Rev. B | Page 15 of 24 AD5602/AD5612/AD5622 SERIAL INTERFACE The AD5602/AD5612/AD5622 have 2-wire I2C-compatible serial interfaces (refer to I2C-Bus Specification, Version 2.1, January 2000, available from Philips Semiconductor). The AD5602/AD5612/AD5622 can be connected to an I2C bus as a slave device, under the control of a master device. See Figure 2 for a timing diagram of a typical write sequence. 3. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition. Table 6. Device Address Selection The AD5602/AD5612/AD5622 support standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. ADDR GND VDD NC (No Connection) The AD5602/AD5612/AD5622 each have a 7-bit slave address. The five MSBs are 00011 and the two LSBs are determined by the state of the ADDR pin. The facility to make hardwired changes to ADDR allows the user to incorporate up to three of these devices on one bus as outlined in Table 6. The master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave address corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. 2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. The input register is 16 bits wide. Figure 38, Figure 39, and Figure 40 illustrate the contents of the input register for each part. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCL. The timing diagram for this operation is shown in Figure 2. The 16-bit word consists of four control bits followed by 8, 10, or 12 bits of data, depending on the device type. MSB (DB15) is loaded first. The first two bits are reserved bits that must be set to zero, the next two bits are control bits that select the mode of operation of the device (normal mode or any one of three power-down modes). See the Power-Down Modes section for a complete description. The remaining bits are left-justified DAC data bits, starting with the MSB and ending with the LSB. DB15 (MSB) 0 DB0 (LSB) PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 05446-024 0 A0 1 0 0 INPUT REGISTER The 2-wire serial bus protocol operates as follows: 1. A1 1 0 1 DATA BITS Figure 38. AD5602 Input Register Contents DB15 (MSB) 0 PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 05446-025 0 DB0 (LSB) DATA BITS Figure 39. AD5612 Input Register Contents 0 0 DB0 (LSB) PD1 PD0 D11 D10 D9 D8 D7 D6 D5 DATA BITS Figure 40. AD5622 Input Register Contents Rev. B | Page 16 of 24 D4 D3 D2 D1 D0 05446-026 DB15 (MSB) AD5602/AD5612/AD5622 POWER-ON RESET The AD5602/AD5612/AD5622 each contain a power-on reset circuit that controls the output voltage during power-up. The DAC register is filled with zeros and the output voltage is 0 V where it remains until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the DAC output while it is in the process of powering up. POWER-DOWN MODES The AD5602/AD5612/AD5622 each contain four separate modes of operation. These modes are software-programmable by setting Bit PD1 and Bit PD0 in the control register. Table 7 shows how the state of the bits corresponds to the mode of operation of the device. When both bits are set to 0, the part works normally with its usual power consumption of 100 μA maximum at 5 V. However, for the three power-down modes, the supply current falls to <150 nA (at 3 V). Not only does the supply current fall, but the output stage is internally switched from the output of the amplifier to a resistor network of known values. This gives the advantage of knowing the output impedance of the part while the part is in power-down mode. There are three different options. The output is connected internally to GND through a 1 kΩ resistor, a 100 kΩ resistor, or it is left open-circuited (three-state). Figure 41 shows the output stage. RESISTOR STRING DAC AMPLIFIER VOUT PD0 0 1 0 1 Operating Mode Normal operation Power-down (1 kΩ load to GND) Power-down (100 kΩ load to GND) Power-down (Three-state output) POWER-DOWN CIRCUITRY RESISTOR NETWORK 05446-027 Table 7. Modes of Operation PD1 0 0 1 1 Figure 41. Output Stage During Power-Down The bias generator, output amplifier, resistor string, and other associated linear circuitry are all shut down when the powerdown mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 14 μs for VDD = 5 V and 17 μs for VDD = 3 V (see Figure 28). Rev. B | Page 17 of 24 AD5602/AD5612/AD5622 Two bytes of data are then written to the DAC, the most significant byte followed by the least significant byte as shown in Figure 39; both of these data bytes are acknowledged by the AD5602/AD5612/AD5622. A stop condition follows. The write operations for the three DACs are shown in Figure 42, Figure 43, and Figure 44. WRITE OPERATION When writing to the AD5602/AD5612/AD5622, the user must begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. 1 9 1 9 SCL SDA 0 0 0 1 1 A1 A0 R/W START BY MASTER 0 0 PD1 PD0 D7 D6 D5 D4 ACK. BY AD5602 ACK. BY AD5602 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 MOST SIGNIFICANT DATA BYTE 1 9 9 SCL (CONTINUED) D3 D2 D1 D0 X X X X ACK. BY AD5602 STOP BY MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE 05446-028 SDA (CONTINUED) Figure 42. AD5602 Write Sequence 1 9 1 9 SCL SDA 0 0 0 1 1 A1 A0 R/W START BY MASTER 0 0 PD1 PD0 D9 D8 D7 D6 ACK. BY AD5612 ACK. BY AD5612 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 MOST SIGNIFICANT DATA BYTE 1 9 9 SCL (CONTINUED) D5 D4 D3 D2 D1 D0 X X ACK. BY AD5612 STOP BY MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE 05446-029 SDA (CONTINUED) Figure 43. AD5612 Write Sequence 1 9 1 9 SCL 0 0 0 1 1 A1 A0 R/W START BY MASTER 0 0 PD1 PD0 D11 D10 D9 D8 ACK. BY AD5622 ACK. BY AD5622 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 MOST SIGNIFICANT DATA BYTE 9 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY AD5622 FRAME 3 LEAST SIGNIFICANT DATA BYTE Figure 44. AD5622 Write Sequence Rev. B | Page 18 of 24 STOP BY MASTER 05446-030 SDA AD5602/AD5612/AD5622 READ OPERATION prepared to transmit data by pulling SDA low. Two bytes of data are then read from the DAC, which are both acknowledged by the master as shown in Figure 45, Figure 46, and Figure 47. A stop condition follows. When reading data back from the AD5602/AD5612/AD5622, the user begins with a start command followed by an address byte (R/W = 1), after which the DAC acknowledges that it is 1 9 1 9 SCL SDA 0 0 0 1 1 A1 A0 START BY MASTER R/W PD1 PD0 D7 D6 D5 D4 D3 D2 ACK. BY AD5602 ACK. BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 MOST SIGNIFICANT DATA BYTE FROM AD5602 1 9 SCL (CONTINUED) D1 D0 0 0 0 0 0 0 NO ACK. BY STOP BY MASTER MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE FROM AD5602 05446-031 SDA (CONTINUED) Figure 45. AD5602 Read Sequence 1 9 1 9 SCL SDA 0 0 0 1 1 A1 A0 START BY MASTER R/W PD1 ACK. BY AD5612 PD0 D9 D8 D7 D6 D5 D4 ACK. BY MASTER FRAME 2 MOST SIGNIFICANT DATA BYTE FROM AD5612 FRAME 1 SERIAL BUS ADDRESS BYTE 1 9 SCL (CONTINUED) D3 D2 D1 D0 0 0 0 0 NO ACK. BY STOP BY MASTER MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE FROM AD5612 05446-032 SDA (CONTINUED) Figure 46. AD5612 Read Sequence 1 9 1 9 SCL 0 0 0 1 1 A1 START BY MASTER A0 R/W PD1 ACK. BY AD5622 PD0 D11 D10 D9 D8 D7 D6 ACK. BY MASTER FRAME 2 MOST SIGNIFICANT DATA BYTE FROM AD5622 FRAME 1 SERIAL BUS ADDRESS BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) D5 D4 D3 D2 D1 D0 0 0 NO ACK. BY STOP BY MASTER MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE FROM AD5622 Figure 47. AD5622 Read Sequence Rev. B | Page 19 of 24 05446-033 SDA AD5602/AD5612/AD5622 followed by a no acknowledge. The master must then issue a repeated start followed by the device address. The selected device then acknowledges its address. All devices continue to operate in high speed mode until the master issues a stop condition. When the stop condition is issued, the devices return to standard/fast mode. HIGH SPEED MODE High speed mode communication commences after the master addresses all devices connected to the bus with the Master Code 00001XXX to indicate that a high speed mode transfer is to begin. No device connected to the bus is permitted to acknowledge the high speed master code, therefore, the code is FAST MODE 1 9 HIGH-SPEED MODE 1 9 SCL 0 0 0 0 1 X START BY MASTER X X 0 NACK. 0 0 1 1 A1 SR HS-MODE MASTER CODE R/W ACK. BY AD56x2 SERIAL BUS ADDRESS BYTE Figure 48. Placing the AD5602/AD5612/AD5622 into High Speed Mode Rev. B | Page 20 of 24 A0 05446-034 SDA AD5602/AD5612/AD5622 APPLICATIONS CHOOSING A REFERENCE AS POWER SUPPLY With VDD = 5 V, R1 = R2 = 10 kΩ Because the supply current required by the AD5602/AD5612/ AD5622 DACs is extremely low, they are ideal for low supply applications. The ADR293 voltage reference is recommended in this case. This requires 15 μA of quiescent current and can therefore drive multiple DACs in the one system, if required. ⎛ 10 × D ⎞ VO = ⎜ ⎟−5 V n ⎝ 2 ⎠ This is an output voltage range of ±5 V with 0x000 corresponding to a −5 V output, and 0xFFF corresponding to a +5 V output. R2 10kΩ +5V R1 10kΩ +5V AD820/ OP295 VDD 10µF 0.1µF AD5602/ AD5612/ AD5622 ±5V OUT VOUT –5V SDA SCL 7V ADR425 05446-036 The AD5602/AD5612/AD5622 come in tiny SC70 packages with less than 100 μA supply current, thereby making the choice of reference dependent upon the application requirement. For space-saving applications, the ADR425 is available in an SC70 package with excellent drift at 3ppm/°C. It also provides very good noise performance at 3.4 μV p-p in the 0.1 Hz to 10 Hz range. Figure 50. Bipolar Operation with the AD5602/AD5612/AD5622 5V POWER SUPPLY BYPASSING AND GROUNDING SCL SDA VOUT = 0V TO 5V 05446-035 AD5602/ AD5612/ AD5622 Figure 49. ADR425 as Power Supply Examples of some recommended precision references for use as supplies to the AD5602/AD5612/AD5622 are shown in Table 8. Table 8. Recommended Precision References Part No. ADR435 ADR425 ADR02 ADR395 Initial Accuracy (mV max) ±6 ±6 ±5 ±6 Temperature Drift (ppm/°C max) 3 3 3 25 0.1 Hz to 10 Hz Noise (μV p-p typ) 3.4 3.4 15 5 BIPOLAR OPERATION The AD5602/AD5612/AD5622 have been designed for singlesupply operation, but a bipolar output range is also possible using the circuit in Figure 50. The circuit in Figure 50 gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as ⎡ ⎛ D ⎞ ⎛ R1 + R2 ⎞ ⎛ R2 ⎞⎤ VO = ⎢VDD × ⎜ n ⎟ × ⎜ ⎟ − VDD × ⎜ ⎟⎥ ⎝ 2 ⎠ ⎝ R1 ⎠ ⎝ R1 ⎠⎦ ⎣ where: D represents the input code in decimal. n represents the bit resolution of the DAC. When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5602/ AD5612/AD5622 should have separate analog and digital sections, each having its own area of the board. If the AD5602, AD5612, or AD5622 is in a system where other devices require an AGND to DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5602/AD5612/AD5622. The power supply to the AD5602/AD5612/AD5622 should be bypassed with 10 μF and 0.1 μF capacitors. The capacitors should be physically as close as possible to the device with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitors are the tantalum bead type. It is important that the 0.1 μF capacitor has low effective series resistance (ESR) and effective series inductance (ESI), such as common ceramic types. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, the microstrip technique is not always possible with a 2-layer board. Rev. B | Page 21 of 24 AD5602/AD5612/AD5622 OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 1.25 1.15 6 5 4 1 2 3 2.40 2.10 1.80 PIN 1 0.65 BSC 1.30 BSC 1.00 0.90 0.70 0.10 MAX 1.10 0.80 0.30 0.15 0.40 0.10 SEATING PLANE 0.22 0.08 0.46 0.36 0.26 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 51. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters Rev. B | Page 22 of 24 AD5602/AD5612/AD5622 ORDERING GUIDE Model AD5602YKSZ-1500RL71 INL (max) ±0.5 LSB AD5602YKSZ-1REEL71 ±0.5 LSB AD5602BKSZ-2500RL71 AD5602BKSZ-2REEL71 AD5602YKSZ-2500RL71 AD5602YKSZ-2REEL71 AD5612YKSZ-1500RL71 ±0.5 LSB ±0.5 LSB ±0.5 LSB ±0.5 LSB ±0.5 LSB AD5612YKSZ-1REEL71 ±0.5 LSB AD5612BKSZ-2500RL71 AD5612BKSZ-2REEL71 AD5612AKSZ-2500RL71 AD5612AKSZ-2REEL71 AD5612YKSZ-2500RL71 AD5612YKSZ-2REEL71 AD5622YKSZ-1500RL71 ±0.5 LSB ±0.5 LSB ±4 LSB ±4 LSB ±0.5 LSB ±0.5 LSB ±2 LSB AD5622YKSZ-1REEL71 ±2 LSB AD5622BKSZ-2500RL71 AD5622BKSZ-2REEL71 AD5622YKSZ-2500RL71 AD5622YKSZ-2REEL71 AD5622WKSZ-1500RL71 ±2 LSB ±2 LSB ±2 LSB ±2 LSB ±6 LSB AD5622WKSZ-1REEL71 ±6 LSB AD5622AKSZ-2500RL71 AD5622AKSZ-2REEL71 ±6 LSB ±6 LSB 1 I2C Interface Modes Supported Standard, fast and high speed Standard, fast and high speed Standard, fast Standard, fast Standard, fast Standard, fast Standard, fast, and high speed Standard, fast, and high speed Standard, fast Standard, fast Standard, fast Standard, fast Standard, fast Standard, fast Standard, fast, and high speed Standard, fast, and high speed Standard, fast Standard, fast Standard, fast Standard, fast Standard, fast, and high speed Standard, fast, and high speed Standard, fast Standard, fast Temperature Range −40°C to +125°C Power Supply Range 2.7 V to 5.5 V Package Option KS-6 Package Description 6-Lead SC70 Branding D5W −40°C to +125°C 2.7 V to 5.5 V KS-6 6-Lead SC70 D5W −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +125°C 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V KS-6 KS-6 KS-6 KS-6 KS-6 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 D5X D5X D5Y D5Y D5T −40°C to +125°C 2.7 V to 5.5 V KS-6 6-Lead SC70 D5T −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +125°C 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 D5U D5U D60 D60 D5S D5S D5M −40°C to +125°C 2.7 V to 5.5 V KS-6 6-Lead SC70 D5M −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +125°C 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V KS-6 KS-6 KS-6 KS-6 KS-6 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 D5N D5N D5P D5P D5Q −40°C to +125°C 2.7 V to 5.5 V KS-6 6-Lead SC70 D5Q −40°C to +85°C −40°C to +85°C 2.7 V to 5.5 V 2.7 V to 5.5 V KS-6 KS-6 6-Lead SC70 6-Lead SC70 D5R D5R Z = Pb-free part. Rev. B | Page 23 of 24 AD5602/AD5612/AD5622 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05446-0-3/06(B) Rev. B | Page 24 of 24