AD5672R/AD5676R (Rev. A)

Octal, 12-/16-Bit nanoDAC+ with
2 ppm/°C Reference, SPI Interface
AD5672R/AD5676R
Data Sheet
FEATURES
GENERAL DESCRIPTION
High performance
High relative accuracy (INL): ±3 LSB maximum at 16 bits
Total unadjusted error (TUE): ±0.14% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.06% of FSR maximum
Low drift 2.5 V reference: 2 ppm/°C typical
Wide operating ranges
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply
Easy implementation
User selectable gain of 1 or 2 (GAIN pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Robust 2 kV HBM and 1.5 kV FICDM ESD rating
20-lead, TSSOP RoHS-compliant package
The AD5672R/AD5676R are low power, octal, 12-/16-bit
buffered voltage output digital-to-analog converters (DACs).
They include a 2.5 V, 2 ppm/°C internal reference (enabled by
default) and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). The devices operate from a single
2.7 V to 5.5 V supply and are guaranteed monotonic by design.
The AD5672R/AD5676R are available in a 20-lead TSSOP package
and incorporate a power-on reset circuit and a RSTSEL pin that
ensures that the DAC outputs power up to zero scale or midscale
and remain there until a valid write. The AD5672R/AD5676R
contain a power-down mode, reducing the current consumption to
1 µA typical while in power-down mode.
Table 1. Octal nanoDAC+® Devices
Interface
SPI
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Data acquisition systems
Reference
Internal
External
Internal
I2C
16-Bit
AD5676R
AD5676
AD5675R
12-Bit
AD5672R
Not applicable
AD5671R
PRODUCT HIGHLIGHTS
1.
2.
High Relative Accuracy (INL).
AD5672R (12-bit): ±1 LSB maximum.
AD5676R (16-bit): ±3 LSB maximum.
Low Drift, 2.5 V On-Chip Reference.
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFOUT
AD5672R/AD5676R
2.5V
REF
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 1
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 2
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 3
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 4
SDO
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 5
LDAC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 6
RESET
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 7
SYNC
SDI
INTERFACE LOGIC
SCLK
BUFFER
VOUT0
BUFFER
VOUT1
BUFFER
VOUT2
BUFFER
VOUT3
BUFFER
VOUT4
BUFFER
VOUT5
BUFFER
VOUT6
BUFFER
VOUT7
GAIN
×1/×2
POWER-ON
RESET
RSTSEL
GAIN
POWER-DOWN
LOGIC
GND
11954-001
VLOGIC
Figure 1.
Rev. A
Document Feedback
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Technical Support
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AD5672R/AD5676R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Write and Update Commands .................................................. 26 Applications ....................................................................................... 1 Daisy-Chain Operation ............................................................. 26 General Description ......................................................................... 1 Readback Operation .................................................................. 27 Product Highlights ........................................................................... 1 Power-Down Operation ............................................................ 27 Functional Block Diagram .............................................................. 1 Load DAC (Hardware LDAC Pin) ........................................... 28 Revision History ............................................................................... 2 LDAC Mask Register ................................................................. 28 Specifications..................................................................................... 3 Hardware Reset (RESET) .......................................................... 29 AD5672R Specifications .............................................................. 3 Reset Select Pin (RSTSEL) ........................................................ 29 AD5676R Specifications .............................................................. 5 Internal Reference Setup ........................................................... 29 AC Characteristics........................................................................ 7 Solder Heat Reflow..................................................................... 29 Timing Characteristics ................................................................ 8 Long-Term Temperature Drift ................................................. 29 Daisy-Chain and Readback Timing Characteristics ............... 9 Thermal Hysteresis .................................................................... 30 Absolute Maximum Ratings.......................................................... 11 Applications Information .............................................................. 31 ESD Caution ................................................................................ 11 Power Supply Recommendations............................................. 31 Pin Configuration and Function Descriptions ........................... 12 Microprocessor Interfacing ....................................................... 31 Typical Performance Characteristics ........................................... 13 AD5672R/AD5676R to ADSP-BF531 Interface ..................... 31 Terminology .................................................................................... 22 AD5672R/AD5676R to SPORT Interface ............................... 31 Theory of Operation ...................................................................... 24 Layout Guidelines....................................................................... 31 Digital-to-Analog Converter .................................................... 24 Galvanically Isolated Interface ................................................. 32 Transfer Function ....................................................................... 24 Outline Dimensions ....................................................................... 33 DAC Architecture ....................................................................... 24 Ordering Guide .......................................................................... 33 Serial Interface ............................................................................ 25 Standalone Operation ................................................................ 26 REVISION HISTORY
2/15—Rev. 0 to Rev. A
Added AD5672R Specifications Section ....................................... 3
Changes to Table 2 ............................................................................ 3
Added AD5676R Specifications Section and Table 3;
Renumbered Sequentially................................................................ 5
Change to RESET Pulse Activation Parameter, Table 5 .............. 8
Change to Terminology Section ................................................... 22
Changes to Transfer Function Section and Output Amplifiers
Section .............................................................................................. 24
Changes to Hardware Reset (RESET) Section ............................ 29
Changes to Ordering Guide .......................................................... 33
10/14—Revision 0: Initial Version
Rev. A | Page 2 of 33
Data Sheet
AD5672R/AD5676R
SPECIFICATIONS
AD5672R SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications TA = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE 1
Resolution
Relative Accuracy (INL)
Min
Zero Code Error
Offset Error
Full-Scale Error
Gain Error
TUE
Offset Error Drift 2
DC Power Supply Rejection Ratio (PSRR)2
DC Crosstalk2
Short-Circuit Current 4
Load Impedance at Rails 5
Power-Up Time
REFERENCE OUTPUT
Output Voltage 6
Reference Temperature Coefficient 7, 8
Output Impedance2
Output Voltage Noise2
Output Voltage Noise Density2
Load Regulation Sourcing2
Load Regulation Sinking2
Output Current Load Capability2
Line Regulation2
Long-Term Stability/Drift2
Thermal Hysteresis2
±0.12
±0.12
±0.01
±0.01
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
±0.03
±0.006
±1
0.25
±2
±3
±2
±1
±1
±0.1
±0.1
1.6
±2
±1.5
±0.14
±0.07
±0.12
±0.06
±0.18
±0.14
0
0
Output Current Drive
Capacitive Load Stability
Resistive Load 3
Load Regulation
Max
12
Differential Nonlinearity (DNL)
OUTPUT CHARACTERISTICS2
Output Voltage Range
Typ
2.5
5
15
Unit
Bits
LSB
LSB
LSB
LSB
mV
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
mV/V
µV
µV/mA
µV
183
V
V
mA
nF
nF
kΩ
µV/mA
177
µV/mA
40
25
2.5
mA
Ω
µs
2
10
1
2.4975
2
0.04
13
240
2.5025
5
29
74
±20
43
12
125
25
V
ppm/°C
Ω
µV p-p
nV/√Hz
µV/mA
µV/mA
mA
µV/V
ppm
ppm
ppm
Rev. A | Page 3 of 33
Test Conditions/Comments
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1 or gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
DAC code = midscale, VDD = 5 V ± 10%
Due to single channel, full-scale output change
Due to load current change
Due to powering down (per channel)
Gain = 1
Gain = 2
RL = ∞
RL = 1 kΩ
VDD = 5 V ± 10%, DAC code = midscale,
−30 mA ≤ IOUT ≤ +30 mA
VDD = 3 V ± 10%, DAC code = midscale,
−20 mA ≤ IOUT ≤ +20 mA
Exiting power-down mode, VDD = 5 V
See the Terminology section
0.1 Hz to 10 Hz
At ambient temperature, f = 10 kHz, CL = 10 nF,
gain = 1 or 2
At ambient temperature
At ambient temperature
VDD ≥ 3 V
At ambient temperature
After 1000 hours at 125°C
First cycle
Additional cycles
AD5672R/AD5676R
Parameter
LOGIC INPUTS2
Input Current
Input Voltage
Low, VINL
High, VINH
Pin Capacitance
LOGIC OUTPUTS (SDO)2
Output Voltage
Low, VOL
High, VOH
Floating State Output Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
Data Sheet
Min
Typ
Max
Unit
Test Conditions/Comments
±1
µA
Per pin
0.3 × VLOGIC
V
V
pF
0.4
V
V
pF
5.5
1
1.3
0.5
1.3
5.5
5.5
V
µA
µA
µA
µA
V
V
1.26
2.0
1.3
2.1
1.7
1.7
2.5
2.5
5.5
5.5
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
0.7 × VLOGIC
3
VLOGIC − 0.4
4
1.8
2.7
VREF + 1.5
IDD
Normal Mode 9
All Power-Down Modes 10
1.1
1.8
1.1
1.8
1
1
1
1
1
1
ISINK = 200 μA
ISOURCE = 200 μA
Power-on, −40°C to +105°C
Power-on, −40°C to +125°C
Power-down, −40°C to +105°C
Power-down, −40°C to +125°C
Gain = 1
Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off, −40°C to +85°C
Internal reference on, −40°C to +85°C
Internal reference off
Internal reference on
Tristate to 1 kΩ, −40°C to +85°C
Power down to 1 kΩ, −40°Cto +85°C
Tristate, −40°C to +105°C
Power down to 1 kΩ, −40°C to +105°C
Tristate to 1 kΩ, −40°C to +125°C
Power down to 1 kΩ, −40°C to +125°C
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 12 to 4080.
2
Guaranteed by design and characterization; not production tested.
3
Together, Channel 0, Channel 1, Channel 2, and Channel 3 can source/sink 40 mA. Similarly, together, Channel 4, Channel 5, Channel 6, and Channel 7 can source/sink
40 mA up to a junction temperature of 125°C.
4
VDD = 5 V. The devices include current limiting intended to protect the devices during temporary overload conditions. Junction temperature can be exceeded during
current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
5
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
6
Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
7
Reference is trimmed and tested at two temperatures and is characterized from −40°C to +125°C.
8
Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
9
Interface inactive. All DACs active. DAC outputs unloaded.
10
All DACs powered down.
1
Rev. A | Page 4 of 33
Data Sheet
AD5672R/AD5676R
AD5676R SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications TA = −40°C to +125°C, unless otherwise noted.
Table 3.
Parameter
STATIC PERFORMANCE 1
Resolution
Relative Accuracy (INL)
Min
Full-Scale Error
Gain Error
TUE
Offset Error Drift 2
DC Power Supply Rejection
Ratio (PSRR)2
DC Crosstalk2
Short-Circuit Current 4
Load Impedance at Rails 5
Power-Up Time
REFERENCE OUTPUT
Output Voltage 6
Reference Temperature
Coefficient 7, 8
Output Impedance2
Output Voltage Noise2
Output Voltage Noise Density2
Load Regulation Sourcing2
Load Regulation Sinking2
Output Current Load
Capability2
Line Regulation2
Long-Term Stability/Drift2
Thermal Hysteresis2
B Grade
Typ
Max
±8
±8
±1
±1
3
±6
±4
±0.28
±0.14
±0.24
±0.12
±0.3
±0.25
±1.8
±1.7
±0.7
±0.5
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
±0.03
±0.006
±1
0.25
±3
±3
±1
±1
1.6
±2
±1.5
±0.14
±0.07
±0.12
±0.06
±0.18
±0.14
Unit
Bits
LSB
LSB
LSB
LSB
mV
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
mV/V
±2
±2
µV
±3
±2
±3
±2
µV/mA
µV
0
0
Output Current Drive
Capacitive Load Stability
Min
16
±1.8
±1.7
±0.7
±0.5
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
±0.03
±0.006
±1
0.25
Zero Code Error
Offset Error
Resistive Load 3
Load Regulation
Max
16
Differential Nonlinearity (DNL)
OUTPUT CHARACTERISTICS2
Output Voltage Range
A Grade
Typ
2.5
5
15
0
0
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1 or gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
DAC code = midscale, VDD = 5 V ±
10%
Due to single channel, full-scale
output change
Due to load current change
Due to powering down (per channel)
183
183
V
V
mA
nF
nF
kΩ
µV/mA
177
177
µV/mA
40
25
2.5
40
25
2.5
mA
Ω
µs
Exiting power-down mode, VDD = 5 V
V
ppm/°C
See the Terminology section
2
10
2.5
5
15
Test Conditions/Comments
2
10
1
1
2.4975
5
2.5025
20
2.4975
2
2.5025
5
Gain = 1
Gain = 2
RL = ∞
RL = 1 kΩ
VDD = 5 V ± 10%, DAC code =
midscale, −30 mA ≤ IOUT ≤ +30 mA
VDD = 3 V ± 10%, DAC code =
midscale, −20 mA ≤ IOUT ≤ +20 mA
0.04
13
240
0.04
13
240
Ω
µV p-p
nV/√Hz
29
74
±20
29
74
±20
µV/mA
µV/mA
mA
0.1 Hz to 10 Hz
At ambient temperature, f = 10 kHz,
CL = 10 nF, gain = 1 or 2
At ambient temperature
At ambient temperature
VDD ≥ 3 V
43
12
125
25
43
12
125
25
µV/V
ppm
ppm
ppm
At ambient temperature
After 1000 hours at 125°C
First cycle
Additional cycles
Rev. A | Page 5 of 33
AD5672R/AD5676R
Parameter
LOGIC INPUTS2
Input Current
Input Voltage
Low, VINL
High, VINH
Pin Capacitance
LOGIC OUTPUTS (SDO)2
Output Voltage
Low, VOL
High, VOH
Floating State Output
Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
Data Sheet
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Unit
Test Conditions/Comments
±1
±1
µA
Per pin
0.3 ×
VLOGIC
0.3 ×
VLOGIC
V
0.7 ×
VLOGIC
0.7 ×
VLOGIC
3
V
3
0.4
VLOGIC −
0.4
pF
0.4
VLOGIC −
0.4
4
1.8
4
5.5
1
1.3
0.5
1.3
5.5
5.5
2.7
VREF +
1.5
1.8
V
µA
µA
µA
µA
V
V
IDD
Normal Mode 9
All Power-Down Modes 10
ISINK = 200 μA
ISOURCE = 200 μA
pF
5.5
1
1.3
0.5
1.3
5.5
5.5
2.7
VREF +
1.5
V
V
1.1
1.26
1.1
1.26
mA
1.8
2.0
1.8
2.0
mA
1.1
1.8
1
1
1
1
1.3
2.1
1.7
1.7
2.5
2.5
1.1
1.8
1
1
1
1
1.3
2.1
1.7
1.7
2.5
2.5
mA
mA
µA
µA
µA
µA
1
1
5.5
5.5
1
1
5.5
5.5
µA
µA
Power-on, −40°C to +105°C
Power-on, −40°C to +125°C
Power-down, −40°C to +105°C
Power-down, −40°C to +125°C
Gain = 1
Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to
5.5 V
Internal reference off, −40°C to
+85°C
Internal reference on, −40°C to
+85°C
Internal reference off
Internal reference on
Tristate to 1 kΩ, −40°C to +85°C
Power down to 1 kΩ, −40°C to +85°C
Tristate, −40°C to +105°C
Power down to 1 kΩ, −40°C to
+105°C
Tristate to 1 kΩ, −40°C to +125°C
Power down to 1 kΩ, −40°C to
+125°C
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.
Guaranteed by design and characterization; not production tested.
3
Together, Channel 0, Channel 1, Channel 2, and Channel 3 can source/sink 40 mA. Similarly, together, Channel 4, Channel 5, Channel 6, and Channel 7 can source/sink
40 mA up to a junction temperature of 125°C.
4
VDD = 5 V. The devices include current limiting intended to protect the devices during temporary overload conditions. Junction temperature can be exceeded during
current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
5
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
6
Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
7
Reference is trimmed and tested at two temperatures and is characterized from −40°C to +125°C.
8
Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
9
Interface inactive. All DACs active. DAC outputs unloaded.
10
All DACs powered down.
1
2
Rev. A | Page 6 of 33
Data Sheet
AD5672R/AD5676R
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND,all specifications TA = −40°C to +125°C, unless
otherwise noted. Guaranteed by design and characterization, not production tested.
Table 4.
Parameter
OUTPUT VOLTAGE SETTLING TIME 2
AD5672R
AD5676R
SLEW RATE
DIGITAL-TO-ANALOG GLITCH IMPULSE2
DIGITAL FEEDTHROUGH2
CROSSTALK2
Digital
Analog
DAC-to-DAC
TOTAL HARMONIC DISTORTION 3
OUTPUT NOISE SPECTRAL DENSITY2
OUTPUT NOISE2
SIGNAL-TO-NOISE RATIO (SNR)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
SIGNAL-TO-NOISE-AND-DISTORTION
RATIO (SINAD)
Min
Typ
Max
Unit
Test Conditions/Comments 1
5
5
0.8
1.4
0.13
8
8
µs
µs
V/µs
nV-sec
nV-sec
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
0.1
−0.25
−1.3
−2.0
−80
300
6
90
83
80
nV-sec
nV-sec
nV-sec
nV-sec
dB
nV/√Hz
µV p-p
dB
dB
dB
1 LSB change around major carry (internal reference, gain = 1)
Internal reference, gain = 2
Internal reference, gain = 2
At TA, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz, gain = 2
0.1 Hz to 10 Hz, gain = 1
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
The operating temperature range is −40°C to +125°C; TA = 25°C.
See the Terminology section. Measured using internal reference and gain = 1, unless otherwise noted.
3
Digitally generated sine wave at 1 kHz.
1
2
Rev. A | Page 7 of 33
AD5672R/AD5676R
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, and VREFIN = 2.5 V. All specifications −40°C to +125°C, unless otherwise noted.
Table 5.
Parameter1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single, Combined, or All Channel Update)
SYNC Falling Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
SCLK Falling Edge to LDAC Falling Edge
RESET Minimum Pulse Width Low
RESET Pulse Activation Time
Power-Up Time2
2
1.8 V ≤ VLOGIC < 2.7 V
Min
Max
20
4
4.5
15.1
0.8
0.1
0.95
9.65
4.75
4.85
41.25
26.35
4.8
132
5.15
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
20
1.7
4.3
10.1
0.8
−0.8
1.25
6.75
9.7
5.45
25
20.3
6.2
80
5.18
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Time to exit power-down to normal mode of AD5672R/AD5676R operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
t9
t1
SCLK
t8
t3
t4
t2
t7
SYNC
t5
SDI
t6
DB23
DB0
t12
t10
LDAC1
t11
LDAC2
RESET
VOUT
t13
t14
11954-002
1
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. A | Page 8 of 33
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
Data Sheet
AD5672R/AD5676R
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and
Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V. All specifications −40°C to +125°C, unless otherwise noted.
Table 6.
Parameter 1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SDO Data Valid from SCLK Rising Edge
SCLK Falling Edge to SYNC Rising Edge
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t10
t11
1.8 V ≤ VLOGIC < 2.7 V
Min
Max
120
33
2.8
75
1.2
0.3
16.2
55.1
21.5
24.4
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
83.3
25.3
3.25
50
0.5
0.4
13
45
22.7
20.3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYNC Rising Edge to SCLK Rising Edge
t12
85.5
54
ns
1
Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit Diagram and Daisy-Chain and Readback Timing Diagrams
200µA
VOH (MIN)
CL
20pF
200µA
11954-003
TO OUTPUT
PIN
IOL
IOH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
SCLK
24
48
t11
t8
t12
t4
SYNC
SDI
t6
DB23
DB0
INPUT WORD FOR DAC N
DB23
DB0
t10
INPUT WORD FOR DAC N + 1
DB23
SDO
UNDEFINED
DB0
INPUT WORD FOR DAC N
Figure 4. Daisy-Chain Timing Diagram
Rev. A | Page 9 of 33
11954-004
t5
AD5672R/AD5676R
Data Sheet
t1
SCLK
24
1
t8
t4
t3
24
1
t7
t2
SYNC
t6
t5
DB23
DB0
DB23
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
DB23
DB0
NOP CONDITION
t10
DB0
DB0
DB23
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 5. Readback Timing Diagram
Rev. A | Page 10 of 33
11954-005
SDI
Data Sheet
AD5672R/AD5676R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 7.
Parameter
VDD to GND
VLOGIC to GND
VOUTx to GND
VREFOUT to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
20-Lead TSSOP, θJA Thermal Impedance,
Zero Airflow (4-Layer Board)
Reflow Soldering Peak Temperature,
Pb Free (J-STD-020)
ESD
Human Body Model (HBM)
Field Induced Charged Device Model
(FICDM)
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +125°C
−65°C to +150°C
125°C
112.6°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
260°C
2 kV
1.5 kV
Rev. A | Page 11 of 33
AD5672R/AD5676R
Data Sheet
VOUT1
1
20
VOUT2
VOUT0
2
19
VOUT3
VDD
3
18
VREFOUT
VLOGIC
4
17
RESET
SYNC
5
16
SDO
SCLK
6
15
LDAC
SDI
7
14
RSTSEL
GAIN
8
13
GND
VOUT7
9
12
VOUT4
VOUT6 10
11
VOUT5
AD5672R/
AD5676R
TOP VIEW
(Not to Scale)
11954-006
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 6. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
VOUT1
VOUT0
VDD
4
5
VLOGIC
SYNC
6
SCLK
7
SDI
8
GAIN
9
10
11
12
13
14
VOUT7
VOUT6
VOUT5
VOUT4
GND
RSTSEL
15
LDAC
16
SDO
17
RESET
18
19
20
VREFOUT
VOUT3
VOUT2
Description
Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
Power Supply Input. These devices operate from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 μF capacitor in
parallel with a 0.1 μF capacitor to GND.
Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data
transfers in on the falling edges of the next 24 clocks.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
transfers at rates of up to 50 MHz.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of
the serial clock input.
Span Set Pin. When this pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. If this pin is tied to
VLOGIC, all eight DACs output a span of 0 V to 2 × VREF.
Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Device.
Power-On Reset Pin. Tie this pin to GND to power up all eight DACs to zero scale. Tie this pin to VLOGIC to power up
all eight DACs to midscale.
Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all
DAC registers to be updated if the input registers have new data, which allows all DAC outputs to simultaneously
update. This pin can also be tied permanently low.
Serial Data Output. This pin can be used to daisy-chain a number of devices together, or it can be used for
readback. The serial data transfers on the rising edge of SCLK and is valid on the falling edge.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored.
When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending
on the state of the RSTSEL pin.
Reference Output Voltage. When using the internal reference, this is the reference output pin.
Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
Rev. A | Page 12 of 33
Data Sheet
AD5672R/AD5676R
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
2.0
0.8
1.5
0.6
DNL ERROR (LSB)
INL ERROR (LSB)
1.0
0.5
0
–0.5
0.4
0.2
0
–0.2
–0.4
–1.0
11954-007
–2.0
0
10000
20000
30000
40000
50000
60000
11954-010
–0.6
–1.5
–0.8
–1.0
70000
0
1000
500
1500
2000
2500
3000
3500
4000
CODE
CODE
Figure 7. AD5676R INL Error vs. Code
Figure 10. AD5672R DNL Error vs. Code
0.04
2.0
1.5
0.03
TUE (% OF FSR)
INL ERROR (LSB)
1.0
0.5
0
–0.5
0.02
0.01
0
–1.0
11954-008
–2.0
0
500
1000
1500
2000 2500
CODE
3000
3500
11954-011
–0.01
–1.5
–0.02
4000
0
10000
Figure 8. AD5672R INL Error vs. Code
20000
30000
40000
CODE
50000
60000
70000
Figure 11. AD5676R TUE vs. Code
0.04
1.0
0.8
0.03
TUE (% of FSR)
0.4
0.2
0
–0.2
0.02
0.01
0
–0.4
–0.6
–0.8
–1.0
0
10000
20000
30000
40000
CODE
50000
60000
11954-012
–0.01
11954-009
DNL ERROR (LSB)
0.6
–0.02
0
70000
Figure 9. AD5676R DNL Error vs. Code
500
1000
1500
2000 2500
CODE
3000
Figure 12. AD5672R TUE vs. Code
Rev. A | Page 13 of 33
3500
4000
Data Sheet
10
10
8
8
6
6
4
4
DNL ERROR (LSB)
2
0
–2
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–2
0
–20
20
40
–6
11954-013
–8
–10
–40
0
–4
–4
–6
2
60
80
100
–8
–10
–40
120
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–20
0
10
0.10
8
0.09
6
0.08
4
0.07
2
0
–2
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0.04
0
–40
5.2
4
0.07
TUE (% OF FSR)
0.08
2
0
–2
40
60
80
100
120
100
120
0.05
0.04
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0.02
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
40
20
0.06
0.03
–4
11954-015
DNL ERROR (LSB)
6
20
0
Figure 17. AD5676R TUE vs. Temperature
0.09
0
–20
TEMPERATURE (°C)
8
–20
11954-017
11954-014
3.7
4.2
4.7
SUPPLY VOLTAGE (V)
0.01
0.10
–8
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0.02
10
–10
–40
120
0.05
Figure 14. AD5672R INL Error vs. Supply Voltage
–6
100
60
80
100
11954-018
3.2
80
0.06
0.03
–4
–10
2.7
60
Figure 16. AD5672R DNL Error vs. Temperature
TUE (% OF FSR)
INL ERROR (LSB)
Figure 13. AD5676R INL Error vs. Temperature
–8
40
TEMPERATURE (°C)
TEMPERATURE (°C)
–6
20
11954-016
INL ERROR (LSB)
AD5672R/AD5676R
0.01
0
–40
120
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. AD5672R TUE vs. Temperature
Figure 15. AD5676R DNL Error vs. Temperature
Rev. A | Page 14 of 33
AD5672R/AD5676R
10
0.10
8
0.08
6
0.06
4
0.04
TUE (% OF FSR)
2
0
–2
–4
–0.02
3.2
3.7
4.2
–0.06
4.7
–0.08
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–0.10
2.7
5.2
3.7
3.2
SUPPLY VOLTAGE (V)
0.08
6
0.06
4
0.04
TUE (% OF FSR)
DNL ERROR (LSB)
0.10
8
2
0
–2
–4
0.02
0
–0.02
–0.04
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
3.2
3.7
4.2
–0.06
11954-027
–10
2.7
4.7
–0.08
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–0.10
2.7
5.2
3.2
3.7
SUPPLY VOLTAGE (V)
0.08
6
0.06
4
0.04
ERROR (% OF FSR)
8
2
0
–2
–4
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
3.2
3.7
4.2
5.2
0.02
FULL-SCALE ERROR
0
GAIN ERROR
–0.02
–0.04
–0.06
11954-028
DNL ERROR (LSB)
0.10
–10
2.7
4.7
Figure 23. AD5672R TUE vs. Supply Voltage
10
–8
4.2
SUPPLY VOLTAGE (V)
Figure 20. AD5676R DNL Error vs. Supply Voltage
–6
5.2
4.7
Figure 22. AD5676R TUE vs. Supply Voltage
10
–8
4.2
SUPPLY VOLTAGE (V)
Figure 19. AD5676R INL Error vs. Supply Voltage
–6
11954-029
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
11954-030
–8
–10
2.7
0
–0.04
11954-025
–6
0.02
4.7
–0.08
–0.10
–40
5.2
SUPPLY VOLTAGE (V)
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–20
0
20
40
11954-031
INL ERROR (LSB)
Data Sheet
60
80
100
120
TEMPERATURE (°C)
Figure 21. AD5672R DNL Error vs. Supply Voltage
Figure 24. AD5676R Gain Error and Full-Scale Error vs. Temperature
Rev. A | Page 15 of 33
AD5672R/AD5676R
Data Sheet
0.10
1.8
0.08
1.5
0.06
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
ERROR (mV)
ERROR (% OF FSR)
1.2
0.04
0.02
0
GAIN ERROR
–0.02
ZERO CODE ERROR
0.9
0.6
OFFSET ERROR
0.3
FULL-SCALE ERROR
–0.04
0
–0.10
–40
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0
–20
20
40
–0.3
60
80
100
–0.6
–40
120
11954-035
–0.08
11954-032
–0.06
–20
0
TEMPERATURE (°C)
0.10
1.8
0.08
1.5
120
1.2
ERROR (mV)
0.02
GAIN ERROR
0
–0.02
FULL-SCALE ERROR
–0.04
ZERO CODE ERROR
0.9
OFFSET ERROR
0.6
0.3
0
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
3.2
3.7
4.2
–0.3
4.7
–0.6
–40
5.2
11954-036
–0.10
2.7
100
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0.04
11954-033
ERROR (% OF FSR)
0.06
–0.08
80
Figure 28. AD5676R Zero Code Error and Offset Error vs. Temperature
Figure 25. AD5672R Gain Error and Full-Scale Error vs. Temperature
–0.06
20
40
60
TEMPERATURE (°C)
–20
0
SUPPLY VOLTAGE (V)
Figure 26. AD5676R Gain Error and Full-Scale Error vs. Supply Voltage
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 29. AD5672R Zero Code Error and Offset Error vs. Temperature
0.10
1.5
0.08
1.0
0.04
ERROR (mV)
GAIN ERROR
–0.02
FULL-SCALE ERROR
–0.04
–0.08
–0.10
2.7
–0.5
–1.0
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
3.2
3.7
4.2
OFFSET ERROR
0
4.7
–1.5
2.7
5.2
SUPPLY VOLTAGE (V)
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
3.2
3.7
4.2
11954-037
0
–0.06
ZERO CODE ERROR
0.5
0.02
11954-034
ERROR (% OF FSR)
0.06
4.7
5.2
SUPPLY VOLTAGE (V)
Figure 27. AD5672R Gain Error and Full-Scale Error vs. Supply Voltage
Figure 30. AD5676R Zero Code Error and Offset Error vs. Supply Voltage
Rev. A | Page 16 of 33
Data Sheet
AD5672R/AD5676R
6
1.5
0xFFFF
5
1.0
ZERO CODE ERROR
4
0xC000
3
VOUT (V)
ERROR (mV)
0.5
OFFSET ERROR
0
0x8000
2
0x4000
1
–0.5
0x0000
0
–1.5
2.7
3.2
4.2
3.7
–1
11954-038
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
4.7
–2
–0.06
5.2
11954-042
–1.0
–0.04
–0.02
0.02
0.04
0.06
Figure 34. Source and Sink Capability at 5 V
Figure 31. AD5672R Zero Code Error and Offset Error vs. Supply Voltage
4.0
70
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
60
3.5
3.0
50
0xFFFF
2.5
VOUT (V)
HITS
0
LOAD CURRENT (A)
SUPPLY VOLTAGE (V)
40
30
2.0
0xC000
1.5
0x8000
1.0
0x4000
0.5
20
0x0000
11954-039
–0.5
–1.0
–0.06
1895
1880
1865
1850
1835
1820
1790
1805
1775
1745
1760
1730
1715
1700
0
11954-043
0
10
–0.04
–0.02
0
0.02
LOAD CURRENT (A)
0.04
0.06
IDD FULL SCALE (µA)
Figure 35. Source and Sink Capability at 3 V
Figure 32. Supply Current (IDD) Histogram with Internal Reference
1.6
1.4
SINKING, VDD = –2.7V
SINKING, VDD = –3.0V
SINKING, VDD = –5.0V
SOURCING, VDD = –5.0V
SOURCING, VDD = –3.0V
SOURCING, VDD = –2.7V
1.0
IDD (mA)
1.4
0.2
–0.2
1.3
1.2
–0.6
–1.4
0
0.005
0.010
0.015
0.020
0.025
11954-044
1.1
–1.0
11954-041
ΔVOUT (V)
0.6
U1284
U1285
U1286
1.5
1.0
0
0.030
LOAD CURRENT (A)
10000
20000
30000
40000
CODE
50000
Figure 36. Supply Current (IDD) vs. Code
Figure 33. Headroom/Footroom (ΔVOUT) vs. Load Current
Rev. A | Page 17 of 33
60000
70000
AD5672R/AD5676R
Data Sheet
2.0
2.0
1.8
1.8
FULL-SCALE
1.6
1.6
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 5
DAC 7
DAC 8
1.4
ZERO CODE
1.2
1.0
VOUT (V)
IDD (mA)
1.4
1.2
1.0
0.8
EXTERNAL REFERENCE, FULL-SCALE
0.6
0.4
0
20
40
60
80
100
0
80
120
100
120
TEMPERATURE (°C)
Figure 37. Supply Current (IDD) vs. Temperature
2.0
1.8
5
1.6
VDD (V)
IDD (mA)
ZERO CODE
3
2
EXTERNAL REFERENCE, FULL-SCALE
0.8
11954-046
0.6
3.2
3.7
4.2
200
0.005
VDD (V)
VOUT0 (V)
VOUT1 (V)
VOUT2 (V)
VOUT3 (V)
VOUT4 (V)
VOUT5 (V)
VOUT6 (V)
VOUT7 (V)
4
FULL-SCALE
0.4
2.7
180
0.006
1.4
1.0
160
Figure 40. Full-Scale Settling Time
6
1.2
140
TIME (µs)
4.7
0.004
0.003
0.002
1
0.001
0
0
–1
5.2
0
2
VOUT (V)
–20
0.2
4
6
8
–0.001
10
TIME (ms)
SUPPLY VOLTAGE (V)
Figure 38. Supply Current (IDD) vs. Supply Voltage
Figure 41. Power-On Reset to 0 V and Midscale
2.2
3.0
2.0
MIDSCALE, GAIN = 2
2.5
FULL-SCALE
1.8
VOUT (V)
2.0
1.4
ZERO CODE
1.2
1.0
EXTERNAL REFERENCE, FULL-SCALE
1.5
MIDSCALE, GAIN = 1
1.0
0.5
0.6
0.4
2.7
3.2
3.7
4.2
4.7
0
–5
5.2
SUPPLY VOLTAGE (V)
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
0
5
TIME (µs)
Figure 42. Exiting Power-Down to Midscale
Figure 39. Supply Current (IDD) vs. Zero Code and Full Scale
Rev. A | Page 18 of 33
10
11954-050
0.8
11954-047
IDD (mA)
1.6
11954-049
0.4
–40
11954-045
0.6
VDD = 5.5V
GAIN = +1
INTERNAL REFERENCE = 2.5V
1/4 TO 3/4 SCALE
11954-048
0.8
Data Sheet
AD5672R/AD5676R
0.004
0.003
0.002
1
VOUT (V)
0.001
0
–0.003
–0.004
15
16
17
18
19
20
21
11954-054
VDD = 5V
GAIN = 1
TD = 25°C
REFERENCE = 2.5V
CODE = 7FFF TO 8000
ENERGY = 1.209376nV-s
–0.002
11954-051
–0.001
2
CH1 50.0mV
22
M1.00s
A CH1
401mV
TIME (µs)
Figure 43. Digital-to-Analog Glitch Impulse
Figure 46. 0.1 Hz to 10 Hz Output Noise
0.003
1200
VDD = 5V
TA = 25°C
GAIN = 1
INTERNAL REFERENCE = 2.5V
0.002
1000
0.001
800
NSD (nV/√Hz)
VOUT (V)
0
–0.001
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
–0.002
–0.003
–0.004
FULL SCALE
MID SCALE
ZERO SCALE
600
400
11954-052
–0.006
0
2
4
6
8
10
12
14
16
18
11954-055
200
–0.005
0
10
20
100
1k
10k
FREQUENCY (Hz)
TIME (µs)
1M
Figure 47. Noise Spectral Density (NSD)
Figure 44. Analog Crosstalk
0
0.012
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
0.010
0.008
0.006
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–20
–40
–60
THD (dBV)
0.004
0.002
0
–0.002
–80
–100
–120
–0.004
–140
–0.006
–0.008
–0.010
0
2
4
6
8
10
12
14
16
18
–160
11954-056
11954-053
VOUT (V)
100k
–180
0
20
2
4
6
8
10
12
14
16
18
FREQUENCY (kHz)
TIME (µs)
Figure 45. DAC-to-DAC Crosstalk
Figure 48. Total Harmonic Distortion (THD) at 1 kHz
Rev. A | Page 19 of 33
20
AD5672R/AD5676R
Data Sheet
2.0
1600
1.8
CL = 0nF
CL = 0.1nF
CL = 1nF
CL = 4.7nF
CL = 10nF
VOUT (V)
1.7
1.6
1.5
1.4
1.3
11954-057
1.2
1.1
1.0
0.10
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
1400
1200
VDD = 5V
TA = 25°C
1000
800
600
400
200
11954–061
INTERNAL REFERENCE NSD (nV/√Hz)
1.9
0
10
0.20
1k
100
TIME (ms)
Figure 49. Settling Time vs. Capacitive Load
1M
Figure 52. Internal Reference NSD vs. Frequency
2.0
2.5020
1.8
2.5015
DEVICE1
DEVICE2
DEVICE3
DEVICE4
DEVICE5
1.6
2.5010
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
DAC 8
1.2
1.0
0.8
2.5005
VREF (V)
1.4
VOUT (V)
100k
10k
FREQUENCY (Hz)
2.5000
2.4995
0.6
2.4990
0.4
0
80
100
120
140
160
180
2.4980
–40
200
TIME (µs)
0.2
RESET
MIDSCALE,MIDSCALE,
GAINGAIN
= 1= 1
VOUT AT ZS (V)
2
0.1
1
ZERO SCALE, GAIN = 1
40
TIME (µs)
0
60
11954-059
VOUT AT MS (V)
0.3
20
0
20
40
60
80
100
120
Figure 53. Internal Reference Voltage (VREF) vs. Temperature (A Grade)
3
0
–20
TEMPERATURE (°C)
Figure 50. Settling Time, 5.5 V
0
–20
11954-062
2.4985
11954-058
0.2
Figure 51. Hardware Reset
Rev. A | Page 20 of 33
Data Sheet
AD5672R/AD5676R
2.5020
2.50050
TA = 25°C
DEVICE1
DEVICE2
DEVICE3
DEVICE4
DEVICE5
2.5015
2.5010
2.50045
2.5000
2.50025
2.4990
2.50020
2.4985
2.50015
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
2.5035
VDD = 5V
TA = 25°C
2.5025
2.5020
2.5015
2.5010
2.5005
11954-064
2.5000
2.4995
–0.035
–0.025
–0.015
–0.005
0.005
0.015
LOAD CURRENT (A)
2.50010
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
Figure 54. Internal Reference Voltage (VREF) vs. Temperature (B Grade)
VREF (V)
DEVICE3
2.4995
2.4980
–40
DEVICE2
2.50030
11954-065
VREF (V)
2.50035
11954-063
VREF (V)
2.5005
2.5030
DEVICE1
2.50040
0.025
0.035
Figure 55. Internal Reference Voltage (VREF) vs. Load Current and Supply
Voltage (VDD)
Rev. A | Page 21 of 33
Figure 56. Internal Reference Voltage (VREF) vs. Supply Voltage (VDD)
AD5672R/AD5676R
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function.
Output Voltage Settling Time
The output voltage settling time is the amount of time it takes
for the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change and is measured from the rising edge
of SYNC.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. These DACs are guaranteed monotonic
by design.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000).
Zero Code Error
Zero code error is a measurement of the output error when zero
code (0x0000) is loaded to the DAC register. The ideal output is
0 V. The zero code error is always positive because the output of
the DAC cannot go below 0 V due to a combination of the offset
errors in the DAC and the output amplifier. Zero code error is
expressed in mV.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Full-Scale Error
Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. The ideal
output is VDD − 1 LSB. Full-scale error is expressed in percent of
full-scale range (% of FSR).
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % of FSR.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured with Code 256
loaded in the DAC register. It can be negative or positive.
DC Power Supply Rejection Ratio (PSRR)
The dc power supply rejection ratio indicates how the output of
the DAC is affected by changes in the supply voltage. PSRR is
the ratio of the change in VOUT to a change in VDD for full-scale
output of the DAC. It is measured in mV/V. VREF is held at 2 V,
and VDD is varied by ±10%.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Noise Spectral Density
Noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nV/√Hz). It is measured by loading the DAC
to midscale and measuring noise at the output. It is measured in
nV/√Hz.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in μV.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has on
another DAC kept at midscale. It is expressed in μV/mA.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-sec.
Rev. A | Page 22 of 33
Data Sheet
AD5672R/AD5676R
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by first loading one of the input registers with a fullscale code change (all 0s to all 1s and vice versa). Then, execute
a software LDAC and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-sec.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by
loading the attack channel with a full-scale code change (all 0s
to all 1s and vice versa), using the write to and update commands
while monitoring the output of the victim channel that is at
midscale. The energy of the glitch is expressed in nV-sec.
Multiplying Bandwidth
The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Voltage Reference Temperature Coefficient (TC)
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given temperature range expressed in ppm/°C, as follows:
 V

V
TC   REF( MAX) REF( MIN)   106
VREF(NOM)  Temp Range
where:
VREF (MAX) is the maximum reference output measured over the
total temperature range.
VREF (MIN) is the minimum reference output measured over the
total temperature range.
VREF (NOM) is the nominal reference output voltage, 2.5 V.
Temp Range is the specified temperature range of −40°C to
+125°C.
Rev. A | Page 23 of 33
AD5672R/AD5676R
Data Sheet
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
VREF
The AD5672R/AD5676R are octal, 12-/16-bit, serial input,
voltage output DACs with an internal reference. The devices
operate from supply voltages of 2.7 V to 5.5 V. Data is written to
the AD5672R/AD5676R in a 24-bit word format via a 3-wire
serial interface. The AD5672R/AD5676R incorporate a poweron reset circuit to ensure that the DAC output powers up to a
known output state. The devices also have a software powerdown mode that reduces the typical current consumption to 1 µA.
R
R
R
TO OUTPUT
AMPLIFIER
TRANSFER FUNCTION
The internal reference is on by default.
R
The gain of the output amplifier is set to 1 by default. This can
be set to ×1 or ×2 using the gain select pin (GAIN). When this
pin is tied to GND, all eight DAC outputs have a span from 0 V
to VREF. If this pin is tied to VLOGIC, all eight DACs output a span
of 0 V to 2 × VREF.
11954-067
R
Figure 58. Resistor String Structure
DAC ARCHITECTURE
Internal Reference
The AD5672R/AD5676R implement a segmented string DAC
architecture with an internal output buffer. Figure 57 shows the
internal block diagram.
The AD5672R/AD5676R on-chip reference is enabled at powerup, but can be disabled via a write to the control register. See the
Internal Reference Setup section for details.
The AD5672R/AD5676R have a 2.5 V, 2 ppm/°C reference,
giving a full-scale output of 2.5 V or 5 V, depending on the state
of the GAIN pin. The internal reference associated with the
device is available at the VREFOUT pin. This buffered reference is
capable of driving external loads of up to 15 mA.
VREF
2.5V
REF
REF (+)
DAC
REGISTER
RESISTOR
STRING
REF (–)
GND
VOUTX
GAIN
(GAIN = 1 OR 2)
Output Amplifiers
11954-066
INPUT
REGISTER
Figure 57. Single DAC Channel Architecture Block Diagram
The resistor string structure is shown in Figure 58. The code
loaded to the DAC register determines the node on the string
where the voltage is tapped off and fed into the output amplifier.
The voltage is tapped off by closing one of the switches and
connecting the string to the amplifier. Because each resistance
in the string has same value, R, the string DAC is guaranteed
monotonic.
The output buffer amplifier generates rail-to-rail voltages on its
output, which gives an output range of 0 V to VREF. The actual
range depends on the value of VREF, the GAIN pin, the offset
error, and the gain error. The GAIN pin selects the gain of the
output. If the GAIN pin is tied to GND, all eight outputs have a
gain of 1, and the output range is 0 V to VREF. If the GAIN pin is
tied to VLOGIC, all eight outputs have a gain of 2, and the output
range is 0 V to 2 × VREF.
These can drive a load of 1 kΩ in parallel with 10 nF to GND.
The slew rate is 0.8 V/µs with a typical ¼ to ¾ scale settling
time of 5 µs.
Rev. A | Page 24 of 33
Data Sheet
AD5672R/AD5676R
SERIAL INTERFACE
Table 9. Command Definitions
The AD5672R/AD5676R use a 3-wire serial interface (SYNC,
SCLK, and SDI that is compatible with SPI, QSPI™, and
MICROWIRE interface standards, as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence. The
AD5672R/AD5676R contain an SDO pin to allow the user to
daisy-chain multiple devices together (see the Daisy-Chain
Operation section) or for readback.
C3
0
0
Input Shift Register
The input shift register of the AD5672R/AD5676R is 24 bits
wide. Data is loaded MSB first (DB23), and the first four bits are
the command bits, C3 to C0 (see Table 9), followed by the 4-bit
DAC address bits, A3 to A0 (see Table 10), and finally, the bit
data-word.
The data-word comprises 12-bit or 16-bit input code, followed by
zero or four don’t care bits for the AD5676R and AD5672R,
respectively (see Figure 59 and Figure 60). These data bits are
transferred to the input register on the 24 falling edges of SCLK
and are updated on the rising edge of SYNC.
Commands execute on individual DAC channels, combined DAC
channels, or on all DACs, depending on the address bits selected.
Command
C2 C1 C0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
1
1
…
1
1
…
1
0
…
1
0
…
1
Description
No operation
Write to Input Register n where n = 1 to 8,
depending on the DAC selected from the
address bits in Table 10 (dependent
on LDAC)
Update DAC Register n with contents of
Input Register n
Write to and update DAC Channel n
Power down/power up the DAC
Hardware LDAC mask register
Software reset (power-on reset)
Internal reference setup register
Set up the DCEN register (daisy-chain
enable)
Set up the readback register (readback
enable)
Update all channels of the input register
simultaneously with the input data
Update all channels of the DAC register
and input register simultaneously with
the input data
Reserved
Reserved
Table 10. Address Commands
A3
0
0
0
0
0
0
0
0
A0
0
1
0
1
0
1
0
1
Selected Channel1
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
Any combination of DAC channels can be selected using the address bits.
DB23 (MSB)
C3
C2
DB0 (LSB)
C1
C0
A3
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
DATA BITS
ADDRESS BITS
11954-068
COMMAND BITS
Figure 59. AD5672R Input Shift Register Content
DB23 (MSB)
C3
C2
DB0 (LSB)
C1
C0
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
COMMAND BITS
ADDRESS BITS
11954-069
1
Channel Address[3:0]
A1
0
0
1
1
0
0
1
1
A2
0
0
0
0
1
1
1
1
Figure 60. AD5676R Input Shift Register Content
Rev. A | Page 25 of 33
AD5672R/AD5676R
Data Sheet
STANDALONE OPERATION
68HC11*
Bring the SYNC line low to begin the write sequence. Data from
the SDI line is clocked into the 24-bit input shift register on the
falling edge of SCLK. After the last of 24 data bits is clocked in,
bring SYNC high. The programmed function is then executed,
that is, an LDAC-dependent change in DAC register contents
and/or a change in the mode of operation. If SYNC is taken
high at a clock before the 24th clock, it is considered a valid
frame, and invalid data may be loaded to the DAC. Bring SYNC
high for a minimum of 20 ns (single channel, see t8 in Figure 2)
before the next write sequence so that a falling edge of SYNC
can initiate the next write sequence. Idle SYNC at rails between
write sequences for even lower power operation. The SYNC line
is kept low for 24 falling edges of SCLK, and the DAC is
updated on the rising edge of SYNC.
MOSI
SDI
SCK
SCLK
PC7
SYNC
PC6
LDAC
SDO
MISO
SDI
AD5672R/
AD5676R
SCLK
SYNC
LDAC
SDO
When data is transferred into the input register of the addressed
DAC, all DAC registers and outputs update by taking LDAC low
while the SYNC line is high.
SDI
AD5672R/
AD5676R
SCLK
WRITE AND UPDATE COMMANDS
SYNC
Write to Input Register n (Dependent on LDAC)
Update DAC Register n with Contents of Input Register n
Command 0010 loads the DAC registers and outputs with the
contents of the input registers selected and updates the DAC
outputs directly.
Write to and Update DAC Channel n (Independent of LDAC)
Command 0011 allows the user to write to the DAC registers
and updates the DAC outputs directly.
DAISY-CHAIN OPERATION
For systems that contain several DACs, the SDO pin can daisychain several devices together and is enabled through a software
executable daisy-chain enable (DCEN) command. Command
1000 is reserved for this DCEN function (see Table 9). The
daisy-chain mode is enabled by setting Bit DB0 in the DCEN
register. The default setting is standalone mode, where DB0 = 0.
Table 11 shows how the state of the bit corresponds to the mode
of operation of the device.
SDO
11954-070
LDAC
Command 0001 allows the user to write the dedicated input
register of each DAC individually. When LDAC is low, the input
register is transparent, if not controlled by the LDAC mask
register.
Figure 61. Daisy-Chaining the AD5672R/AD5676R
The SCLK pin is continuously applied to the input shift register
when SYNC is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting this line to the
SDI input on the next DAC in the chain, a daisy-chain interface is
constructed. Each DAC in the system requires 24 clock pulses.
Therefore, the total number of clock cycles must equal 24 × N,
where N is the total number of devices updated. If SYNC is
taken high at a clock that is not a multiple of 24, it is considered
a valid frame, and invalid data may be loaded to the DAC.
When the serial transfer to all devices is complete, SYNC goes
high, which latches the input data in each device in the daisy
chain and prevents any further data from being clocked into the
input shift register. The serial clock can be continuous or a gated
clock. If SYNC is held low for the correct number of clock
cycles, a continuous SCLK source is used. In gated clock mode,
use a burst clock containing the exact number of clock cycles,
and take SYNC high after the final clock to latch the data.
Table 11. Daisy-Chain Enable (DCEN) Register
DB0
0
1
AD5672R/
AD5676R
Description
Standalone mode (default)
DCEN mode
Rev. A | Page 26 of 33
Data Sheet
AD5672R/AD5676R
READBACK OPERATION
Table 12. Modes of Operation
Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisychain mode disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
disabled again. Command 1001 is reserved for the readback
function. This command, in association with selecting one of
address bits, DAC A to DAC D, selects the register to read. Note
that, during readback, only one DAC register can be selected.
Set the remaining three address bits to Logic 0. The remaining
data bits in the write sequence are don’t care bits. If more than
one or no bits are selected, DAC Channel 0 is read back by
default. During the next SPI write, the data appearing on the
SDO output contains the data from the previously addressed
register.
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
Tristate
1.
2.
PD0
0
0
1
1
1
When both Bit PD1 and Bit PD0 in the input shift register are set
to 0, the device works normally with its normal power
consumption of typically 1 mA at 5 V. However, for the two
power-down modes, the supply current falls to typically 1 µA.
In addition to this fall, the output stage switches internally from
the amplifier output to a resistor network of known values. This
has the advantage that the output impedance of the devices are
known while the devices are in power-down mode. There are
two different power-down options. The output is connected
internally to GND through either a 1 kΩ resistor, or it is left
open-circuited (tristate). The output stage is shown in Figure 62.
Write 0x900000 to the AD5672R/AD5676R input register.
This configures the device for read mode with the DAC
register of Channel 0 selected. Note that all data bits, DB15
to DB0, are don’t care bits.
Follow this with a second write, a no operation (NOP)
condition, 0x000000. During this write, the data from the
register is clocked out on the SDO line. DB23 to DB20
contain undefined data, and the last 16 bits contain the
DB19 to DB4 DAC register contents.
DAC
AMPLIFIER
POWER-DOWN
CIRCUITRY
VOUT
RESISTOR
NETWORK
11954-071
For example, to read back the DAC register for Channel 0,
implement the following sequence:
PD1
0
Figure 62. Output Stage During Power-Down
POWER-DOWN OPERATION
The AD5672R/AD5676R contain two separate power-down
modes. Command 0100 is designated for the power-down
function (see Table 9). These power-down modes are software
programmable by setting 16 bits, Bit DB15 to Bit DB0, in the
input shift register. There are two bits associated with each DAC
channel. Table 12 shows how the state of the two bits corresponds
to the mode of operation of the device.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry shut down when power-down mode is
activated. However, the contents of the DAC register are
unaffected when in power-down. The DAC register updates
while the device is in power-down mode. The time required to
exit power-down is typically 2.5 µs for VDD = 5 V.
To reduce the current consumption further, power off the on-chip
reference. See the Internal Reference Setup section.
Any or all DACs (DAC A to DAC D) power down to the
selected mode by setting the corresponding bits. See Table 13
for the contents of the input shift register during the powerdown/power-up operation.
Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation
[DB23:DB20]
0100
1
DB19
0
[DB18:DB16]
XXX1
DAC 7
[DB15: B14]
[PD1:PD0]
DAC 6
[DB13: B12]
[PD1:PD0]
DAC 5
[DB11: B10]
[PD1:PD0]
DAC 4
[DB9:DB8]
[PD1:PD0]
X means don’t care.
Rev. A | Page 27 of 33
DAC 3
[DB7:DB6]
[PD1:PD0]
DAC 2
[DB5:DB4]
[PD1:PD0]
DAC 1
[DB3:DB2]
[PD1:PD0]
DAC 0
[DB1:DB0]
[PD1:PD0]
AD5672R/AD5676R
Data Sheet
LOAD DAC (HARDWARE LDAC PIN)
Deferred DAC Updating (LDAC is Pulsed Low)
The AD5672R/AD5676R DACs have double buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The user can write to any combination of the input
registers. Updates to the DAC register are controlled by the
LDAC pin.
LDAC is held high while data is clocked into the input register
using Command 0001. All DAC outputs are asynchronously
updated by taking LDAC low after SYNC is taken high. The
update now occurs on the falling edge of LDAC.
Instantaneous DAC Updating (LDAC Held Low)
Command 0101 is reserved for this software LDAC function.
Address bits are ignored. Writing to the DAC, using
Command 0101, loads the 4-bit LDAC register (DB3 to DB0).
The default for each channel is 0; that is, the LDAC pin works
normally. Setting the bits to 1 forces this DAC channel to ignore
transitions on the LDAC pin, regardless of the state of the hardware
LDAC pin. This flexibility is useful in applications where the
user wishes to select which channels respond to the LDAC pin.
LDAC is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
the DAC register are updated on the rising edge of SYNC and
the output begins to change (see Table 15).
AMPLIFIER
VREF
12-/16-BIT
DAC
LDAC
DAC
REGISTER
VOUTX
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 14). Setting the LDAC
bits (DB0 to DB3) to 0 for a DAC channel means that this
channel update is controlled by the hardware LDAC pin.
SCL
12664-072
INPUT
REGISTER
SDA
LDAC MASK REGISTER
INTERFACE
LOGIC
Figure 63. Simplified Diagram of Input Loading Circuitry for a Single DAC
Table 14. LDAC Overwrite Definition
Load LDAC Register
LDAC Bits (DB3 to DB0)
LDAC Pin
LDAC Operation
0000
1111
1 or 0
X1
Determined by the LDAC pin.
DAC channels update and override the LDAC pin. DAC channels see LDAC as 1.
1
X means don’t care.
Table 15. Write Commands and LDAC Pin Truth Table1
Command
0001
Description
Write to Input Register n
(dependent on LDAC)
0010
Update DAC Register n
with contents of Input
Register n
Write to and update DAC
Channel n
0011
Hardware LDAC Pin State
VLOGIC
GND2
VLOGIC
GND
Input Register Contents
Data update
Data update
No change
No change
DAC Register Contents
No change (no update)
Data update
Updated with input register contents
Updated with input register contents
VLOGIC
GND
Data update
Data update
Data update
Data update
A high to low hardware LDAC pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that
are not masked (blocked) by the LDAC mask register.
2
When LDACis permanently tied low, the LDAC mask bits are ignored.
1
Rev. A | Page 28 of 33
Data Sheet
AD5672R/AD5676R
HARDWARE RESET (RESET)
SOLDER HEAT REFLOW
The RESET pin is an active low reset that allows the outputs to
be cleared to either zero scale or midscale. The clear code value
is user selectable via the RESET select pin. It is necessary to
keep the RESET pin low for a minimum time (see Table 5) to
complete the operation. When the RESET signal is returned
high, the output remains at the cleared value until a new value is
programmed. While the RESET pin is low, the outputs cannot
be updated with a new value. A software executable reset function
is also available, which resets the DAC to the power-on reset code.
Command 0110 is designated for this software reset function (see
Table 9). Any events on the LDAC or RESET pins during power-on
reset are ignored.
As with all IC reference voltage circuits, the reference value
experiences a shift induced by the soldering process. Analog
Devices, Inc., performs a reliability test called precondition to
mimic the effect of soldering a device to a board. The output
voltage specification quoted previously includes the effect of
this reliability test.
Figure 64 shows the effect of solder heat reflow (SHR) as
measured through the reliability test (precondition).
35
30
POSTSOLDER
HEAT REFLOW
25
PRESOLDER
HEAT REFLOW
RESET SELECT PIN (RSTSEL)
HITS
The AD5672R/AD5676R contain a power-on reset circuit that
controls the output voltage during power-up. By connecting the
RSTSEL pin low, the output powers up to zero scale. Note that
this is outside the linear region of the DAC; by connecting the
RSTSEL pin high, VOUTx power up to midscale. The output
remains powered up at this level until a valid write sequence is
made to the DAC.
20
15
10
11954-073
5
0
2.497
2.498
2.499
INTERNAL REFERENCE SETUP
2.500
2.501
2.502
VREF (V)
The on-chip reference is on at power-up by default. To reduce
the supply current, turn off this reference by setting the software
programmable bit, DB0, in the control register. Table 16 shows
how the state of the bit corresponds to the mode of operation.
Command 0111 is reserved for setting up the internal reference
(see Table 9). Table 16 shows how the state of the bits in the
input shift register corresponds to the mode of operation of the
device during internal reference setup.
Figure 64. Solder Heat Reflow Reference Voltage Shift
LONG-TERM TEMPERATURE DRIFT
Figure 65 shows the change in VREF value after 1000 hours in the
life test at 150°C.
70
0 HOURS
168 HOURS
500 HOURS
1000 HOURS
60
50
Table 16. Reference Setup Register
Action
Reference on (default)
Reference off
40
HITS
Internal Reference Setup Register (DB0)
0
1
30
20
11954-074
10
0
2.498
2.499
2.500
VREF (V)
2.501
2.502
Figure 65. Reference Drift Through to 1000 Hours
Table 17. 24-Bit Input Shift Register Contents for Internal Reference Setup Command 1
DB23 (MSB)
DB22
DB21
0
1
1
Command bits (C3 to C0)
1
DB20
1
DB19
X
DB18
DB17
DB16
X
X
X
Address bits (A3 to A0)
X means don’t care.
Rev. A | Page 29 of 33
DB15 to DB1
X
Don’t care
DB0 (LSB)
1/0
Reference setup register
AD5672R/AD5676R
Data Sheet
THERMAL HYSTERESIS
3
FIRST TEMPERATURE SWEEP
SUBSEQUENT TEMPERATURE SWEEPS
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient to
cold, to hot, and then back to ambient.
2
HITS
1
0
–130 –110
11954-075
Thermal hysteresis data is shown in Figure 66. It is measured by
sweeping the temperature from ambient to −40°C, then to
+125°C, and returning to ambient. The VREF delta is then
measured between the two ambient measurements and shown
in blue in Figure 66. The same temperature sweep and
measurements were immediately repeated and the results are
shown in red in Figure 66.
–90
–70
–50
–30
–10
10
DISTORTION (ppm)
Figure 66. Thermal Hysteresis
Rev. A | Page 30 of 33
30
50
70
Data Sheet
AD5672R/AD5676R
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS
AD5672R/AD5676R TO SPORT INTERFACE
The AD5672R/AD5676R are typically powered by the following
supplies: VDD = 3.3 V and VLOGIC = 1.8 V.
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 69 shows how a SPORT interface is used to control the
AD5672R/AD5676R.
LDO
ADP160
LDO
ADSP-BF531
3.3V: VDD
SPORT_TFS
SPORT_TSCK
SPORT_DTO
11954-176
ADP7118
5V
INPUT
AD5672R/
AD5676R
1.8V: VLOGIC
GPIO0
GPIO1
Figure 67. Low Noise Power Solution for the AD5672R/AD5676R
MICROPROCESSOR INTERFACING
AD5672R/AD5676R TO ADSP-BF531 INTERFACE
The SPI interface of the AD5672R/AD5676R can easily
connected to industry-standard DSPs and microcontrollers.
Figure 68 shows the AD5672R/AD5676R connected to the
Analog Devices Blackfin® DSP. The Blackfin has an integrated
SPI port that can connect directly to the SPI pins of the
AD5672R/AD5676R.
AD5672R/
AD5676R
SYNC
SCLK
SDI
In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. Design the printed circuit
board (PCB) on which the AD5672R/AD5676R are mounted so
that the devices lie on the analog plane.
The AD5672R/AD5676R must have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply, located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are tantalum bead type. The 0.1 µF capacitors
must have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types,
which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
The GND plane on the device can be increased (as shown in
Figure 70) to provide a natural heat sinking effect.
11954-076
LDAC
RESET
LAYOUT GUIDELINES
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
ADSP-BF531
PF9
PF8
LDAC
RESET
Figure 69. SPORT Interface
Microprocessor interfacing to the AD5672R/AD5676R is
performed via a serial bus that uses a standard protocol
compatible with DSP processors and microcontrollers. The
communications channel requires a 3-wire or 4-wire interface
consisting of a clock signal, a data signal, and a synchronization
signal. The devices require a 24-bit data-word with data valid
on the rising edge of SYNC.
SPISELx
SCK
MOSI
SYNC
SCLK
SDI
11954-077
The ADP7118 can be used to power the VDD pin. The ADP160
can be used to power the VLOGIC pin. This setup is shown in
Figure 67. The ADP7118 can operate from input voltages up to
20 V. The ADP160 can operate from input voltages up to 5.5 V.
AD5672R/
AD5676R
Figure 68. ADSP-BF531 Interface
BOARD
Figure 70. Pad Connection to the Board
Rev. A | Page 31 of 33
11954-078
GND
PLANE
AD5672R/AD5676R
Data Sheet
CONTROLLER
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur.
iCoupler® products from Analog Devices provide voltage
isolation in excess of 2.5 kV. The serial loading structure of the
AD5672R/AD5676R makes the devices ideal for isolated
interfaces because the number of interface lines is kept to a
minimum. Figure 71 shows a 4-channel isolated interface to the
AD5672R/AD5676R using an ADuM1400. For further
information, visit http://www.analog.com/icoupler.
SERIAL
CLOCK IN
SERIAL
DATA OUT
SYNC
LOAD DAC
OUT
1ADDITIONAL
ADuM14001
VIA
VIB
VIC
VID
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
PINS OMITTED FOR CLARITY.
Figure 71. Isolated Interface
Rev. A | Page 32 of 33
VOA
VOB
VOC
VOD
TO
SCLK
TO
SDI
TO
SYNC
TO
LDAC
11954-079
GALVANICALLY ISOLATED INTERFACE
Data Sheet
AD5672R/AD5676R
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
8°
0°
SEATING
PLANE
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 72. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5672RBRUZ
AD5672RBRUZ-REEL7
AD5676RARUZ
AD5676RARUZ-REEL7
AD5676RBRUZ
AD5676RBRUZ-REEL7
EVAL-AD5676RSDZ
1
Resolution
12 Bits
12 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Accuracy
±1 LSB INL
±1 LSB INL
±8 LSB INL
±8 LSB INL
±3 LSB INL
±3 LSB INL
Reference
Temperature
Coefficient (ppm/°C)
2 (typical)
2 (typical)
5 (typical)
5 (typical)
2 (typical)
2 (typical)
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11954-0-2/15(A)
Rev. A | Page 33 of 33
Package Description
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
AD5676R Evaluation Board
Package
Option
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20