INTEGRATED CIRCUITS DATA SHEET TZA3019 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch Preliminary specification File under Integrated Circuits, IC19 2000 Apr 10 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 FEATURES APPLICATIONS • Dual postamplifier • Postamplifier for Synchronous Digital Hierarchy and Synchronous Optical Network (SDH/SONET) transponder • Single 3.3 V power supply • Wideband operation from 50 kHz to 2.5 GHz (typical value) • SDH/SONET wavelength converter • Crosspoint or channel switch • Fully differential • Channels are delay matched • PECL driver • On-chip DC-offset compensations without external capacitor • Fibre channel arbitrated loop • Protection ring • Interfacing with positive or negative supplied logic • Monitoring • Switching possibility between channels • Signal level detectors • Positive Emitter Coupled Logic (PECL) or Current-Mode Logic (CML) compatible data outputs adjustable from 200 to 800 mV (p-p) single-ended • Swing converter CML 200 mV (p-p) to PECL 800 mV (p-p) • Power-down capability for unused outputs and detectors • 2.5 GHz clock amplification. • Port bypass circuit • Rise and fall times 80 ps (typical value) • Possibility to invert the output of each channel separately GENERAL DESCRIPTION The TZA3019 is a low gain postamplifier multiplexer with a dual RSSI and/or LOS detector that is designed for use in critical signal path control applications, such as loop-through, redundant channel switching or Wavelength Division Multiplexing (WDM). The signal path is unregistered, so no clock is required for the data inputs. The signal path is fully differential and delay matched. It is capable of operating from 50 kHz to 2.5 GHz. • Input level-detection circuits for Received Signal Strength Indicator (RSSI) or Loss Of Signal (LOS) detection, programmable from 0.4 to 400 mV (p-p) single-ended, with open-drain comparator output for direct interfacing with positive or negative logic • Reference voltage for output level and LOS adjustment • Automatic strongest input signal switch possibility (TZA3019 version B) The TZA3019 HTQFP32 and HBCC32 packages can be delivered in three versions: • HTQFP32 or HBCC32 plastic package with exposed pad. • TZA3019AHT and TZA3019AV with two RSSI signals • TZA3019BHT and TZA3019BV with one RSSI and one LOS signal • TZA3019CHT and TZA3019CV with two LOS signals. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TZA3019AHT HTQFP32 plastic, heatsink thin quad flat package; 32 leads; body 5 × 5 × 1 mm SOT547-2 TZA3019BHT HTQFP32 plastic, heatsink thin quad flat package; 32 leads; body 5 × 5 × 1 mm SOT547-2 TZA3019CHT HTQFP32 plastic, heatsink thin quad flat package; 32 leads; body 5 × 5 × 1 mm SOT547-2 TZA3019AV HBCC32 plastic, heatsink bottom chip carrier; 32 terminals; body 5 × 5 × 0.65 mm SOT560-1 TZA3019BV HBCC32 plastic, heatsink bottom chip carrier; 32 terminals; body 5 × 5 × 0.65 mm SOT560-1 TZA3019CV HBCC32 plastic, heatsink bottom chip carrier; 32 terminals; body 5 × 5 × 0.65 mm SOT560-1 TZA3019U 2000 Apr 10 − DESCRIPTION bare die; 2.22 × 2.22 × 0.28 mm 2 VERSION − Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 BLOCK DIAGRAM handbook, full pagewidth VEE1A LOSTH1 32 25 VEE1B 10 LOS DETECTOR 27 1× RSSI1 offset LEVEL1 INV1 S1 GND1A IN1 IN1Q GND1A TEST GND2A IN2Q IN2 GND2A S2 INV2 LEVEL2 TZA3019AHT TZA3019AV 12 level 29 31 24 1 SWITCH 2 23 3 22 A1A 4 15 A1B BAND GAP REFERENCE DFT 8 A2B 20 SWITCH 30 GND1B Vref GND2B OUT2Q OUT2 GND2B level 1× 26 RSSI2 11 9 16 MGT028 Fig.1 Block diagram (TZA3019AHT and TZA3019AV). 2000 Apr 10 OUT1 OUT1Q 28 13 LOS DETECTOR VEE2A 18 19 6 offset LOSTH2 14 17 A2A 7 5 21 GND1B 3 VEE2B Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch handbook, full pagewidth VEE1A LOSTH1 TZA3019 32 25 VEE1B 10 LOS DETECTOR 5 kΩ 27 LOS1 offset LEVEL1 INV1 S1 GND1A IN1 IN1Q GND1A TEST GND2A IN2Q IN2 GND2A S2 INV2 LEVEL2 TZA3019BHT TZA3019BV 12 level 29 31 24 1 SWITCH 2 23 3 22 A1A 4 15 A1B BAND GAP REFERENCE DFT 8 A2B 20 SWITCH 30 GND1B Vref GND2B OUT2Q OUT2 GND2B level 1× 26 RSSI2 11 9 16 MGT027 Fig.2 Block diagram (TZA3019BHT and TZA3019AV). 2000 Apr 10 OUT1 OUT1Q 28 13 offset VEE2A 18 19 6 LOS DETECTOR LOSTH2 14 17 A2A 7 5 21 GND1B 4 VEE2B Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch handbook, full pagewidth VEE1A LOSTH1 TZA3019 32 25 VEE1B 10 LOS DETECTOR 5 kΩ 27 LOS1 offset LEVEL1 INV1 S1 GND1A IN1 IN1Q GND1A TEST GND2A IN2Q IN2 GND2A S2 INV2 LEVEL2 TZA3019CHT TZA3019CV 12 level 29 31 24 1 SWITCH 2 23 3 22 A1A 4 15 VEE2A 14 BAND GAP REFERENCE DFT 8 17 A2A 7 A2B 18 19 6 5 20 SWITCH 30 GND1B Vref GND2B OUT2Q OUT2 GND2B level offset 5 kΩ 26 LOS2 11 9 16 MGS553 Fig.3 Block diagram (TZA3019CHT and TZA3019CV). 2000 Apr 10 OUT1 OUT1Q 28 13 LOS DETECTOR LOSTH2 21 A1B GND1B 5 VEE2B Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 PINNING PIN SYMBOL TZA3019xHT/xV(1) A B PAD TYPE(2) DESCRIPTION C GND1A 1 1 1 1 S ground for input 1 and LOS1 circuits IN1 2 2 2 2 I differential circuit 1 input; complimentary to pin IN1Q; DC bias level is set internally at approximately −0.33 V IN1Q 3 3 3 3 I differential circuit 1 input; complimentary to pin IN1; DC bias level is set internally at approximately −0.33 V GND1A 4 4 4 4 S ground for input 1 and LOS1 circuits n.c − − − 5 − not connected n.c − − − 6 − not connected GND2A 5 5 5 7 S ground for input 2 and LOS2 circuits IN2 6 6 6 8 I differential circuit 2 input; complimentary to pin IN2Q; DC bias level is set internally at approximately −0.33 V IN2Q 7 7 7 9 I differential circuit 2 input; complimentary to pin IN2; DC bias level is set internally at approximately −0.33 V GND2A 8 8 8 10 S ground for input 2 and LOS2 circuits VEE2A 9 9 9 11 S negative supply voltage for input 2 and LOS2 circuits LOSTH1 10 10 10 12 I Input for level detector programming of input 1 circuit; threshold level is set by connecting external resistors between pins GND1A and Vref. When forced to VEE2A or not connected, the LOS1 circuit will be switched off. LOSTH2 11 11 11 13 I Input for level detector programming of input 2 circuit; threshold level is set by connecting external resistors between pins GND2A and Vref. When forced to VEE2A or not connected, the LOS2 circuit will be switched off. n.c − − − 14 − not connected LEVEL1 12 12 12 15 I Input for programming output level of output 1 circuit; output level is set by connecting external resistors between pins GND1A and Vref. When forced to GND1A or not connected, pins OUT1 and OUT1Q will be switched off. LEVEL2 13 13 13 16 I Input for programming output level of output 2 circuit; output level is set by connecting external resistors between pins GND2A and Vref. When forced to GND2A or not connected, pins OUT2 and OUT2Q will be switched off. Vref 14 14 14 17 O reference voltage for level circuit and LOS threshold programming; typical value is −1.6 V; no external capacitor allowed n.c − − − 18 − TEST 15 15 15 19 I for test purposes only; to be left open-circuit in the application VEE2B 16 16 16 20 S negative supply voltage for output 2 circuit GND2B 17 17 17 21 S ground for output 2 circuit OUT2Q 18 18 18 22 O PECL or CML compatible differential circuit 2 output; complimentary to pin OUT2 2000 Apr 10 6 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 PIN SYMBOL TZA3019xHT/xV(1) PAD TYPE(2) DESCRIPTION A B C OUT2 19 19 19 23 O GND2B 20 20 20 24 S ground for output 2 circuit n.c − − − 25 − not connected n.c − − − 26 − not connected PECL or CML compatible differential circuit 2 output; complimentary to pin OUT2Q GND1B 21 21 21 27 S ground for output 1 circuit OUT1Q 22 22 22 28 O PECL or CML compatible differential circuit 1 output; complimentary to pin OUT1 OUT1 23 23 23 29 O PECL or CML compatible differential circuit 1 output; complimentary to pin OUT1Q GND1B 24 24 24 30 S ground for output 1 circuit VEE1B 25 25 25 31 S negative supply voltage for output 1 circuit RSSI2 26 26 − 32 O output of received signal strength indicator of detector LOS2 − − 26 33 RSSI1 27 − − 34 LOS1 − 27 27 35 INV2 28 28 28 36 TTL input to invert the signal of pins OUT2 and OUT2Q; directly positive (inverted) or negative supplied logic driven INV1 29 29 29 37 TTL input to invert the signal of pins OUT1 and OUT1Q; directly of positive (inverted) or negative supplied logic driven S2 30 30 30 38 TTL input selector output 2 circuit; directly positive (inverted) or negative supplied logic driven S1 31 31 31 39 TTL input selector output 1 circuit; directly positive (inverted) or negative supplied logic driven VEE1A 32 32 32 40 S negative supply voltage for input 1 and LOS1 circuits VEEP pad pad pad − S negative supply voltage pad (exposed die pad) O-DRN output loss of signal detector 2; detection of input 2 signal; direct drive of positive or negative supplied logic via internal 5 kΩ resistor O output of received signal strength indicator of detector O-DRN output loss of signal detector 2; detection of input 2 signal; direct drive of positive or negative supplied logic via internal 5 kΩ resistor Notes 1. The ‘x’ in TZA3019xHT/xV represents versions A, B and C. 2. Pin type abbreviations: O = output, I = input, S = power supply, TTL = logic input and O-DRN = open-drain output. 2000 Apr 10 7 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch 1 IN1 2 IN1Q 3 GND1A 4 25 VEE1B 27 RSSI1/LOS1 28 INV2 29 INV1 30 S2 31 S1 32 VEE1A handbook, full pagewidth GND1A 26 RSSI2/LOS2 TZA3019 24 GND1B 23 OUT1 exposed pad 22 OUT1Q 21 GND1B TZA3019xHT GND2A 5 20 GND2B IN2 6 19 OUT2 IN2Q 7 GND2A 8 VEEP 18 OUT2Q VEE2B 16 TEST 15 Vref 14 LEVEL2 13 LEVEL1 12 LOSTH2 11 LOSTH1 10 VEE2A 9 17 GND2B MGS554 VEE1A S1 S2 INV1 INV2 RSSI1/LOS1 RSSI2/LOS2 VEE1B Fig.4 Pin configuration HTQFP32. 32 31 30 29 28 27 26 25 handbook, full pagewidth GND1A 1 IN1 2 IN1Q 24 GND1B 3 23 OUT1 GND1A 4 22 OUT1Q GND2A 5 21 GND1B IN2 6 20 GND2B IN2Q 7 19 OUT2 18 OUT2Q 17 GND2B TZA3019xV VEEP 9 10 11 12 13 14 15 16 LOSTH1 LOSTH2 LEVEL1 LEVEL2 Vref TEST VEE2B 8 VEE2A GND2A exposed pad Fig.5 Pin configuration HBCC32. 2000 Apr 10 8 MGT029 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 In such cases, pull-up resistors of 100 Ω should be connected as close as possible to the IC from pins OUT1 and OUT1Q, and pins OUT2 and OUT2Q to VEE1B and VEE2B respectively. These matching resistors are not needed in most applications. FUNCTIONAL DESCRIPTION The TZA3019 is a dual postamplifier with multiplexer and loss of signal detection see Figs 1, 2 and 3. The RF path starts with the multiplexer, which connects an amplifier to one of the two inputs. It is possible to invert the output for easy layout of the Printed-Circuit Board (PCB). The signal is amplified to a certain level. To guarantee this level with minimum distortion over the temperature range and level range, an active control part is added. The offset compensation circuit following the inverter minimizes the offset. GND1A, GND2A handbook, halfpage 12 pF The Received Signal Strength Indicator (RSSI) or the Loss Of Signal (LOS) detection uses a 7-stage ‘successive detection’ circuit. It provides a logarithmic output. The LOS is followed by a comparator with a programmable threshold. The input signal level-detection is implemented to check if the input signal voltage is above the user programmed level. This can insure that data will only be transmitted when the input signal-to-noise ratio is sufficient for low bit error rate system operation. A second offset compensation circuit minimizes the offset of the logarithmic amplifier. 50 Ω 420 Ω 50 Ω IN1, IN2 IN1Q, IN2Q MGS555 VEE1A, VEE2A Fig.6 RF input circuit. RF input circuit The input circuit contains internal 50 Ω resistors decoupled to ground via an internal common mode 12 pF capacitor (see Fig.6). Postamplifier level adjustment The postamplifier boosts the signal up to PECL levels. The output can be either CML- or PECL-level compatible, adjusted by means of the voltage on pins LEVEL1 and LEVEL2. The DC voltages of pins OUT1 and OUT1Q, and pins OUT2 and OUT2Q match with the DC-levels on pins LEVEL1 and LEVEL2, respectively. Due to the receiving end 50 Ω load resistance, it means that at the same level of Vo(p-p), VLEVEL1 and VLEVEL2 with AC-coupling are not equal to VLEVEL1 and VLEVEL2 with DC-coupling (see Figs 7 and 8). The input pins are DC-biased at approximately −0.33 V by an internal reference generator. The TZA3019 can be DC-coupled, but AC-coupling is preferred. In case of DC-coupling, the driving source must operate within the allowable input range (−1.0 to +0.3 V). A DC-offset voltage of more than a few millivolts should be avoided, since the internal DC-offset compensation circuit has a limited correction range. When AC-coupling is used, if no DC-compatibility is required, the values of the coupling capacitors must be large enough to pass the lowest input frequency of interest. Capacitor tolerance and resistor variation must be included for an accurate calculation. Do not use signal frequencies around the low cut-off circuit frequencies (f−3dB(l) = 50 kHz for the postamplifiers and f−3dB(l) = 1 MHz for the LOS circuits). The postamplifier is in power-down state when pin LEVEL1 or LEVEL2 is connected to ground or not connected (see Fig.8). Postamplifier DC offset cancellation loop Offset control loops connected between the inputs of the buffers A1A and A2A and the outputs of the amplifiers A1B and A2B (see Figs 1, 2 and 3) will keep the input of both buffers at their toggle point during the absence of an input signal. The active offset compensation circuit is integrated, so no external capacitor is required. The loop time constant determines the lower cut-off frequency of the amplifier chain. The cut-off frequency of the offset compensations is fixed internally at approximately 5 kHz. RF output circuit Matching the main amplifier outputs (see Fig.7) is not mandatory. In most applications, the transmission line receiving end will be properly matched, while very little reflections occur. Matching the transmitting end to absorb reflections is only recommended for very sensitive applications. 2000 Apr 10 9 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch handbook, full pagewidth GND1A, GND2A TZA3019 GND1B, GND2B 100 Ω R1 100 Ω OUT1, OUT2 Vo 50 Ω 50 Ω OUT1Q, OUT2Q LEVEL1, LEVEL2 Vlevel REG R2 0 Vref Vlevel Vo(se)(p-p) Vo (V) MGS556 Vlevel = 0.5 × Vo(se)(p-p). R1 V level = V ref × ---------------------- . R1 + R2 Level detector in power-down mode: VLEVEL1 or VLEVEL2 = VGND. a. DC-coupling. handbook, full pagewidth GND1A, GND2A GND1B, GND2B 100 Ω 100 Ω OUT1, OUT2 Vo R1 50 Ω 50 Ω OUT1Q, OUT2Q LEVEL1, LEVEL2 Vlevel 0 R2 REG Vref Vlevel Vo (V) Vlevel = 1.5 × Vo(se)(p-p). R1 V level = V ref × ---------------------- . R1 + R2 Level detector in power-down mode: VLEVEL1 or VLEVEL2 = VGND. b. AC-coupling. Fig.7 RF output configurations. 2000 Apr 10 10 Vo(se)(p-p) MGL811 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 MGS557 handbook, full pagewidth 1000 Vo(se)(p-p) (mV) 800 DC-coupled AC-coupled 600 400 200 0 0 20 40 100 80 Vlevel (% of Vref) 60 Fig.8 Output signal as a function of Vlevel. TTL logic input of selector and inverter Table 2 The logic levels are differently defined for positive or negative logic (see Fig.9). It should be noted that positive logic levels are inverted if a negative supply voltage is used. S2 OUT2 OUT2Q 0 IN2 IN2Q 1 IN1 IN1Q Table 3 Outputs as a function of switch input pins S1, S2, INV1 and INV2 OUT2 and OUT2Q as function of input S2 OUT1 and OUT1Q as function of INV1 INV1 OUT1 OUT1Q See Tables 1, 2, 3 and 4. 0 IN1 or IN2 IN1Q or IN2Q The default values for the switch input pins S1, S2, INV1 and INV2 if not connected, is zero. 1 IN1Q or IN2Q IN1 or IN2 Table 4 Table 1 OUT1 and OUT1Q as function of input S1 S1 OUT1 OUT1Q 0 IN1 IN1Q 1 IN2 IN2Q 2000 Apr 10 INV2 11 OUT2 and OUT2Q as function of INV2 OUT2 OUT2Q 0 IN1 or IN2 IN1Q or IN2Q 1 IN1Q or IN2Q IN1 or IN2 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch handbook, full pagewidth logic level TZA3019 MGS558 2.0 V 2.0 V 1 (1) T TL 0.8 V 0.8 V 0 1.4 V 1.4 V VEE −4 GND −3 −2 −1 +1 0 +2 +3 VI (V) a. Negative circuit supply voltage VEE and negative logic supply voltage VEE. handbook, full pagewidth logic level MGS559 2.0 V 2.0 V 1 (1) T TL 0.8 V 0.8 V 0 1.4 V 1.4 V VEE −4 VCC GND −3 −2 −1 0 +1 +2 +3 VI (V) b. Negative circuit supply voltage VEE and positive logic supply voltage VCC. logic level handbook, full pagewidth MGS560 2.0 V 2.0 V 1 (1) T TL 0.8 V 0.8 V 0 1.4 V 1.4 V VCC GND −1 0 +1 +2 +3 +4 +5 +6 VI (V) c. Positive circuit supply voltage VCC and positive logic supply voltage VCC. (1) Level not defined. Fig.9 Logic levels on pins S1, S2, INV1 and INV2 as a function of the input voltages. 2000 Apr 10 12 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 RSSI and LOS detection The TZA3019 allows AC-signal level detection. This can prevent the outputs from reacting to noise during the absence of a valid input signal, and can insure that data only will be transmitted when the signal-to-noise ratio of the input signal is sufficient to insure low bit error rate system operation. handbook, halfpage 103 Vi(se)(p-p) (mV) 102 The RSSI detection circuit uses seven limiting amplifiers in a ‘successive detection’ topology to closely approximate logarithmic response over a total range of 70 dB. The detectors provide full-wave rectification of the AC signals presented at each previous amplifier stage. Their outputs are current drivers. Each cell incorporates a low-pass filter, being the first step in recovering the average value of the demodulated signal of the input frequency. The summed detector output currents are converted to a voltage by an internal load resistor. This voltage is buffered and available in the A and B versions of the TZA3019. When VRSSI is used VLOSTH must be connected to GND to prevent the LOS comparator from switching to the standby mode. The LOS comparator detects an input signal above a fixed threshold, resulting in a LOW-level at the LOS circuit output.The threshold level is determined by the voltage on pins LOSTH1 or LOSTH2 (see Fig.10). A filter with a time constant of 1 µs nominal is included to prevent noise spikes from triggering the level detector. LOS1, LOS2 HIGH-level 1 10−1 10 −0.16 (3) 20 −0.32 40 50 60 30 70 VLOSTH1, VLOSTH2 (% of Vref) −0.48 −0.64 −0.8 −0.96 −1.12 VRSSI1, VRSSI2 (V) (1) PRBS pattern input signal with a frequency <1 GHz. (2) Linearity error typically 0.5 dB. (3) ϕ = 1/12.5 dB/mV. Fig.10 Loss of signal assert level. A full understanding of the offset control loop is useful. The primary purpose of the loop is to extend the lower end of the dynamic range in any case where the offset voltage of the first stage might be high enough to cause later stages to prematurely enter limiting, caused by the high DC-gain of the amplifier system. The offset is automatically and continuously compensated via a feedback path from the last stage. An offset at the output of the logarithmic converter is equivalent to a change of amplitude at the input. Consequently, with DC-coupling, signal absence, either LOW-level or HIGH-level is detected as a full signal, only signals with an average value equal to zero give zero output. Version B can be used for an auto function, which switches the strongest input signal to output 1 and the weakest to output 2. To achieve this output VRSSI2 must be used as the reference voltage for input VLOSTH. Then the output LOS1 can switch S1 and S2. (1) where S = sensitivity. Example: a 200 mV (p-p) single-ended 1.2 GB/s PRBS signal has an RSSI from 1003 mV. 2000 Apr 10 (1) (2) The response is independent of the sign of the input signal because of the particular way the circuit has been built. This is part of the demodulating nature of the detector, which results in an alternating input voltage being transformed to a rectified and filtered quasi DC-output signal. For the TZA3019 the logarithmic voltage slope is ϕ = 1/13 dB/mV and is essentially temperature and supply independent through four feedback loops in the reference circuit. The internal LOS detector output voltage is based on Vref. The demodulator characteristic depends on the waveform and the response depends roughly on the input signal RMS value. This influences high frequencies, a square wave input of 2.4 GHz (LOS circuit bandwidth of 2.4 GHz) offsets the intercept voltage by 20%. VLOSTH can be calculated using the following formulae: ( Vi ⁄ 18µV ) LOS1, LOS2 LOW-level 10 The comparator (with internal 3 dB hysteresis) drives an open-drain circuit with an internal resistor (5 kΩ) for direct interfacing to positive or negative logic (see Fig.11). Only available in the B and C versions of the TZA3019. V LOSTH = V RSSI = S × 20log MGS564 13 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch GND handbook, halfpage TZA3019 VCC handbook, halfpage GND 56 kΩ 5 kΩ LOS1, LOS2 TZA3019 LOS1, LOS2 TZA3019 5 kΩ GND1A, GND2A GND1A, GND2A ILOS ILOS MGS561 5.6 kΩ VEE MGS562 a. Negative supply and negative logic. VEE b. Negative supply and positive logic. VCC handbook, halfpage 56 kΩ LOS1, LOS2 TZA3019 5 kΩ GND1A, GND2A ILOS GND MGS563 VCC − VEE < 7 V. c. Positive supply and positive logic. Fig.11 Loss of signal outputs, pins LOS1 and LOS2. Supply current 58 Using a positive supply voltage I EE1B, 50 I EE2B Although the TZA3019 has been designed to use a single −3.3 V supply voltage (see Fig.13), a +3.3 V supply (see Fig.14) can also be used. However, care should be taken with respect to RF transmission lines. The on-chip signals refer to the various ground pins as being positive supply pins in a +3.3 V application. The external transmission lines will most likely be referred to the pins VEE1A, VEE2A, VEE1B and VEE2B, being the system ground. The RF signals will change from one reference plane to another when interfacing the RF inputs and outputs. A positive supply application is very vulnerable to interference with respect to this point. For a successful +3.3 V application, special care should be taken when designing the PCB layout in order to reduce the influence of interference and to keep the positive supply voltage as clean as possible. 2000 Apr 10 (1) 60 For the supply currents IEE1B and IEE2B, see Fig.12. (mA) 40 30 20 17 10 5 0 0 0.2 0.8 0.5 Vo(se)(p-p) (V) (1) IEE1B and IEE2B at 25 °C. Fig.12 Supply current as a function of output voltage 14 1 MGS566 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER VEE negative supply voltage Vn DC voltage MIN. −5.5 UNIT +0.5 V 0.5 V VEE − 0.5 VEE + 7 V pins IN1, IN1Q, IN2 and IN2Q −20 +20 mA pins LOSTH1, LOSTH2, LEVEL1 and LEVEL2 0 14 µA pins Vref, TEST, LOS1 and LOS2 −1 +1 mA pins OUT1, OUT1Q, OUT2 and OUT2Q −30 +30 mA pins INV1, INV2, S1 and S2 0 20 µA pins IN1, IN1Q, IN2, IN2Q, LOSTH1, LOSTH2, LEVEL1, LEVEL2, VEE − 0.5 Vref, TEST, OUT2Q, OUT2, OUT1Q, OUT1, VEEP, GND1A, GND2A, GND1B and GND2B pins LOS1, LOS2, INV1, INV2, S1 and S2 In MAX. DC current Ptot total power dissipation − 1.2 W Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Tamb ambient temperature −40 +85 °C THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT 15 K/W Rth(j-s) thermal resistance from junction to solder point (exposed die pad); note 1 Rth(j-a) thermal resistance from junction to ambient; note 1 1s2p multi-layer test board 33 K/W Rth(s-a) thermal resistance from solder point to ambient (exposed die pad); note 1 1s2p multi-layer test board 18 K/W Rth(s-a)(req) required thermal resistance from solder point to ambient LOS circuits switched on Vo = 200 mV (p-p) single-ended; both output circuits 60 K/W Vo = 800 mV (p-p) single-ended; both output circuits 30 K/W Note 1. JEDEC standard. 2000 Apr 10 15 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 CHARACTERISTICS Typical values at Tamb = 25 °C and VEE = −3.3 V; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range; all voltages referenced to ground; unless otherwise specified; note 1. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply SUPPLY PINS VEE1A, VEE1B, VEE2A AND VEE2B VEE negative supply voltage IEE1A, IEE2A negative supply current IEE1B, IEE2B negative supply current Ptot total power dissipation −3.13 −3.3 −3.47 V LOS circuit power-down 14 24 34 mA LOS circuit switched on 24 40 56 mA amplifier power-down 2 6 10 mA Vo = 200 mV (p-p) single-ended; one output circuit 11 17 24 mA Vo = 800 mV (p-p) single-ended; one output circuit 47 60 77 mA power-down 100 200 300 mW Vo = 200 mV (p-p) single-ended; both output circuits 220 380 555 mW Vo = 800 mV (p-p) single-ended; both output circuits 450 660 925 mW LOS circuit switched on; IEE1A; 30 IEE2A 50 80 µA/°C Vo = 800 mV (p-p) single-ended; IEE1A; IEE2A 15 30 50 µA/°C both LOS circuits switched on TC temperature coefficient Tj junction temperature −40 − +125 °C Tamb ambient temperature −40 +25 +85 °C 50 − 500 mV −0.28 −0.33 −0.4 V Inputs multiplexer and loss of signal detector PECL OR CML INPUT PINS IN1, IN1Q, IN2 AND IN2Q Vi(p-p) input voltage swing (peak-to-peak value) Vi(bias) DC input bias voltage VI DC and AC input window voltage note 3 −1.0 − +0.3 V Ri input resistance single-ended 35 50 70 Ω Ci input capacitance single-ended; note 3 0.6 0.8 1.2 pF 2000 Apr 10 single-ended; note 2 16 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch SYMBOL PARAMETER TZA3019 CONDITIONS MIN. TYP. MAX. UNIT Postamplifier AMPLIFIERS A1A, A1B, A2A AND A2B Gv small signal voltage gain Vo = 200 mV (p-p) single-ended; note 4 10 15 19 dB Vo = 800 mV (p-p) single-ended; note 4 22 29 34 dB fD signal path data rate notes 5 and 9 − 2500 − Mbits/s f−3dB(l) low −3 dB cut-off frequency DC compensation note 3 2 5 10 kHz f−3dB(h) high −3 dB cut-off frequency − 2.0 − GHz tPD propagation delay note 3 150 200 250 ps ∆tPD propagation delay difference at the same signal levels; note 3 − 0 5 ps J total jitter 20 bits of the 28.5kbits pattern; notes 3 and 6 − 8 − ps αct crosstalk crosstalk of IC only 90 110 − dB 200 − 800 mV −1 0 −1 mV/K PECL OR CML OUTPUT PINS OUT1, OUT1Q, OUT2 AND OUT2Q 50 Ω load Vo(se)(p-p) single-ended output voltage (peak-to-peak value) TC temperature coefficient output level tr rise time 20% to 80%; note 5 − 80 − ps tf fall time 80% to 20%; note 5 − 80 − ps Ro output resistance single-ended 70 100 130 Ω Co output capacitance single-ended; note 3 0.6 0.8 1.2 pF Vref − 0 V 150 350 600 kΩ Vo = 200 mV (p-p) single-ended; note 7 4 9 13 dB Vo = 800 mV (p-p) single-ended; note 7 10 14 20 dB peak-to-peak value single-ended −10 − +10 mV Vn(i)(eq)(rms) equivalent input noise voltage (RMS value) Vo = 800 mV (p-p) single-ended; note 3 − 75 170 µV Fn note 3 − 5 12 dB LEVEL CONTROL INPUT PINS LEVEL1 AND LEVEL2 Vi input voltage Ri input resistance measured to GND1A or GND2A Multiplexer and inverter switch PECL OR CML INPUT PINS IN1, IN1Q, IN2 AND IN2Q αOS(red) Vio(cor) 2000 Apr 10 input offset reduction input offset voltage correction range noise factor 17 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch SYMBOL PARAMETER TZA3019 CONDITIONS MIN. TYP. MAX. UNIT SWITCH CIRCUIT ta assert time multiplexer and inverter 70 100 200 ns td de-assert time multiplexer and inverter 55 80 160 ns positive logic 2.0 − VEE + 7.3 V negative logic VEE − 0.3 − −2.5 V TTL INPUT PINS S1, S2, INV1 AND INV2 VIL VIH LOW-level input voltage HIGH-level input voltage Ri input resistance Ii input current negative logic −1.3 − +0.3 V positive logic −0.3 − +0.8 V measured to VEE1A or VEE2A 100 180 400 kΩ −10 − +10 µA Received Signal Strength Indicator and Loss Of Signal detector RSSI AND LOS CIRCUIT Vi(se)(p-p) single-ended input voltage swing (peak-to-peak value) 0.4 − 400 mV DR dynamic range 57 60 63 dB SLOS LOS sensitivity 50 MHz, square; note 8 11 12.5 14 mV/dB 620 MHz, square; note 8 10.7 11.9 13 mV/dB 1.2 GHz, square; note 8 10 11.1 12.2 mV/dB 11.2 12.7 14.2 mV/dB 1.2 GB/s PRBS (231 − 1); note 8 10.9 12.4 13.9 mV/dB 100 GB/s PRBS (231 − 1); note 8 10.7 11.9 13 mV/dB −2 0 −2 µV/dbK 100 MB/s PRBS note 8 (231 − 1); TCsens temperature coefficient sensitivity LE linearity error see Fig.10 − 0.5 1 dB αOS(red) input offset reduction notes 3 and 7 25 35 45 dB Vio(cor) input offset voltage correction range peak-to-peak value single-ended −5 − +5 mV f−3dB(l) low −3 dB cut-off frequency 0.5 1 2 MHz f−3dB(h) high −3 dB cut-off frequency note 8 1.5 2 2.5 GHz hysLOS LOS hysteresis input signal waveform dependency 2.0 3.0 4.0 dB ta assert time note 3 − − 5 µS td de-assert time note 3 − − 5 µS VEE − 0 V measured to VEE1A or VEE2A 150 350 600 kΩ LOS CIRCUIT INPUT PINS LOSTH1 AND LOSTH2 Vi input voltage Ri input resistance 2000 Apr 10 18 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch SYMBOL PARAMETER TZA3019 CONDITIONS MIN. TYP. MAX. UNIT OUTPUT PINS LOS1 AND LOS2 Vo output voltage VEE − 3.5 V Io(sink) output sink current − − 1 mA Ro output resistance 3.5 5 6.5 kΩ internal output series resistance OUTPUT PINS RSSI1 AND RSSI2 Vo output voltage −1 − 0 V Io output current −1 − +1 mA Band gap reference circuit OUTPUT PIN VREF Vref reference voltage −1.45 −1.6 −1.8 V Cext allowed external capacitance − − 10 pF Io(sink) output sink current − − 500 µA Notes 1. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true differential excitation). 2. Minimum signal with limiting output. 3. Guaranteed by design. Vo 4. GV = -----Vi 5. Based on −3dB cut-off frequency. 6. Vi = 100 mV (p-p) single-ended and Vo = 200 mV (p-p) single-ended. 7. Input offset reduction = G AC ----------G DC 8. Sensitivity depends on the waveform and is therefore a function of −3 dB cut-off frequency see equation (1). 9. Low limit can go as low as DC if input signal overrides input offset voltage correction range. APPLICATION INFORMATION All VEE pins (one at each corner and the exposed die pad) need to be connected to a common supply plane with an inductance as low as possible. This plane should be decoupled to ground. To avoid high frequency resonance, multiple bypass capacitors should not be mounted at the same location. To minimize low frequency switching noise in the vicinity of the TZA3019, the power supply line should be filtered once using a beaded capacitor circuit with a low cut-off frequency (see Figs 13 and 14). RF input and output connections Striplines, or microstrips, with an odd mode characteristic impedance of Zo = 50 Ω must be used for the differential RF connections on the PCB. This applies to both the signal inputs and the signal outputs. The two lines in each pair should have the same length. Grounding and power supply decoupling The VEE connection on the PCB also needs to be a large copper area to improve heat transfer to the PCB and thus support IC cooling. The ground connection on the PCB needs to be a large copper filled area connected to a common ground plane with an inductance as low as possible. 2000 Apr 10 19 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch handbook, full pagewidth TZA3019 0 1 2 3 4 To central VEE decoupling GND1B 23 OUT1 22 OUT1Q 21 GND1B 20 GND2B 19 OUT2 18 OUT2Q 17 0603 8 GND2B 0603 0603 0603 16 VEE2B 15 TEST 14 Vref 13 LEVEL2 12 LEVEL1 11 LOSTH2 VEE2A 10 LOSTH1 9 0603 0603 24 7 0603 VEE1B 25 28 6 To central VEE decoupling 26 29 5 0603 LOS2 INV2 4 IN2Q 27 INV1 30 3 IN2 GND2A S2 2 IN1Q GND2A 31 IN1 GND1A S1 1 GND1A VEE1A 32 0603 ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, LOS1 ,, ,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,, ,,, ,, ,,, ,, ,,, ,,, ,,, 5 mm 0603 To central VEE decoupling GND GND VEE signal/VEEP Boundary of 200 mm2 area 0603 0603 0603 To central VEE decoupling 0603 0603 0603 0603 0603 HTQFP 0603 MGS567 In order to enable heat flow out of the package, the following measures have to be taken: (1) Solder the 3 × 3 mm2 die pad to a plane with maximum size. (2) Add a plane with minimum 200 mm2 in an inner layer, surrounded by ground layers. (3) Use maximum amount of vias to connect two planes. (4) Use minimum of openings in heat transport area between hot plane and ground planes. Fig.13 PCB layout for negative supply voltage. 2000 Apr 10 20 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch handbook, full pagewidth TZA3019 0 1 2 3 4 5 mm To central VEE decoupling 0603 0603 To central VEE decoupling INV2 LOS1 LOS2 29 28 27 26 GND1B OUT1 OUT1Q 21 GND1B 20 GND2B 19 OUT2 OUT2Q 17 8 18 7 22 6 GND2B 0603 0603 0603 16 VEE2B 15 TEST 14 Vref 13 LEVEL2 12 LEVEL1 11 LOSTH2 VEE2A 10 LOSTH1 9 0603 0603 23 5 To central VEE decoupling ,, ,, ,, ,, ,, ,, ,, ,, ,, 24 4 0603 0603 VEE1B 25 INV1 30 3 IN2 IN2Q GND2A S2 2 IN1Q GND2A 31 IN1 GND1A S1 1 GND1A VEE1A 32 ,, ,, ,, ,, ,, ,, ,, ,, ,, ,,,,, , , , 0603 GND GND VEE signal/VEEP Boundary of 200 mm2 area 0603 0603 0603 0603 0603 0603 0603 0603 To central VEE decoupling HTQFP 0603 MGS568 In order to enable heat flow out of the package, the following measures have to be taken: (1) Solder the 3 × 3 mm2 die pad to a plane with maximum size. (2) Add a plane with minimum 200 mm2 in an inner layer, surrounded by ground layers. (3) Use maximum amount of vias to connect two planes. (4) Use minimum of openings in heat transport area between hot plane and ground planes. Fig.14 PCB layout for positive supply voltage. 2000 Apr 10 21 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 BONDING PAD LOCATIONS COORDINATES(1) SYMBOL COORDINATES(1) SYMBOL PAD x PAD y OUT2 23 +928 −396 GND1A 1 −928 +710 GND2B 24 +928 −239 IN1 2 −928 +553 n.c. 25 +928 −81 IN1Q 3 −928 +396 n.c. 26 +928 +81 GND1A 4 −928 +239 GND1B 27 +928 +239 n.c. 5 −928 +81 OUT1Q 28 +928 +396 x y n.c. 6 −928 −81 OUT1 29 +928 +553 GND2A 7 −928 −239 GND1B 30 +928 +710 IN2 8 −928 −396 VEE1B 31 +707 +928 IN2Q 9 −928 −553 RSSI2 32 +550 +928 GND2A 10 −928 −710 LOS2 33 +393 +928 VEE2A 11 −707 −928 RSSI1 34 +236 +928 LOSTH1 12 −550 −928 LOS1 35 +79 +928 LOSTH2 13 −393 −928 INV2 36 −79 +928 n.c. 14 −236 −928 INV1 37 −236 +928 38 −393 +928 LEVEL1 15 −79 −928 S2 LEVEL2 16 +79 −928 S1 39 −550 +928 VREF 17 +236 −928 VEE1A 40 −707 +928 n.c. 18 +393 −928 TEST 19 +550 −928 VEE2B 20 +707 −928 GND2B 21 +928 −710 OUT2Q 22 +928 −553 2000 Apr 10 Note 1. All x and y coordinates represent the position of the centre of the pad in µm with respect to the centre of the die (see Fig.15) 22 Philips Semiconductors Preliminary specification VEE1B RSSI2 LOS2 TZA3019 RSSI1 LOS1 INV2 INV1 S2 handbook, full pagewidth S1 VEE1A 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch 40 39 38 37 36 35 34 33 32 31 GND1A 1 30 GND1B IN1 2 29 OUT1 IN1Q 3 28 OUT1Q GND1A 4 27 GND1B n.c. 5 26 n.c. n.c. 6 25 n.c. GND2A 7 24 GND2B IN2 8 23 OUT2 IN2Q 9 22 OUT2Q 21 GND2B GND2A x 0 0 y TZA3019U 10 VEE2B TEST n.c. Vref LEVEL2 LEVEL1 n.c. LOSTH2 LOSTH1 VEE2A 11 12 13 14 15 16 17 18 19 20 MGT030 Fig.15 Bonding pad locations TZA3019U. 2000 Apr 10 23 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 PACKAGE OUTLINE HTQFP32: plastic, heatsink thin quad flat package; 32 leads; body 5 x 5 x 1.0 mm SOT547-2 c y heathsink side X Dh 24 17 25 A 16 ZE e E HE Eh (A 3) A A2 A1 w M θ bp Lp pin 1 index 32 L 9 detail X 1 8 ZD w M bp v M A e D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 A2 A3 bp c D(1) Dh E(1) Eh e HD HE L Lp v w y 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 5.1 4.9 3.1 2.7 5.1 4.9 3.1 2.7 0.5 7.1 6.9 7.1 6.9 1.0 0.75 0.45 0.2 0.08 0.08 ZD(1) ZE(1) θ 0.89 0.61 7° 0° 0.89 0.61 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ SOT547-2 2000 Apr 10 EUROPEAN PROJECTION ISSUE DATE 99-06-15 24 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 HBCC32: plastic, heatsink bottom chip carrier; 32 terminals; body 5 x 5 x 0.65 mm SOT560-1 x B D b1 w M w M ball A1 index area b b3 E w M b2 w M detail X x C A e1 B e y v A C E1 e4 e2 1 32 A1 X D1 A2 e3 A 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b b1 b2 b3 D D1 E E1 e e1 e2 e3 e4 v w x y mm 0.80 0.10 0.05 0.70 0.60 0.35 0.20 0.50 0.30 0.50 0.35 0.50 0.35 5.1 4.9 3.2 3.0 5.1 4.9 3.2 3.0 0.5 4.2 4.2 4.15 4.15 0.2 0.15 0.15 0.05 OUTLINE VERSION SOT560-1 2000 Apr 10 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 99-09-10 00-02-01 MO-217 25 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 2000 Apr 10 TZA3019 26 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Apr 10 27 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch TZA3019 DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2000 Apr 10 28 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch NOTES 2000 Apr 10 29 TZA3019 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch NOTES 2000 Apr 10 30 TZA3019 Philips Semiconductors Preliminary specification 2.5 Gbits/s dual postamplifier with level detectors and 2 × 2 switch NOTES 2000 Apr 10 31 TZA3019 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com SCA 69 © Philips Electronics N.V. 2000 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403510/50/01/pp32 Date of release: 2000 Apr 10 Document order number: 9397 750 06019