Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD DESCRIPTION ABT22V10-7 PIN CONFIGURATIONS The ABT22V10 is a versatile PAL device fabricated with the Philips BiCMOS process known as QUBiC. The QUBiC process produces a very high speed device (7.5ns worst case) which has excellent noise characteristics. The ground bounce, with 9 outputs switching and the 10th held low is less than 0.8V (see page 12). N Package I0/CLK 1 24 VCC I1 2 23 F9 The ABT22V10 is designed so the outputs can never display a metastable state due to set up and hold time violations. If set up and hold times are violated, the outputs will not glitch or display a metastable state (the propagation delays may, however, be extended). I2 3 22 F8 I3 4 21 F7 I4 5 20 F6 I5 6 19 F5 The ABT22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-product equations. This device has a programmable AND array which drives a fixed OR array. The AND array is programmed to create custom product terms while the fixed OR array sums selected terms at the output. I6 7 18 F4 I7 8 17 F3 I8 9 16 F2 The OR sum of the products feeds the “Output Macro Cell” (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. In other words, the architecture provides maximum design flexibility by allowing the Output Macro Cell to be configured by the user. I9 10 15 F1 I10 11 14 F0 GND 12 13 I11 N = Plastic Dual In-Line Package (300mil-wide) A Package This device is pin and JEDEC file compatible with industry standard 22V10 and can be used in all standard applications where speed is to be maximized. I3 FEATURES • Ultra fast 7.5ns tPD and 6ns tCO • High output drive; 48mA = IOL (complete specification, page 3) • Metastable immune flip-flops, τ = 83pS (complete specification, page 9) • Low ground bounce (<0.8V) • Varied product term distribution with up to 16 product terms per I2 I1 4 3 CLK/ I0 NC VCC F9 F8 2 1 28 27 26 5 25 F7 I4 6 24 F6 I5 7 23 F5 NC 8 22 NC I6 9 21 F4 I7 10 20 F3 I8 11 output for complex functions Programmable output polarity • • Power-up reset on all registers • Synchronous Preset/Asynchronous Reset • Programmable on standard PAL-type device programmers • Design support provided using SNAP software development 19 F2 14 15 16 17 18 12 13 I9 I10 GND NC I11 F0 F1 A = Plastic Leaded Chip Carrier SP00406 PIN LABEL DESCRIPTIONS package and other CAD tools for PLDs APPLICATIONS • DMA control • State machine implementation • High speed graphics processing • Counters/shift registers • SSI/MSI random logic replacement • High speed memory decoder I1 – I11 Dedicated Input NC Not Connected F0 – F9 Macro Cell Input/Output CLK/I0 Clock Input/Dedicated Input VCC Supply Voltage GND Ground ORDERING INFORMATION DESCRIPTION ORDER CODE DRAWING NUMBER 24-Pin Plastic Dual-In-Line Package 300mil-wide ABT22V10–7N SOT222-1 28-Pin Plastic Leaded Chip Carrier ABT22V10–7A SOT261-3 PAL is a registered trademark of Advanced Micro Devices, Inc. 1995 Sep 26 2 853-1735 15806 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 ABSOLUTE MAXIMUM RATINGS1 RATINGS SYMBOL PARAMETER MIN UNIT MAX VCC Supply voltage –0.5 +7.0 VDC VIN Input voltage –1.2 VCC + 0.5 VDC VOUT Output voltage –0.5 VCC + 0.5 VDC IIN Input currents –30 +30 mA IOUT Output currents +100 mA Tstg Storage temperature range +150 °C –65 NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. THERMAL RATINGS OPERATING RANGES RATINGS TEMPERATURE SYMBOL PARAMETER Maximum junction 150°C Maximum ambient 75°C VCC Supply voltage Allowable thermal rise ambient to junction 75°C Tamb Operating free-air temperature UNIT MIN MAX +4.75 +5.25 VDC 0 +75 °C DC ELECTRICAL CHARACTERISTICS (OVER OPERATING RANGES) SYMBOL PARAMETER TEST CONDITIONS1 LIMITS MIN MAX UNIT Input voltage VIL Low VCC = MIN VIH High VI Clamp VCC = MAX 0.8 2.0 VCC = MIN, IIN = –18mA V V –1.2 V 0.5 V Output voltage VCC = MIN, VIN = VIH or VIL VOL Low IOL = 48mA VOH High IOH = –16 mA IIL Low VCC = MAX, VIN = 0.40V –10 µA IIH High VCC = MAX, VIN = 2.7V 10 µA 2.4 V Input current Output current VCC = MIN VIN or VIL IOL Low VOL = .5 (MAX) 48 mA IOH High VOH = 2.4 (MIN) –16 mA VCC = MAX IOZH Output leakage2 VIN = VIL or VIH, VOUT = 2.7V 100 µA IOZL Output leakage2 VIN = VIL or VIH, VOUT = 0.4V –100 µA –190 mA 185 mA ISC Short circuit3 VOUT = 0.5 V ICC VCC supply current VCC = MAX –30 NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IOZX or IIX (where X = H or L). 3. No more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 1995 Sep 26 3 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER LIMITS1 TEST CONDITIONS MIN TYP UNIT MAX Active-LOW 3.5 7.5 Active-HIGH 3.5 7.5 tPD Input or feedback to non-registered output2, 4 tS Setup time from input, feedback or SP to Clock tH Hold time tCO Clock to output4, 7 tCF Clock to feedback3 tAR Asynchronous Reset to registered output tARW Asynchronous Reset width 7.5 ns tARR Asynchronous Reset recovery time 5.5 ns tSPR Synchronous Preset recovery time 5.0 ns tWL Width of Clock LOW 3.0 ns tWH Width of Clock HIGH 3.0 ns 87/83 MHz 125 MHz 5.5 ns 0 ns 3.0 Maximum frequency; External feedback 1/(tS + tCO)4,7 fMAX ns Maximum frequency; Internal feedback 1/(tS + tCF)4 6.0/6.5 ns 2.5 ns 10.0 ns tEA Input to Output Enable5 7.5 ns tER Disable5 7.5 ns Input to Output Capacitance6 CIN COUT Input Capacitance (Pin 1) VIN = 2.0V VCC = 5.0V 6 pF Input Capacitance (Others) VIN = 2.0V Tamb = 25°C 6 pF VOUT = 2.0V f = 1MHz 8 pF Output Capacitance NOTES: 1. Commercial Test Conditions: R1 = 300Ω, R2 = 390Ω (see Test Load Circuit). 2. tPD is tested with switch S1 closed and CL = 50pF (including jig capacitance). VIH = 3V, VIL = 0V, VT = 1.5V. 3. Calculated from measured fMAX internal. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 7. For PLCC package, tCO = 6.0ns; for DIP package, tCO = 6.5ns TEST LOAD CIRCUIT VOLTAGE WAVEFORM VCC +5V S1 +3.0V C1 C2 90% R1 F0 I0 10% R2 0V CL DUT tR INPUTS CK NOTE: C1 and C2 are to bypass VCC to GND. 2.5ns Fn In 1995 Sep 26 tF 2.5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. OE GND Input Pulses SP00369 SP00407 4 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 TIMING CHARACTERIZATION Delta tPD vs # of Outputs Switching (VCC = 5.0V, temp = 25°C, cap = 50pF) 0 0 –0.2 –0.2 –0.4 –0.4 Delta tpd (ns) Delta tcko (ns) Delta tCKO vs # of Outputs Switching (VCC = 5.0V, temp = 25°C, cap = 50pF) –0.6 –0.8 –0.6 –0.8 –1 –1 1 2 3 4 5 6 7 8 9 10 1 2 3 Number of Outputs Switching Delta tCKO vs Output Capacitance (VCC = 5.0V, temp = 25°C, 1 output switching) 6 5 6 7 8 9 10 Delta tPD vs Output Capacitance (VCC = 5.0V, temp = 25°C, 1 output switching) 6 RISE RISE FALL FALL 5 5 4 4 Delta tpd (ns) Delta tcko (ns) 4 Number of Outputs Switching 3 2 3 2 1 1 0 0 –1 –1 0 100 200 300 400 0 Output Capacitance 100 200 300 400 Output Capacitance The timing characterization represents the average values of a representative sample for each parameter. The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design. Philips guarantees the MAX AC CHARACTERIZATION specifications. SP00408 Figure 1. Device Characterization 1995 Sep 26 5 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 TIMING CHARACTERIZATION Normalized tCKO vs Temperature (VCC = 5.0 V, cap = 50 pF, 1 output switching) Normalized tPD vs Temperature (VCC = 5.0 V, cap = 50 pF, 1 output switching) 1.1 RISE RISE FALL FALL 1.05 1.05 1 1 Normalized tpd Normalized tcko 1.1 0.95 0.95 0.9 0.9 0.85 0.85 0.8 0.8 –50 –25 0 25 50 Temperature (°C) 75 100 –50 125 0 25 50 Temperature (°C) 75 100 125 Normalized tPD vs VCC (VCC = 5.0 V, cap = 50 pF, 1 output switching) Normalized tCKO vs VCC (VCC = 5.0 V, cap = 50 pF, 1 output switching) 1.1 1.1 RISE RISE FALL FALL 1.05 1.05 1 1 Normalized tpd Normalized tcko –25 0.95 0.95 0.9 0.9 0.85 0.85 0.8 0.8 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 4.5 5.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 Supply Voltage (V) Supply Voltage (V) The timing characterization represents the average values of a representative sample for each parameter. The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design. Philips guarantees the MAX AC CHARACTERIZATION specifications. SP00409 Figure 1. Device Characterization (continued) 1995 Sep 26 6 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as if every fuse is programmed. PRODUCT FEATURES Metastable Immune Flip-flops The D-type flip-flops have been designed such that the outputs will not glitch or display an output anomaly if the input set up or hold times are violated. Based on a τ of 83pS, and sampling the output 8ns after the clock edge, the typical MTBF is 104 years. If the sample is taken 8.5ns after the clock, the MTBF is 43,095 years. (See page 11.) Quality and Testability The ABT22V10 offers a very high level of built-in quality. Extra programmable fuses provide a means of verifying performance of all AC and DC parameters. In addition, this verifies programmability and functionality of the device to provide the highest programming and post-programming functional yields. Low Ground Bounce The Philips Semiconductors BiCMOS QUBiC process produces exceptional noise immunity. The typical ground bounce, with 9 outputs simultaneously switching and the 10th output held low, is less than 0.8V. (See page 12.) Technology The BiCMOS ABT22V10 is fabricated with the Philips Semiconductors process known as QUBiC. QUBiC combines an advanced, state-of-the-art 1.0µm (drawn feature size) CMOS process with an ultra fast bipolar process to achieve superior speed and drive capabilities. QUBiC incorporates three layers of Al/Cu interconnects for reduced chip size, and our proven Ti-W fuse technology ensures highest programming yields. Programmable 3-stage Outputs Each output has a 3-Stage output buffer with 3-State control. A product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bidirectional I/O pin, and may be configured as a dedicated input if the buffer is always disabled. Programming The ABT22V10-7 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL CUPL and PALASM 90 design software packages also support the ABT22V10-7 architecture. Programmable Output Parity The polarity of each macro cell output can be Active-HIGH or Active-LOW, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. All packages allow Boolean and state equation entry formats, SNAP, ABEL and CUPL also accept, as input, schematic capture format. Selection is controlled by programmable bit S0 in the Output Macro Cell, and affects both registered and combinatorial outputs. Selection is automatic, based on the design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be Active-HIGH (S0 = 1). (See page 15.) PROGRAMMING/SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Support material) of the1994 PLD data handbook for additional information. OUTPUT REGISTER PRELOAD Preset/Reset The register on the ABT22V10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired sate. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. The procedure for preloading follows: 1. Raise VCC to 5.0V ± 0.25V. For initialization, the ABT22V10 has additional Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous Preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the Asynchronous Reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW, independent of the clock. Note that Preset and Reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected. (See page 16.) 2. Set pin 2 or 3 to VHH to disable outputs and enable preload. Power-Up Reset 4. Clock Pin 1 from VILP to VIHP. 3. Apply the desired value (VILP/VIHP) to all registered output pins. Leave combinatorial output pins floating. All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the ABT22V10 will depend on the programmed output polarity. The VCC rise must be monotonic and the reset delay time is 1–10µs maximum. (See page 18.) 5. Remove VILP/VIHP from all registered output pins. 6. Lower pin 2 or 3 to VILP. Security Fuse 7. Enable the output registers according to the programmed pattern. After programming and verification, a ABT22V10 design can be secured by programming the security fuse link. Once programmed, 8. Verify VOL/VOH at all registered output pins. Note that the output pin signal will depend on the output polarity. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. PALASM is a registered trademark of AMD Corp. 1995 Sep 26 7 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 The ABT22V10A55 and ABT22V10A7 offer high performance with live insertion capability, as well as high drive and low noise. Live insertion refers to the ability of the outputs to remain 3-Stated during power supply ramp. This is a key feature for many telecom applications, where boards are inserted into powered–up systems. System integrity is maintained as the device powers up in a well-defined manner. PHILIPS ABT FEATURES The ABT22V10-7 is the first in a complete family of 22V10s targeted to meet the high performance needs of the design community. In addition to the high speed characteristics of the devices, Philips has designed the devices with advanced features to ensure high system reliability. The ABT22V10-7 is the only programmable device that guarantees metastable immunity while providing high drive and low noise. ABT22V10-7 ABT22V10A5 ABT22V10A7 Live Insertion NO YES YES Dual Verify NO YES YES Immune NO NO Source Drive Capability 16mA (VOH = 2.4V) 16mA (VOH = 2.4V) 16mA (VOH = 2.4V) Sink Drive Capability 48mA (VOL = 0.5V) 48mA (VOL = 0.5V) 48mA (VOL = 0.5V) Low Ground Bounce YES YES YES Plastic Dual In-line (N) 24-Pin not available not available Plastic Leaded Chip Carrier (A) 28-Pin 28-Pin 28-Pin Standard Evolutionary Evolutionary Metastability Package Availability: Pinout 1995 Sep 26 8 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD Figure 3 shows that for a non-metastable immune device, the Q output can vay in time with respect to the Q trigger point. this also implies that the Q or Q output waveshapes may be distorted. This can be erified on an analog scope with a charge plate CRT. Of even greater interest are the dots running along the 3.5V volt line in the upper right-hand quadrant. These show that the Q output did not change state even though the Q output glitched to at least 1.5 volts, the trigger point of the scope. Metastable Immune Characteristics What is metastable immunity? Philips Semiconductors uses the term ‘metastable immune’ to describe a combination of two characteristic features. The first is a patented Philips circuit that prevents the outputs from glitching, oscillating, or remaining in the linear region under any circumstances, including setup and hold time violations. The second is the flip-flop’s inherent ability of resolving the metastable condition. When the device-under-test is a metastable immune part, the waveform will appear as in Figure 4. The output will not vary with respect to the Q trigger point even when the part is driven into a metastable state. Any tendency towards internal metastability is resolved by Philips Semiconductors patented circuitry. If a metastable event occurs within the flip-flop, the only outward manifestation of the event will be an increased clock-to-Q delay. This delay is a function of the metastability characteristics of the device, defined by τ and T0 as described in the Design Example that follows. Since the outputs never glitch, oscillate, or remain in the linear region, the only metastable failure that can propagate further into the system is when the next flip-flop in the system samples the ABT22V10-7’s outut at recisely the same time it is making a logic transition. By allowing sufficient time for any increased clock-to-Q delay, propagation of metastable failures can be avoided. The following design example illustrates this concept. For example, using a non-metastable immune device, a typical metastabel condition could result by running two independent signal genrators (see Figure 2) at nearly the same frequency (in this case 10MHz clock and 10.02MHz data). This device-under-test can often be driven into a metastable state. If the Q outut is used to trigger a digital scope set to infinite persistence, the Q output will build a waveform. SIGNAL GENERATOR D Q TRIGGER DIGITAL SCOPE SIGNAL GENERATOR CP Q INPUT SP00410 Figure 2. Test Set-up 1995 Sep 26 ABT22V10-7 9 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 COMPARISON OF METASTABLE IMMUNE AND NON-IMMUNE CHARACTERISTICS 4 3 2 1 0 Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive SA00006 Figure 3. Non-immune Q output triggered by Q output, Setup and Hold times violated 3 2 1 0 Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive SA00007 Figure 4. Metastable Immune Q output triggered by Q output, Setup and Hold times violated 1995 Sep 26 10 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD output is sampled (t > TCO). T0 and τ are derived from tests and can most nearly be defined as follows: Design Example Suppose a designer wants to use the ABT22V10-7 for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), in a 5V system that has a clock frequency of 50MHz, at an ambient temperature of 25°C. She has decided that she would like to sample the output of the ABT22V10 8.5ns after the clock edge to ensure that any clock-to-Q delays that were the result of the ABT22V10 internal metastability resolution circuitry have completed and the outputs have transitioned. The MTBF for this situation can be calculated by using the equation below: MTBF τ is a function of the rate at which a latch in a metastable state resolves that condition. T0 is a function of the measurement of the propensity of a latch to enter a metastable state. T0 is also a normalization constant which is a very stron function of the normal propagation delay of the device. In this situation, the FI will be twice the data frequency, or 20MHz, because input events consist of both low and high transitions. Thus, in this case, FC is 50MHz, FI is 20MHz, τ is 83ps, t is 8.5ns, and T0 is 2.2 × 1017 seconds. Using the above formula, the actual MTBF for this situation is 1.36 × 1012 seconds, or 43,095 years for the ABT22V10-7. t e ABT22V10-7 T 0F C F I In this formula, FC is the frequency of the clock, FI is the average input event frequency, and t is the time after the clock pulse that the ABT22V10–7 VALUES FOR τ AND T0 Tamb = 0°C VCC τ Tamb = 25°C τ T0 Tamb = 70°C T0 τ T0 5.5V 83ps 8.1 × sec 82ps 7.5 × sec 101ps 3.0 × 1012 sec 5.0V 80ps 4.0 × 1018 sec 83ps 2.2 × 1017 sec 98ps 4.4 × 1011 sec 4.5V 85ps 3.4 × 1014 sec 91ps 2.5 × 1012 sec 106ps 1.1 × 108 sec 1018 Summary The Philips ABT22V10-7 has on-chip circuitry that completely eliminates any output glitches, oscillations, or other output anomalies associated with metastable conditions. For outputs that are then used to generate clocks, control signals or other asynchonous data, this represents an unparalled level of reliability in a PLD. In addition, a complete set of metastability data is provided, which allows designers the ability to design extremely robust systems where data is synchronously pipelined. 1995 Sep 26 11 1018 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 LOW NOISE 4V 3V 2V output F9 pin 27 800mV 1V 0V GND –1V –2V –3V –4V 5.0 nS/Division SP00414 Figure 5. Device Characterization Ground Bounce Figure 5 shows the low ground (VOLP) bounce (0.8V) observed on the 10th output of the ABT22V10 under the following conditions: 9 remaining outputs switching, each driving 50pF loads, in PLCC non-socketed device, at 5.25V, 25°C. Similar testing of comparable EECMOS 22V10 devices resulted in ground bounce in the 1.5 – 2.0V range. At Philips the utilization of our advanced BiCMOS process, QUBiC, enables the production of high performance devices with the lowest output noise to ensure first pass system reliability. Quiet your concerns on ground bounce with Philips ABT22V10-7. 1995 Sep 26 12 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 LOGIC DIAGRAM CLK/I0 1 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 24 VCC 43 AR 0 1 DAR 9 SP Q Q 1 1 0 0 0 1 0 1 23 F9 1 1 0 0 0 1 0 1 22 F8 1 1 0 0 0 1 0 1 21 F7 1 1 0 0 0 1 0 1 20 F6 1 1 0 0 0 1 0 1 19 F5 1 1 0 0 0 1 0 1 18 F4 1 1 0 0 0 1 0 1 17 F3 1 1 0 0 0 1 0 1 16 F2 1 1 0 0 0 1 0 1 15 F1 1 1 0 0 0 1 0 1 14 F0 13 I11 0 1 10 DAR 20 I1 SP Q Q 0 1 2 21 DAR SP 33 I2 Q Q 0 1 3 34 DAR SP Q Q 48 I3 0 1 4 49 DAR SP Q Q 65 I4 0 1 5 66 DAR SP Q Q 82 I5 0 1 6 83 DAR SP Q Q 97 I6 0 1 7 98 DAR SP 110 I7 Q Q 0 1 8 111 DAR 121 I8 SP Q Q 0 1 9 122 DAR 130 SP I9 10 SP 131 I10 11 GND 12 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 NOTE: Programmable connection. 1995 Sep 26 35 36 39 40 Q Q 0 1 43 SP00059 13 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 FUNCTIONAL DIAGRAM CLK/I0 I1 – I11 1 11 PROGRAMMABLE AND ARRAY (44 × 132) 8 RESET OUTPUT MACRO CELL 10 OUTPUT MACRO CELL 12 OUTPUT MACRO CELL 14 OUTPUT MACRO CELL 16 16 OUTPUT MACRO CELL OUTPUT MACRO CELL 14 OUTPUT MACRO CELL 12 OUTPUT MACRO CELL 10 OUTPUT MACRO CELL 8 OUTPUT MACRO CELL PRESET F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 SP00060 Figure 6. Functional Diagram configuration bits S0 – S1. Multiplexer controls are connected to ground (0) through a programmable fuse link, selecting the “0” path through the multiplexer. Programming the fuse disconnects the control line from GND and it floats to VCC (1), selecting the “1” path. FUNCTIONAL DESCRIPTION The ABT22V10 allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function. The device is produced with a fuse link at each input to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easily-implemented programming algorithm, these products can be rapidly programmed to any customized pattern. Information on approved programmers can be found in the Programmer Reference Guide. Extra test fuses are pre-programmed during manufacturing to ensure extremely high field programming yields, and provide extra test paths to achieve parametric correlation. Product terms with all fuses opened assume the logical HIGH state; product terms connected to both True and Complement of any single input assume the logical LOW state. The ABT22V10 has 12 inputs and 10 I/O Macro Cells (Figure 6). The Macro Cell allows one of four potential output configurations, registered output or combinatorial I/O, Active-HIGH or Active-LOW (see Figure 7). The configuration choice is made according to the user’s design specification and corresponding programming of the 1995 Sep 26 14 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 OUTPUT MACRO CELL 1 0 1 1 Q 0 0 Q 0 1 AR D CLK SP F S1 S0 OUTPUT CONFIGURATION 0 0 Registered/Active-LOW 0 1 Registered/Active-HIGH 1 0 Combinatorial/Active-LOW 1 1 Combinatorial/Active-HIGH 0 = Unprogrammed fuse 1 = Programmed fuse S1 S0 0 1 SP00375 Figure 7. Output Macro Cell Logic Diagram S0 = 0 S1 = 0 AR D Q CLK S0 = 0 S1 = 1 F F Q SP a. Registered/Active-LOW S0 = 1 S1 = 0 AR D Q CLK c. Combinatorial/Active-LOW S0 = 1 S1 = 1 F F Q SP d. Combinatorial/Active-HIGH b. Registered/Active-HIGH SP00376 Figure 8. Output Macro Cell Configurations Registered Output Configuration Variable Input/Output Pin Ratio Each Macro Cell of the ABT22V10 includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the registered configuration (S1 = 0), the array feedback is from Q of the flip-flop. The ABT22V10 has twelve dedicated input lines, and each Macro Cell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to VCC or GND. Combinatorial I/O Configuration Any Macro Cell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (S1 = 1). In the combinatorial configuration, the feedback is from the pin. 1995 Sep 26 15 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 SWITCHING WAVEFORMS INPUT OR FEEDBACK INPUT OR FEEDBACK VT VT tPD COMBINATORIAL OUTPUT tS tH CLOCK VT VT tCO REGISTERED OUTPUT Combinatorial Output VT Registered Output CLK tS + tCF CLOCK tS LOGIC VT REGISTER tCF Clock to Feedback (fMAX Internal) (See Path at Right) Clock to Feedback INPUT VT tWH tER CLOCK VT tEA VOH – 0.5V OUTPUT VT VOL + 0.5V tWL Clock Width Input to Output Disable/Enable tARW INPUT ASSERTING ASYNCHRONOUS RESET INPUT ASSERTING SYNCHRONOUS PRESET VT tAR REGISTERED OUTPUT VT tS CLOCK VT tARR CLOCK tH tSPR VT VT tCO REGISTERED OUTPUT VT Asynchronous Reset VT Synchronous Preset SP00377 NOTES: 1. VT = 1.5V. 2. Input pulse amplitude 0V to 3.0V. 3. Input rise and fall times 2.5ns max. 1995 Sep 26 16 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 “AND” ARRAY – (I, B) I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B P, D I, B P, D I, B P, D P, D STATE CODE STATE CODE STATE CODE INACTIVE1 O TRUE H COMPLEMENT L STATE CODE DON’T CARE — SP00008 NOTE: 1. This is the initial state. PRELOAD SET-UP LIMITS SYMBOL PARAMETER UNIT MIN REC MAX VHH Super-level input voltage 9.5 9.5 10 V VILP Low-level input voltage 0 0 0.8 V VIHP High-level input voltage 2.4 5.0 5.5 V tD Delay time 100 200 1000 ns tI/O I/O valid after Pin 2 or 3 drops from VHH to VILP 100 ns VHH PINS 2, 3 VILP tD tD REGISTERED OUTPUTS DATA IN tI/O DATA OUT tD tD VIHP VOH VOL VILP VIHP CLOCK tD Output Register Preload Waveform 1995 Sep 26 17 VILP SP00373 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 VCC POWER 4V tPR REGISTERED ACTIVE-LOW OUTPUT tS CLOCK tWL Power-Up Reset Waveform SP00066 LIMITS SYMBOL PARAMETER UNIT MIN tPR Power-up Reset Time tS Input or Feedback Setup Time tWL Clock Width LOW 1 µs See AC Electrical Characteristics POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown above. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. 1995 Sep 26 MAX 18 Philips Semiconductors Product specification Low noise, high drive, metastable immune, PLD ABT22V10-7 SNAP RESOURCE SUMMARY DESIGNATIONS CLK/I0 I1 – I11 1 DINV10 11 NINV10 DINV10 PROGRAMMABLE AND ARRAY (44 × 132) AND DINV10 NINV10 NINV10 CKV10 8 10 OR RESET CLOCK output macro cell 12 OR output macro cell 14 OR output macro cell 16 OR 16 OR output macro cell output macro cell 14 OR 12 OR output macro cell 10 OR output macro cell output macro cell 8 OR output macro cell OR output macro cell PRESET OUTV10 F0 OUTV10 F1 OUTV10 F2 OUTV10 OUTV10 F3 F4 OUTV10 F5 OUTV10 F6 OUTV10 F7 OUTV10 F8 OUTV10 F9 OLMDIR AR OLMREG OUTV10 D F Q OLMINV CLK Q SP S1 S0 DINV10 0 NINV10 1 Output Macro Cell SP00413 1995 Sep 26 19