ICS840002I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS840002I is a 2 output LVCMOS/LVTTL Synthesizer optimized to generate Fibre Channel HiPerClockS™ reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 26.5625MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL1:0): 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and 53.125MHz. The ICS840002I uses ICS’ 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS840002I is packaged in a 16-pin TSSOP package. • Two LVCMOS outputs @ 3.3V, 17Ω typical output impedance • Selectable crystal oscillator interface or LVCMOS single-ended input • Output frequency range: 46.66MHz - 233.33MHz • VCO range: 560MHz - 700MHz • Supports the following output frequencies: 212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz • RMS phase jitter @ 212.5MHz (637KHz - 10MHz): 0.83ps (typical) Typical phase noise at 212.5MHz: Offset Noise Power 100Hz ............... -91.3 dBc/Hz 1KHz .............. -114.3 dBc/Hz 10KHz .............. -120.7 dBc/Hz 100KHz .............. -120.2 dBc/Hz ICS • Power supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V • -40°C to 85°C ambient operating temperature • Lead-Free package RoHS compliant FREQUENCY SELECT FUNCTION TABLE Inputs Input Frequency (MHz) F_SEL1 F_SEL0 M Divider Value N Divider Value M/N Ratio Value Output Frequency (MHz) 26.5625 0 0 24 3 8 212.5 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 26.04166 0 1 24 4 6 156.25 BLOCK DIAGRAM OE PIN ASSIGNMENT Pullup F_SEL0 nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD 2 F_SEL1:0 Pullup:Pullup nPLL_SEL Pulldown nXTAL_SEL Pulldown XTAL_IN 26.5625MHz OSC F_SEL1:0 0 1 00 01 10 11 XTAL_OUT TEST_CLK Pulldown 1 Phase Detector VCO 0 N ÷3 ÷4 ÷6 ÷12 (default) Q0 Q1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 F_SEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT ICS840002I 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View M = ÷24 (fixed) MR 840002AGI Pulldown www.icst.com/products/hiperclocks.html 1 REV. A MARCH 10, 2005 ICS840002I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number 1, 16 Name F_SEL0, F_SEL1 Type 2 nXTAL_SEL Input 3 TEST_CLK Input 4 OE Input 5 MR Input 6 nPLL_SEL Input 7 VDDA Power 8 9, 10 11 VDD XTAL_OUT, XTAL_IN VDDO Power Power Core supply pin. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Output supply pin. 12, 13 Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 14, 15 GND Power Power supply ground. Input Description Pullup Frequency select pins. LVCMOS/LVTTL interface levels. Selects between the crystal or TEST_CLK inputs as the PLL reference Pulldown source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Pulldown Single-ended LVCMOS/LVTTL clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the Pullup outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are Pulldown reset causing active outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = Pulldown reference clock frequency/n output divider. LVCMOS/LVTTL interface levels. Analog supply pin. Input NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum 4 Units pF CPD Power Dissipation Capacitance 8 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ROUT Output Impedance 3.3V±5% 14 17 21 Ω 2.5V±5% 16 21 25 Ω TABLE 3. FREQUENCY SELECT FUNCTION TABLE Input Frequency (MHz) 26.5625 F_SEL1 0 F_SEL0 0 26.5625 0 1 Inputs M Divider Value N Divider Value 24 3 24 M/N Divider Value 8 4 6 Output Frequency (MHz) 212.5 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 26.04166 0 1 24 4 6 156.25 840002AGI www.icst.com/products/hiperclocks.html 2 REV. A MARCH 10, 2005 ICS840002I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol VDD Parameter Core Supply Voltage VDDA Analog Supply Voltage Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 Units V 3.135 3.3 3.465 V 3.135 3.3 3.465 V 2.375 2.5 VDDO Output Supply Voltage 2.625 V IDD Power Supply Current 100 mA IDDA IDDO Analog Supply Current Output Supply Current 12 5 mA mA Maximum 2.625 Units V TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol VDD Parameter Core Supply Voltage Test Conditions Minimum 2.375 Typical 2.5 VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 95 mA IDDA IDDO Analog Supply Current Output Supply Current 12 5 mA mA 840002AGI www.icst.com/products/hiperclocks.html 3 REV. A MARCH 10, 2005 ICS840002I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% OR 2.5V±5%, OR VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current OE F_SEL0:1, nPLL_SEL, MR, nXTAL_SEL, TEST_CLK OE F_SEL0:1, nPLL_SEL, MR, nXTAL_SEL, TEST_CLK VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 Maximum Units VDD = 3.465V Minimum Typical 2 VDD + 0.3 V VDD = 2.625V 1.7 VDD + 0.3 V VDD = 3.465V -0.3 0.8 V VDD = 2.625V VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -0.3 0.7 V 5 µA 150 µA -150 µA VDD = 3.465V or 2.625V, VIN = 0V -5 µA VDDO = 3.3V±5% 2.6 V VDDO = 2.5V±5% 1.8 V VDDO = 3.3V or 2.5V±5% 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Mode of Oscillation Minimum Typical Maximum Units Fundamental Frequency 26.5625 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. 840002AGI www.icst.com/products/hiperclocks.html 4 REV. A MARCH 10, 2005 ICS840002I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol fOUT tsk(o) tjit(Ø) tR / tF Parameter Output Frequency Range Test Conditions Minimum Typical F_SEL[1:0] = 00 186.67 226.67 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MH z F_SEL[1:0] = 11 46.67 56.67 MH z 12 ps Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 Output Rise/Fall Time 212.5MHz @ Integration Range: 637KHz - 10MHz 159.375MHz @ Integration Range: 637KHz - 10MHz 156.25MHz @ Integration Range: 1.875MHz - 20MHz 106.25MHz @ Integration Range: 637KHz - 10MHz 53.125MHz @ Integration Range: 637KHz - 10MHz 20% to 80% Units 0.83 ps 0.62 ps 0.59 ps 0.80 ps 0.68 ps 200 F_SEL[1:0] ≠ 00 46 F_SEL[1:0] = 00 42 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. odc Maximum Output Duty Cycle 700 ps 54 58 % % Maximum Units TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency Range tsk(o) Output Skew; NOTE 1, 3 tjit(Ø) tR / tF RMS Phase Jitter (Random); NOTE 2 Output Rise/Fall Time Test Conditions Minimum F_SEL[1:0] = 00 186.67 226.67 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MH z F_SEL[1:0] = 11 46.67 56.67 MH z 12 ps 212.5MHz @ Integration Range: 637KHz - 10MHz 159.375MHz @ Integration Range: 637KHz - 10MHz 156.25MHz @ Integration Range: 1.875MHz - 20MHz 106.25MHz @ Integration Range: 637KHz - 10MHz 53.125MHz @ Integration Range: 637KHz - 10MHz 20% to 80% Typical 0.73 ps 0.62 ps 0.56 ps 0.76 ps 0.72 ps 200 F_SEL[1:0] ≠ 00 46 odc Output Duty Cycle F_SEL[1:0] = 00 42 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 840002AGI www.icst.com/products/hiperclocks.html 5 700 ps 54 58 % % REV. A MARCH 10, 2005 ICS840002I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 6C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol fOUT tsk(o) tjit(Ø) tR / tF Parameter Output Frequency Range Test Conditions Minimum Typical F_SEL[1:0] = 00 186.67 226.67 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MH z F_SEL[1:0] = 11 46.67 56.67 MH z 12 ps Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 Output Rise/Fall Time 212.5MHz @ Integration Range: 637KHz - 10MHz 159.375MHz @ Integration Range: 637KHz - 10MHz 156.25MHz @ Integration Range: 1.875MHz - 20MHz 106.25MHz @ Integration Range: 637KHz - 10MHz 53.125MHz @ Integration Range: 637KHz - 10MHz 20% to 80% 840002AGI Output Duty Cycle www.icst.com/products/hiperclocks.html 6 Units 0.78 ps 0.67 ps 0.69 ps 0.82 ps 0.75 ps 200 F_SEL[1:0] ≠ 00 46 F_SEL[1:0] = 00 42 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. odc Maximum 700 ps 54 58 % % REV. A MARCH 10, 2005 ICS840002I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 53.125MHZ @3.3V ➤ 0 -10 -20 Fibre Channel Filter NOISE POWER dBc Hz -30 -40 53.125MHz -50 RMS Phase Jitter (Random) 637KHz to 10MHz = 0.68ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ -120 -130 -140 ➤ -150 -160 -170 Phase Noise Result by adding Fibre Channel Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 212.5MHZ @3.3V ➤ 0 -10 -20 Fibre Channel Filter -40 212.5MHz -50 RMS Phase Jitter (Random) 637KHz to 10MHz = 0.83ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 ➤ NOISE POWER dBc Hz -30 -110 -120 -130 -140 ➤ -150 -160 Phase Noise Result by adding Fibre Channel to raw data -170 -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 840002AGI www.icst.com/products/hiperclocks.html 7 REV. A MARCH 10, 2005 ICS840002I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2.05V±5% 1.25V±5% 1.65V±5% SCOPE VDD, VDDA, VDDO Qx LVCMOS SCOPE VDD, VDDA VDDO Qx LVCMOS GND GND -1.25V±5% -1.65V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.25V±5% Noise Power Phase Noise Plot SCOPE VDD, VDDA, VDDO Qx LVCMOS Phase Noise Mask GND Offset Frequency f1 RMS Jitter = Area Under the Masked Phase Noise Plot -1.25V±5% 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER V 80% DDO Qx 80% 2 Clock Outputs V DDO Qy f2 20% 20% tR tF 2 t sk(o) OUTPUT SKEW OUTPUT RISE/FALL TIME V DDO 2 Q0, Q1 Pulse Width t odc = PERIOD t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 840002AGI www.icst.com/products/hiperclocks.html 8 REV. A MARCH 10, 2005 ICS840002I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840002I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VDDA. 3.3V or 2.5V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS840002I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p ICS840002I Figure 2. CRYSTAL INPUt INTERFACE 840002AGI www.icst.com/products/hiperclocks.html 9 REV. A MARCH 10, 2005 ICS840002I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE and C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1KΩ pullup or pulldown resistors can be used for the logic control input pins. Figure 3 shows a schematic example of the ICS840002I. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used. The C1=22pF Logic Control Input Examples Set Logic Input to '1' VDD RU1 1K Set Logic Input to '0' VDD R2 33 RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins U1 RD2 1K VDD 1 2 3 4 5 6 7 8 VDDA R1 10 C3 10uF Zo = 50 Ohm VDD C4 0.01u LVCMOS FSEL0 XTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD FSEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT 16 15 14 13 12 11 10 9 VDD R3 100 C6 0.1u Zo = 50 Ohm C5 0.1u ICS840002i R4 100 XTAL2 If not using the crystal input, it can be left floating. For additional protection the XTAL_IN pin can be tied to ground. LVCMOS C2 22pF X1 XTAL1 Optional Termination C1 22pF Unused output can be left floating. There should no trace attached to unused output. Device characterized with all outputs terminated. FIGURE 3. ICS840002I SCHEMATIC EXAMPLE 840002AGI www.icst.com/products/hiperclocks.html 10 REV. A MARCH 10, 2005 ICS840002I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 137.1°C/W 89.0°C/W 118.2°C/W 81.8°C/W 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS840002I is: 3085 840002AGI www.icst.com/products/hiperclocks.html 11 REV. A MARCH 10, 2005 ICS840002I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER 16 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 16 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 840002AGI www.icst.com/products/hiperclocks.html 12 REV. A MARCH 10, 2005 ICS840002I Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 9. ORDERING INFORMATION Part/Order Number ICS840002AGI ICS840002AGIT ICS840002AGILF ICS840002AGILFT Marking ICS840002AI ICS840002AI TBD TBD The aforementioned trademarks, HiPerClockS™ and FEMTOCLOCKS™ Package 16 Lead TSSOP 16 Lead TSSOP 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP Shipping Packaging 94 per tube 2500 94 per tube 2500 Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840002AGI www.icst.com/products/hiperclocks.html 13 REV. A MARCH 10, 2005