Philips Semiconductors RF Communications Products Product specification Divide by: 128/129-64/65 dual modulus low power ECL prescaler DESCRIPTION FEATURES The SA701 is an advanced dual modulus (Divide By 128/129 or 64/65) low power ECL prescaler. The minimum supply voltage is 2.7V and is compatible with the CMOS UMA1005 synthesizer from Philips and other logic circuits. The low supply current allows application in battery operated low-power equipment. Maximum input signal frequency is 1.1GHz for cellular and other land mobile applications. There is no lower frequency limit due to a fully static design. The circuit is implemented in ECL technology on the QUBiC process. The circuit will be available in an 8-pin SO package with 150 mil package width and in 8-pin dual in-line plastic package, and is pin compatible with Fujitsu MB501, Plessey SP8704 and Motorola MC12022. SA701 PIN CONFIGURATION • Low voltage operation • Low current consumption • Operation up to 1.1GHz • ESD hardened N, D Package APPLICATIONS IN 1 8 IN VC 2 7 nc C SW 3 6 MC OUT 4 5 GND • Cellular phones • Cordless phones • RF LANs • Test and measurement • Military radio • VHF/UHF mobile radio • VHF/UHF hand-held radio ORDERING INFORMATION TEMPERATURE RANGE ORDER CODE 8-Pin Plastic Dual In-Line Package (DIP) DESCRIPTION -40 to +85°C SA701N DWG # 0404B 8-Pin Plastic Small Outline (SO) package (Surface-mount) -40 to +85°C SA701D 0174C ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER VCC Supply voltage VIN Voltage applied to any other pin IO Output current RATING UNITS -0.3 to +7.0 V -0.3 to (VCC + 0.3) V 10 mA Storage temperature range -65 to +125 °C TA Operating ambient temperature range -55 to +125 °C θJA Thermal impedance 158 108 °C/W TSTG June 17, 1993 D package N package 2 853-1708 10044 Philips Semiconductors RF Communications Products Product specification Divide by: 128/129-64/65 dual modulus low power ECL prescaler SA701 OUT BLOCK DIAGRAM Q D Q D Q Q Q D Q D Q Q D D Q D Q Q June 17, 1993 SW MC IN IN D 3 Philips Semiconductors RF Communications Products Product specification Divide by: 128/129-64/65 dual modulus low power ECL prescaler SA701 DC ELECTRICAL CHARACTERISTICS The following DC specifications are valid for TA = 25°C and VCC = 3.0V; unless otherwise stated. Test circuit Figure 1. SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN fIN = 1GHz, input level = 0dBm TYP 2.7 UNITS MAX VCC Power supply voltage range ICC Supply current VOH Output high level VOL Output low level VIH MC input high threshold 2.0 VCC V VIL MC input low threshold –0.3 0.8 V VIH SW input high threshold 2.0 VCC V VIL SW input low threshold –0.3 0.8 V IIH MC input high current VMC = VCC = 6V 50 µA No load 6.0 4.5 IOUT = 1.2mA VCC-1.4 V VCC-2.6 IIL MC input low current VMC = 0V, VCC = 6V IIH SW input high current VSW = VCC = 6V IIL SW input low current VSW = 0V, VCC = 6V 0.1 –100 V µA –30 35 –50 V mA 100 µA µA –0.1 AC ELECTRICAL CHARACTERISTICS The following AC specifications are valid for VCC = 3.0V, fIN = 1GHz, input level = 0dBm, TA = 25°C; unless otherwise stated. Test circuit Fig. 1. SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN VIN fIN Input signal amplitude1 1000pF input coupling Input signal frequency Direct coupled input2 TYP UNITS MAX 0.05 2.0 VP-P 0 1.1 GHz 1.1 GHz 1000pF input coupling RID Differential input resistance DC measurement 5 VO Output voltage kΩ VCC = 5.0V 1.6 VP-P tS Modulus set-up time1 VCC = 3.0V 1.2 5 ns tH Modulus hold time1 0 ns tPD Propagation time 10 VP-P ns NOTES: 1. Maximum limit is not tested, however, it is guaranteed by design and characterization. 2. For fIN < 50MHz, minimum input slew rate of 32V/µs is required. DESCRIPTION OF OPERATION The SA701 comprises a frequency divider circuit implemented using a divide by 4 or 5 synchronous prescaler followed by a 5 stage synchronous counter, see BLOCK DIAGRAM. The normal operating mode is for SW (Modulus Set Switch) input to be set low and MC (Modulus Control) input to be set high in which case the circuit comprises a divide by 128. For divide by 129 the MC signal is forced low, causing the prescaler circuit to switch into divide by 5 operation for the last cycle of the synchronous counter. Similarly, for divide by 64 and 65 the SA701 will generate those respective moduli with the SW signal forced high, in which the fourth stage of the synchronous divider is June 17, 1993 bypassed. A truth table for the modulus values is given below: Table 1. Modulus MC SW 128 1 0 129 0 0 64 1 1 65 0 1 For minimization of propagation delay effects, the second divider circuit is synchronous to the divide by 4/5 stage output. The prescaler input is positive edge sensitive, and the output at the final count is a falling edge with propagation delay tPD relative to 4 the input. The rising edge of the output occurs at the count 64 for modulus 128/129 or count 32 for modulus 64/65 with delay tPD. The SW input is not designed for synchronous switching. The MC and SW inputs are TTL compatible threshold inputs operating at a reduced input current. CMOS and low voltage interface capability are allowed. The SW input has an internal pull-down simplifying modulus group selection. With SW open the divide by 128/129 mode is selected and with SW connected to VCC divide by 64/65 is selected. The prescaler input is differential and ECL compatible. The output is single-ended ECL compatible. Philips Semiconductors RF Communications Products Product specification Divide by: 128/129-64/65 dual modulus low power ECL prescaler SA701 AC TIMING CHARACTERISTICS COUNT 128 129 1 64 127 128 1 IN MC OUT tS tP tH SW = 0. DIVIDE BY 128/129 OPERATION. D COUNT 127 128 1 127 64 128 129 1 IN MC OUT tS tP D COUNT 64 65 tH SW = 0. DIVIDE BY 128/129 OPERATION. 1 32 63 64 1 IN MC OUT tS tP tH SW = 1. DIVIDE BY 64/65 OPERATION. D COUNT 63 64 1 32 63 64 65 1 IN MC OUT tP D June 17, 1993 tS SW = 1. DIVIDE BY 64/65 OPERATION. 5 tH Philips Semiconductors RF Communications Products Product specification Divide by: 128/129-64/65 dual modulus low power ECL prescaler SA701 IN IN 50Ω R1 50Ω 50Ω C1 1000pF R2 50Ω C2 1000pF IN IN VCC VCC NC SW SW MC OUT GND MC C3 0.1µF OUT R3 2.2kΩ C4 5pF Figure 1. SA701 Test Circuit FREQUENCY (MHz) 0 200 400 600 800 1000 MINIMUM INPUT POWER (dBm) –5 –10 –40°C –15 VCC = 3.0V –20 25°C 85°C –25 –30 –35 –40 Figure 2. Minimum Input Power vs Frequency and Temperature June 17, 1993 6 1200 Philips Semiconductors RF Communications Products Product specification Divide by: 128/129-64/65 dual modulus low power ECL prescaler SA701 FREQUENCY (MHz) 0 200 400 600 800 1000 MINIMUM INPUT POWER (dBm) –5 –10 2.7V –15 3.0V TA = 25°C –20 6.0V –25 –30 –35 –40 Figure 3. Minimum Input Power vs Frequency and VCC 6 85°C 5.5 25°C ICC (mA) 5 4.5 –40°C 4 3.5 3 2.7 3 6 7 VCC (V) Figure 4. Supply Current vs Supply Voltage and Temperature With No Load June 17, 1993 7 1200 Philips Semiconductors RF Communications Products Product specification Divide by: 128/129-64/65 dual modulus low power ECL prescaler SA701 j1 j0.5 j2 VCC = 3V j0.2 j5 0.2 0 0.5 1 R3 4Ω INPUT 5 2 TA = 25°C L4 6nH 50 R1 C2 0.4pF 300 3000Ω C1 0.9pF –j5 –j0.2 600 EQUIVALENT INPUT IMPEDANCE 900 –j0.5 –j2 1200 –j1 Figure 5. Typical N Package Input Impedance j1 j2 j0.5 j0.2 VCC = 3V j5 TA = 25°C 0 0.2 0.5 1 R3 2Ω INPUT 5 2 L4 3nH 50 C2 0.2pF R1 3000Ω 300 –j5 –j0.2 600 EQUIVALENT INPUT IMPEDANCE 900 –j0.5 1200 –j2 –j1 Figure 6. Typical D Package Input Impedance June 17, 1993 8 C1 0.9pF