PI6C3Q991A, PI6C3Q993A 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 3.3V Programmable Skew PLL Clock Driver SuperClock Features Description • PI6C3Q99X family provides following products: PI6C3Q991A: 32-pin PLCC version PI6C3Q993A: 28-pin QSOP version • Inputs are 5V Tolerant • 4 pairs of programmable skew outputs • Low skew: 200ps same pair; 250ps all outputs • Selectable positive or negative edge synchronization: Excellent for DSP applications • Synchronous output enable • Input frequency: 3.75 MHz to 110 MHz • Output frequency: 15 MHz to 110 MHz • 2x, 4x, 1/2, and 1/4 outputs • 3 skew grades: PI6C3Q99x: tSKEW0 <750ps PI6C3Q99x-5: tSKEW0 <500ps PI6C3Q99x-2: tSKEW0 <250ps • 3-level inputs for skew and PLL range control • PLL bypass for DC testing • External feedback, internal loop filter • 12mA balanced drive outputs • Low Jitter: < 200ps peak-to-peak • Industrial temperature range • Pin-to-pin compatible with IDT QS5V991A and QS5V993A • Available in 32-pin PLCC and 28-pin QSOP The PI6C3Q99X family, a high-fanout 3.3V PLL-based clock driver, is intended for high-performance computing and data-communication applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The PI6C3Q991A has 8 programmable skew outputs in 4 banks of 2, while the PI6C3Q993A has 6 programmable skew outputs and 2 zero skew outputs. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels. When the GND/sOE pin is held LOW, all the outputs are synchronously enabled. However, if GND/sOE is held HIGH, all outputs except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when the V CCQ /PE is held HIGH, all outputs are synchronized with the positive edge of the REF clock input. When VCCQ /PE is held LOW, all outputs are synchronized with the negative edge of REF. Both devices have LVTTL outputs with 12mA balanced drive outputs. Pin Configurations PI6C3Q993A 3F0 FS VCCQ REF GND TEST 2F1 PI6C3Q991A 4 3 2 5 6 1 32 31 30 29 28 FS 2F0 GND/sOE 1F1 1F0 VCCN 1Q0 1Q1 GND GND 3F0 3F1 VCCQ/PE VCCN 4Q1 4Q0 GND 3Q1 3Q0 VCCN FB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-Pin Q 28 GND 27 26 25 24 23 22 21 20 TEST 19 18 17 16 1Q1 15 2Q1 2F1 2F0 GND/sOE 1F1 1F0 VCCN 1Q0 GND GND 2Q0 VCCN FB VCCN 2Q1 2Q0 7 27 8 26 32-Pin 9 25 J 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 3Q1 3Q0 3F1 4F0 4F1 VCCQ/PE VCCN 4Q1 4Q0 GND GND REF VCCQ 1 PS8628A 02/06/03 PI6C3Q991A, PI6C3Q993A 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Logic Block Diagrams PI6C3Q993A PI6C3Q991A GND/sOE GND/sOE Skew Select 3 3 Skew Select 1Q1 3 1F1:0 VCCQ/PE Skew Select REF 1Q0 3 2Q1 Skew Select 3 3 REF 3Q1 Skew Select 3 3 2Q1 2F1:0 Skew Select 3 FS 2Q0 3 PLL 3 3F1:0 FS 3 FB 3Q0 3 1F1:0 Skew Select 2F1:0 PLL FB 1Q1 3 VCCQ/PE 2Q0 3 1Q0 3Q0 3Q1 3 3F1:0 4Q0 4Q0 4Q1 4Q1 4F1:0 Table 1. Pin Descriptions Pin Name Type Functional De s cription REF IN Reference Clock input FB IN Feedback Input TEST(1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see table 3) remain in effect. Set LOW for normal operation. GND/sOE(1) IN Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state 3Q0 or 3Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF [1:0] pins act as output disable controls for individual banks when nF [1:0] = LL. Set GND/sOE LOW for normal operation. VCCQ/ PE IN Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. nF [1:0] IN 3- level inputs for selecting 1of 9 skew taps or frequency range. FS IN Selects appropriate oscillator circuit based on anticipated frequency range. See table 2 nQ [1:0] OUT 4 output banks of 2 outputs, with programmable skew. On the PI6C3Q993A 4Q1:0 are fixed zero skew outputs. VCCN PWR Power supply for output buffers VCCQ PWR Power supply for phase locked loop and other internal circuitry GND PWR Ground Note: 1. When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] =LL functioning as an output disable control for individual output banks. Skew selections (see Table 3) remain in effect unless nF[1:0] = LL. 2 PS8628A 02/06/03 PI6C3Q991A, PI6C3Q993A 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Programmable Skew External Feedback Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit tU which is of the order of a nanosecond (see Table 2). There are 9 skew configurations available for each output pair. These configurations are choosen by the nF1:0 control pins. In order to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Skew Selection Table (Table 3) shows how to select specific skew taps by using the nF1:0 control pins. By providing external feedback, the PI6C3Q99x family gives users flexibility with regard to skew adjustment. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. Table 2. PLL Programmable Skew Range and Resolution Table Timing unit calculatio n (t U ) VC O freq uency range (F N O M) (2 , 3 ) FS = LOW FS = M ID FS = HIGH 1/(4 4 xF N O M ) 1/(2 6 xF N O M ) 1/(16 xF N O M ) 15 to 3 5 MHz 2 5 to 6 0 MHz 4 0 to 110 MHz S kew ad justment range(4 ) Max. ad justment ± 9 . 0 9 ns ± 49° ± 14% ± 9 . 2 3 ns ± 83° ± 23% Examp le 1, F N O M = 15 MHz tU = 1. 5 2 ns Examp le 2 , F N O M = 2 5 MHz tU = 0 . 9 1ns tU = 1. 5 4 ns Examp le 3 , F N O M = 3 0 MHz tU = 0 . 7 6 ns tU = 1. 2 8 ns ± 9 . 3 8 ns ± 135° ± 37% Examp le 4 , F N O M = 4 0 MHz tU = 0 . 9 6 ns tU = 1. 5 6 ns Examp le 5 , F N O M = 5 0 MHz tU = 0 . 7 7 ns tU = 1. 2 5 ns Examp le 6 , F N O M = 8 0 MHz Co mme nts ns P hase d egrees % o f cycle time tU = 0 . 7 8 ns Notes: 2. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest. 3. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided output as the FB input. 4. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range applies to output pairs 3 and 4 where ±6tU skew adjustment is possible and at the lowest FNOM value. 3 PS8628A 02/06/03 PI6C3Q991A, PI6C3Q993A 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 3. Skew Selection Table for Output Pairs nF1 :0 S k e w (Pa ir #1 , #2 ) S k e w (Pa ir #3 ) S k e w (Pa ir #4 )(5) LL(6) – 4 tU Divid e b y 2 Divid e b y 2 * LM – 3 tU – 6 tU – 6 tU LH – 2 tU – 4 tU – 4 tU ML – 1 tU – 2 tU – 2 tU MM Zero skew Zero skew Zero skew MH + 1 tU + 2 tU + 2 tU HL + 2 tU + 4 tU + 4 tU HM + 3 tU + 6 tU + 6 tU HH + 4 tU Divid e b y 4 * Inverted (7) Notes: 5. Programmable skew on pair #4 is not applicable for the PI6C3Q993A. 6. LL disables outputs if TEST = MID and GND/sOE = HIGH. 7. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when VCCQ /PE = HIGH, GND/sOE disables pair #4 LOW when VCCQ /PE = LOW. * The rising edge of 3Qx and 4Qx are not aligned only when both 3F1 : 0 = HH (divide by 4) and 4F1 : 0 = LL (divide by 2) are selected. This is not applicable for PI6C3Q993A. Table 4. Absolute Maximum Ratings Supply Voltage to Ground ...................................... –0.5V to 7.0V Input Voltage .......................................................... –0.5V to 7.0V Maximum Power Dissipation at TA = 85°C, PLCC ....... 0.80 watts QSOP ....... 0.66 watts TSTG Storage Temperature .................................. –65°C to 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings arestress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 5. Recommended Operating Range PI6C3Q991A/PI6C3Q993A PI6C3Q99A- 5/PI6C3Q993A- 5 (Indus trial) Symbol VC C TA De s cription PI6C3Q991A/PI6C3Q993A PI6C3Q991A- 2/PI6C3Q993A- 2 PI6C3Q991A- 5/PI6C3Q993A- 5 (Comme rcial) M in. M a x. M in. M a x. Units Power Supply Voltage 3.0 3.6 3.0 3.6 V Ambient Operating Temperature –40 85 0 70 °C 4 PS8628A 02/06/03 PI6C3Q991A, PI6C3Q993A 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 6. DC Characteristics Over Operating Range Symbol Parame te r Te s t Condition M in. M a x. VIH Input HIGH Voltage Guaranteed Logic HIGH (REF, FB inputs only) 2.0 5.5 VIL Input LOW Voltage Guaranteed Logic LOW (REF, FB inputs only) –0.5 0.8 VIHH Input HIGH Voltage(8) 3- Level Inputs Only VCC –0.6 VIMM Input MID Voltage(8) 3- Level Inputs Only VCC/2 –0.3 VILL Input LOW Voltage(8) 3- Level Inputs Only IIN Input Leakage Current (REF, FB inputs only) VIN = VCC or GND, VCC = Max. I3 3- Level Input DC Current (TEST, FS, nF1:0) VIN = VCC VIN = VCC/2 VIN = GND IPU Input Pull- Up Current (VCCQ/PE) VCC = Max., VIN = GND 100 IPD Input Pull- Down Current (GND/sOE) VCC = Max., VIN = VCC 100 VOH Output HIGH Voltage VCC = Min., IOH = –12mA VOL Output LOW Voltage VCC = Min., IOL = 12mA Units V VCC/2 +0.3 0.6 5 HIGH Level MID Level LOW Level 200 50 200 µA 2.2 V 0.55 Table 7. Power Supply Characteristics Symbol Typ. M ax. Units VCC = Max., TEST = Mid., REF = LOW, GND/sOE = LOW, All outputs unloaded 8.0 15 mA VCC = Max., VIN = 3.0V 1.0 30 µA Dynamic Power Supply Current per Output(9) VCC = Max., CL = 0pF 55 90 125 µA/ MHz IC Total Power Supply Current(9) VCC = 3.3V, FREF = 20 MHz, CL = 160pF(10) 29 IC Total Power Supply Current(9) VCC = 3.3V, FREF = 33 MHz, CL = 160pF(10) 42 IC Total Power Supply Current(9) VCC = 3.3V, FREF = 66 MHz, CL = 160pF(10) 76 ICCQ Parame te r Quiescent Power Supply Current ∆ICC N Power Supply Current per Input HIGH(9) ICCD Te s t Condition mA Notes: 8. These inputs are normally wired to VCC , GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and timing of the outputs may glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 9. Guaranteed by characterization but not production tested. 10. For 8 outputs each loaded with 20pF. 5 PS8628A 02/06/03 PI6C3Q991A, PI6C3Q993A 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 8. Capacitance (TA = 25°C, f = 1 MHz, VIN = 0V) QSOP CIN PLCC Typ. M ax. Typ. M ax. 4 6 5 7 Units pF VCC 150Ω Output 150Ω ≤1ns 20pF tORISE ≤1ns 3.0V 2.0V Vth=1.5V 0.8V 0V 2.0V tOFALL tPWL 0.8V tPWH LVTTL Input Test Waveform LVTTL Output Waveform Figure 1. AC Test Loads and Waveforms 6 PS8628A 02/06/03 PI6C3Q991A, PI6C3Q993A 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 9. Switching Characteristics Over Operating Range PI6C3Q991A-2 PI6C3Q993A-2 D e s cription S ymbol FNOM M in. VC O frequency range PI6C3Q991A-5 PI6C3Q993A-5 PI6C3Q991A PI6C3Q993A see Table 2 see Table 2 see Table 2 tRPWH (2 1 ) REF pulse width HIGH 3.0 3.0 3.0 tRPWL REF pulse width LO W(21) 3.0 3.0 3.0 tU tSK EWPR tSK EW0 tSK EW1 tSK EW2 P rogrammable skew time unit Zero output matched- pair skew (xQ 0, xQ 1) Zero output skew (all outputs) C L = 0pF O utput skew (rise- fall, nominal- inverted, divided- divided O utput skew (rise- rise, fall- fall, different class outputs) tP W H tP W L tO RISE 0.25 0.1 0.25 0.1 0.25 0.25 0.5 0.3 0.75 0.25 0.50 0.6 0.7 0.6 1.0 0.30 1.2 0.5 1.2 1.0 1.5 0.25 0.50 0.5 0.7 0.7 1.2 0.50 0.90 0.5 1.0 1.2 1.7 (11,12,16) Device- to- device skew 0.75 0 0.25 –0.5 0 0.5 –0.7 0 0.7 –1.2 0 1.2 –1.2 0 1.2 –1.2 0 1.2 O utput LO W time deviation from 50% (11,19) 2.0 2.5 3.0 (11,20) 1.5 3.0 3.5 (11) (11) O utput fall time P LL lock time(11,17) C ycle- to- cycle output jitter(11) 1.65 –0.25 O utput HIGH time deviation from 50% tLO C K 1.25 (11) O utput duty cycle varation from 50% O utput rise time see Table 3 (11,18) REF input to F B propagation delay tO FALL tJ R 0.1 (11,15) O utput skew (rise- fall, nominal- divided, divided inverted(11,15) tO DC V 0.20 (11,15) tSK EW4 tP D 0.05 (11,15) tSK EW3 tDEV see Table 3 (11,14) O utput skew (rise- rise, fall- fall, same class outputs) ns see Table 3 (11,12,13) Units Typ. M ax. M in. Typ. M ax. M in. Typ. M ax. 0.15 1.0 0.15 1.0 1.5 0.15 1.0 1.5 0.15 1.0 1.5 0.15 1.5 1.5 0.15 1.5 ns 2.5 2.5 0.5 0.5 0.5 RMS 25 40 40 P e a k - to - p e a k 200 200 200 ms ps Notes: 11. All timing tolerances apply for FNOM ≥ 25MHz. Guaranteed by design and characterization, not subject to 100% production testing. 12. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 13. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. 14. tSKEW0 is the skew between outputs when they are selected for 0tU. 15. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode). 16. tDEV is output-to-output skew between any two devices operating under the same conditions (VCC , ambient temperature, air flow, etc.) 17. tLOCK is time that is required before synchronization is achieved. This specification is valid only after VCC is stable & within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 18. tPD is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns. 19. Measured at 2.0V. 20. Measured at 0.8V. 21. Refer to Table10 for more detail. 7 PS8628A 02/06/03 PI6C3Q991A, PI6C3Q993A 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Table 10. Input Timing Requirements(22) Symbol De s cription M in. tR, tF Maximum input rise and fall times, 0.8V to 2.0V tPWC Input clock pulse, HIGH or LOW 3 Input duty cycle 10 DH M a x. Units 10 ns/V ns 90 % Notes: 22. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies. tREF tRPWH tRPWL REF tPD tODCV tODCV FB tJR Q tSKEWPR tSKEW0, 1 tSKEWPR tSKEW0, 1 Other Q tSKEW2 tSKEW2 Inverted Q tSKEW3,4 tSKEW3,4 tSKEW3,4 REF Divided by 2 tSKEW1,3,4 tSKEW2,4 REF Divided by 4 Figure 2. AC Timing Diagram Notes: VCCQ/PE: The AC timing diagram above applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75ohms to VCC/2. tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. tSKEW0: The skew between outputs when they are selected for 0t U. tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. t PWH is measured at 2.0V. t PWL is measured at 0.8V. tORISE & tOFALL are measured between 0.8V and 2.0V. 8 PS8628A 02/06/03 PI6C3Q991A, PI6C3Q993A 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 32-Pin PLCC Package Diagram 28-Pin QSOP Package Diagram 28 .008 0.20 MIN. 0.150 0.157 .008 .013 0.20 0.33 3.81 3.99 Guage Plane .010 0.254 1 Detail A .041 1.04 REF .386 9.804 .394 10.009 .033 REF 0.84 0˚-6˚ .016 .035 0.41 0.89 .015 x 45˚ 1.35 .053 1.75 .069 Detail A .007 0.178 .010 0.254 SEATING PLANE .025 BSC 0.635 .008 0.203 .012 0.305 0.41 .016 1.27 .050 .004 0.101 .010 0.254 .228 .244 5.79 6.19 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 9 PS8628A 02/06/03 PI6C3Q991A, PI6C3Q993A 3.3V Programmable Skew PLL Clock Driver SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Ordering Information Orde ring Code Package Code Package Type PI6C3Q991AJ J32 32- Pin PLCC PI6C3Q991A- 2J J32 32- Pin PLCC PI6C3Q991A- 5J J32 32- Pin PLCC PI6C3Q991A- IJ J32 32- Pin PLCC PI6C3Q991A- 5IJ J32 32- Pin PLCC PI6C3Q993AQ Q 28 28- Pin QSOP PI6C3Q993A- 2Q Q 28 28- Pin QSOP PI6C3Q993A- 5Q Q 28 28- Pin QSOP PI6C3Q993A- IQ Q 28 28- Pin QSOP PI6C3Q993A- 5IQ Q 28 28- Pin QSOP Ope rating Range Commercial Industrial Commercial Industrial Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 10 PS8628A 02/06/03