IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II JR. FEATURES: • • • • DESCRIPTION: Ref input is 5V tolerant 4 pairs of programmable skew outputs Low skew: 185ps same pair, 250ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Input frequency: 6MHz to 200MHz Output frequency: 6MHz to 200MHz 2x, 4x, 1/2, and 1/4 outputs 3-level inputs for skew and PLL range control PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <100ps cycle-to-cycle Available in TQFP package • • • • • • • • • • IDT5V9950 The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V9950 has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5V9950 has LVTTL outputs with 12mA balanced drive outputs. FUNCTIONAL BLOCK DIAGRAM sOE 1Q 0 Skew Select 3 1Q 1 3 1F1:0 PE TEST 3 3 REF 2Q 0 Skew Select 2Q 1 3 PLL 2F1:0 FB 3 3Q 0 Skew Select 3 3Q 1 3 FS 3F1:0 4Q 0 Skew Select 3 4Q 1 3 4F1:0 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE FEBRUARY 2002 1 c 2002 Integrated Device Technology, Inc. DSC 5870/4 IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. PIN CONFIGURATION INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) 3F 0 FS VDD REF GND TE ST 2F 1 2F 0 Symbol 32 31 30 29 28 27 26 25 Description Max VDDQ, VDD Supply Voltage to Ground VI DC Input Voltage –0.5 to +4.6 V –0.5 to VDD+0.5 V REF Input Voltage 3F 1 1 24 1F 1 4F 0 2 23 1F 0 4F 1 3 22 sOE PE 4 21 V DD Q V DDQ 5 20 1Q 0 4Q 1 6 19 1Q 1 4Q 0 7 18 GND GND 8 17 GND TSTG V TA = 85°C 0.7 W Dissipation TA = 55°C 1.1 Storage Temperature Range –65 to +150 °C CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V) 16 CIN Description Typ. Max. Unit 5 7 pF Input Capacitance NOTE: 1. Capacitance applies to all inputs except TEST, FS, nF[1:0], and DS[1:0]. 2Q 0 15 2Q 1 14 V DDQ 13 FB 12 V DDQ 11 3Q 0 3Q 1 G ND 10 –0.5 to +5.5 Maximum Power NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. Parameter 9 Unit TQFP TOP VIEW PIN DESCRIPTION Pin Name Type REF IN Description Reference Clock Input FB IN Feedback Input TEST (1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary sOE(1) IN Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down). PE IN Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference nF[1:0] IN 3-level inputs for selecting 1 of 9 skew taps or frequency functions FS IN Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.) Table) remain in effect. Set LOW for normal operation. clock (has internal pull-up). nQ[1:0] OUT Four banks of two outputs with programmable skew VDDQ PWR Power supply for output buffers VDD PWR Power supply for phase locked loop, lock output, and other internal circuitry GND PWR Ground NOTE: 1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL. 2 IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE PROGRAMMABLE SKEW Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit (tU) which ranges from 625ps to 1.3ns (see Programmable Skew Range and Resolution Table). There are nine skew configurations available for each output pair. These configurations are chosen by the nF1:0 control pins. In order to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the nF1:0 control pins. EXTERNAL FEEDBACK By providing external feedback, the IDT5V9950 gives users flexibility with regard to skew adjustment. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE FS = LOW FS = MID FS = HIGH Timing Unit Calculation (tU) 1/(32 x FNOM) 1/(16 x FNOM) 1/(8 x FNOM) VCO Frequency Range (FNOM)(1,2) 24 to 50MHz 48 to 100MHz 96 to 200MHz ±7.8125ns ±7.8125ns ±7.8125ns Comments Skew Adjustment Range(3) Max Adjustment: ns ±67.5° ±135° ±270° Phase Degrees ±18.75% ±37.5% ±75% % of Cycle Time Example 1, FNOM = 25MHz tU = 1.25ns — — Example 2, FNOM = 37.5MHz tU = 0.833ns — — Example 3, FNOM = 50MHz tU = 0.625ns tU = 1.25ns — Example 4, FNOM = 75MHz — tU = 0.833ns — Example 5, FNOM = 100MHz — tU = 0.625ns tU = 1.25ns Example 6, FNOM = 150MHz — — tU = 0.833ns Example 7, FNOM = 200MHz — — tU = 0.625ns NOTES: 1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. 2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as VCO when the output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for frequency multiplication by using a divided output as the FB input. 3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value. 3 IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS nF1:0 Skew (Pair #1, #2) Skew (Pair #3) Skew (Pair #4) LL (1) –4tU Divide by 2 Divide by 2 LM –3tU –6tU –6tU LH –2tU –4tU –4tU ML –1tU –2tU –2tU MM Zero Skew Zero Skew Zero Skew MH 1tU 2tU 2tU HL 2tU 4tU 4tU HM 3tU 6tU 6tU HH 4tU Divide by 4 Inverted (2) NOTES: 1. LL disables outputs if TEST = MID and sOE = HIGH. 2. When pair #4 is set to HH (inverted), sOE disables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW. RECOMMENDED OPERATING RANGE Symbol Description VDD/VDDQ Power Supply Voltage TA Min. Typ. Max. Unit 3 3.3 3.6 V -40 +25 +85 °C Ambient Operating Temperature DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol Conditions Min. Max. Unit VIH Input HIGH Voltage Parameter Guaranteed Logic HIGH (REF, FB Inputs Only) 2 — V — 0.8 V VDD−0.6 — V VDD/2−0.3 VDD/2+0.3 V VIL Input LOW Voltage Guaranteed Logic LOW (REF, FB Inputs Only) VIHH Input HIGH Voltage(1) 3-Level Inputs Only VIMM Input MID Voltage 3-Level Inputs Only VILL Input LOW Voltage 3-Level Inputs Only — 0.6 V IIN Input Leakage Current VIN = VDD or GND −5 +5 µA — +200 −50 −200 −100 +50 — µA (1) (1) (REF, FB Inputs Only) I3 3-Level Input DC Current (TEST, FS, nF[1:0]) IPU Input Pull-Up Current (PE) VDD = Max. VIN = VDD HIGH Level VIN = VDD/2 MID Level VIN = GND LOW Level VDD = Max., VIN = GND µA — IPD Input Pull-Down Current (sOE) VDD = Max., VIN = VDD — +100 µA VOH Output HIGH Voltage VDDQ = Min., IOH = −12mA 2.4 — V VOL Output LOW Voltage VDDQ = Min., IOL = 12mA — 0.4 V NOTE: 1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 4 IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Test Conditions(1) Symbol Parameter IDDQ Quiescent Power Supply Current Typ.(2) Max. Unit 20 30 mA 1 30 µA FS = L 190 290 FS = M 150 230 FS = H 130 200 VDD = Max., TEST = MID, REF = LOW, PE = LOW, sOE = LOW, FS = MID All outputs unloaded ∆IDD Power Supply Current per Input HIGH VIN = 3V, VDD = Max., TEST = HIGH (REF and FB inputs only) IDDD ITOT Dynamic Power Supply Current per Output Total Power Supply Current FS = L , FVCO = 50MHz, CL = 0pF 56 — FS = M , FVCO = 100MHz, CL = 0pF 80 — FS = H, FVCO = 200MHz, CL = 0pF 125 — µA/MHz mA NOTES: 1. Measurements are for divide-by-1 outputs and nF[1:0] = MM. 2. For nominal voltage and temperature. INPUT TIMING REQUIREMENTS Description(1) Symbol Min. Max. Unit — 10 ns/V Input clock pulse, HIGH or LOW 2 — ns Input duty cycle 10 90 % FS = LOW 6 50 FS = MID 12 100 FS = HIGH 24 200 tR, tF Maximum input rise and fall times, 0.8V to 2V tPWC DH FREF Reference clock input frequency NOTE: 1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies. 5 MHz IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter Min. Typ. Max. Unit FNOM VCO Frequency Range See Programmable Skew Range and Resolution Table tRPWH REF Pulse Width HIGH(1) 2 tRPWL REF Pulse Width LOW 2 tU (1) Programmable Skew Time Unit — — ns — — ns See Control Summary Table tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1)(2,3) — 50 185 ps tSKEW0 Zero Output Skew (All Outputs)(4) — 0.1 0.25 ns tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs) — 0.1 0.25 ns tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided) — 0.2 0.5 ns tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)(5) — 0.15 0.5 ns tSKEW4 Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted) — 0.3 0.9 ns — — 0.75 ns −0.25 −1 — 0.25 ns 0 1 ns — — 1.5 ns tDEV Device-to-Device Skew(2,6) t(φ) REF Input to FB Static Phase Offset) (5) (5) (2) (7) tODCV Output Duty Cycle Variation from 50% tPWH Output HIGH Time Deviation from 50%(8) tPWL Output LOW Time Deviation from 50% — — 2 ns tORISE Output Rise Time 0.15 0.7 1.5 ns tOFALL Output Fall Time 0.15 0.7 1.5 ns tLOCK PLL Lock Time ms tCCJH Cycle-to-Cycle Output Jitter (peak-to-peak) (9) (10) — — 0.5 — — 100 — — 150 — — 200 (divide by 1 output frequency, FS = H, FB divide-by-n=1,2) tCCJM Cycle-to-Cycle Output Jitter (peak-to-peak) ps (divide by 1 output frequency, FS = M) tCCJL Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, FS = L, FREF > 3MHz) NOTES: 1. Refer to Input Timing Requirements table for more detail. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. 4. tSK(0) is the skew between outputs when they are selected for 0tU. 5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divideby-4 mode). Test condition: nF0:1=MM is set on unused outputs. 6. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) 7. tφ is measured with REF input rise and fall times (from 0.8V to 2V) of 0.5ns. Measured from 1.5V on REF to 1.5V on FB. 8. Measured at 2V. 9. Measured at 0.8V. 10. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 6 IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE AC TEST LOADS AND WAVEFORMS V D DQ 150 Ω Output 150 Ω 20pF t O FA LL t OR IS E t PW H 2.0 V V TH = 1.5V 0.8 V t PW L LVTTL Output Waveform ≤ 1ns 3.0V 2.0V V TH = 1.5V 0.8V 0V LVTTL Input Test Waveform 7 ≤ 1ns IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE AC TIMING DIAGRAM t R PW L t R EF t RP W H RE F t (φ ) tO DC V t O DC V FB tCC JH,M ,L Q t S KE W P R t SK EW 0, 1 tS KE W P R tSK EW 0, 1 OTH ER Q t S KE W 2 t S KE W 2 INV ER TE D Q tSK EW 3, 4 tSK EW 3, 4 t SK EW 3, 4 REF D IVIDE D B Y 2 t SK EW 1, 3, 4 tSK EW 2, 4 REF D IVIDE D B Y 4 NOTES: PE: The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75Ω to VDDQ/2. tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. tSKEW0: The skew between outputs when they are selected for 0tU. tDEV: The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. tPWH is measured at 2V. tPWL is measured at 0.8V. tORISE and tOFALL are measured between 0.8V and 2V. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 8 IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX XX X Device Type Package Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 I -40°C to +85°C (Industrial) PF Thin Quad Flat Pack 5V9950 3.3V Program mable Skew PLL Clock Driver TurboClock II Jr. for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 9 for Tech Support: [email protected] (408) 654-6459