IDT IDT5992A-2JI

IDT5992A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5992A
PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK™
FEATURES:
DESCRIPTION:
• 4 pairs of programmable skew outputs
• Low skew: 200ps same pair, 250ps all outputs
• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
• Output frequency: 3.75MHz to 100MHz
• 2x, 4x, 1/2, and 1/4 outputs
• 5V with CMOS outputs
• 3 skew grades:
IDT5992A-2: tSKEW0<250ps
IDT5992A-5: tSKEW0<500ps
IDT5992A-7: tSKEW0<750ps
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 46mA IOL high drive outputs
• Low Jitter: <200ps peak-to-peak
Ω terminated lines
• Outputs drive 50Ω
• Pin-compatible with Cypress CY7B992
• Available in PLCC Package
The IDT5992A is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The IDT5992A has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals
that may be hard-wired to appropriate HIGH-MID-LOW levels.
The IDT5992A maintains Cypress CY7B992 compatibility while providing two additional features: Synchronous Output Enable (GND/sOE),
and Positive/Negative Edge Synchronization (VDDQ/PE). When the GND/
sOE pin is held low, all the outputs are synchronously enabled (CY7B992
compatibility). However, if GND/sOE is held high, all the outputs except
3Q0 and 3Q1 are synchronously disabled.
Furthermore, when the VDDQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input (CY7B992 compatibility). When VDDQ/PE is held low, all the outputs are synchronized
with the negative edge of REF.
FUNCTIONAL BLOCK DIAGRAM
G N D /sO E
1Q0
S ke w
S e le ct
1Q1
3
3
1 F 1 :0
V D D Q /P E
2Q0
S ke w
S e le ct
2Q1
3
3
REF
PLL
2 F 1 :0
FB
3
FS
3Q0
S ke w
S e le ct
3
3Q1
3
3 F 1 :0
4Q0
S ke w
S e le ct
3
4Q1
3
4 F 1 :0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AUGUST 2001
1
c
2001
Integrated Device Technology, Inc.
DSC 5391/1
IDT5992A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Symbol
2F1
TEST
ABSOLUTE MAXIMUM RATINGS(1)
GND
VDDQ
REF
FS
3F0
PIN CONFIGURATION
VI
4
3
2
1
32
31
5
29
2F0
4F0
6
28
GND/sOE
4F1
7
27
1F1
VDDQ/PE
8
26
1F0
VDDN
9
25
VDDN
4Q1
10
24
1Q0
4Q0
11
23
1Q1
GND
12
22
GND
GND
13
21
GND
19
TSTG
Unit
Supply Voltage to Ground
–0.5 to +7
V
DC Input Voltage
–0.5 to +7
V
Storage Temperature
0.8
W
–65 to +150
°C
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
20
Parameter
2Q0
18
2Q1
FB
17
VDDN
16
VDDN
15
3Q0
3Q1
14
Max
Maximum Power Dissipation (TA = 85°C)
30
3F1
Description
CIN
Description
Input Capacitance
Typ.
Max.
Unit
5
7
pF
NOTE:
1. Capacitance applies to all inputs except TEST, FS, and nF1:0.
PLCC
TOP VIEW
PIN DESCRIPTION
Pin Name
Type
Description
REF
IN
Reference Clock Input
FB
IN
Feedback Input
TEST (1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control
Summary Table) remain in effect. Set LOW for normal operation.
GND/ sOE (1)
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF[1:0] pins act as output disable
controls for individual banks when nF[1:0] = LL. Set GND/sOE LOW for normal operation.
VDDQ/PE
IN
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
nF[1:0]
IN
3-level inputs for selecting 1 of 9 skew taps or frequency functions
FS
IN
nQ[1:0]
OUT
Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.)
VDDN
PWR
Power supply for output buffers
VDDQ
PWR
Power supply for phase locked loop and other internal circuitry
GND
PWR
Ground
Four banks of two outputs with programmable skew
NOTE:
1.When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain
in effect unless nF[1:0] = LL.
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit tU which is of the
order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF1:0 control pins. In order
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF1:0 control pins.
2
IDT5992A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
EXTERNAL FEEDBACK
By providing external feedback, the IDT5992A gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FS = LOW
FS = MID
FS = HIGH
Timing Unit Calculation (tU)
1/(44 x FNOM)
1/(26 x FNOM)
1/(16 x FNOM)
VCO Frequency Range (FNOM)(1,2)
15 to 35MHz
25 to 60MHz
40 to 100MHz
±9.09ns
±9.23ns
±9.38ns
Comments
Skew Adjustment Range(3)
Max Adjustment:
ns
±49º
±83º
±135º
Phase Degrees
±14%
±23%
±37%
% of Cycle Time
Example 1, FNOM = 15MHz
tU = 1.52ns
—
—
Example 2, FNOM = 25MHz
tU = 0.91ns
tU = 1.54ns
—
Example 3, FNOM = 30MHz
tU = 0.76ns
tU = 1.28ns
—
Example 4, FNOM = 40MHz
—
tU = 0.96ns
tU = 1.56ns
Example 5, FNOM = 50MHz
—
tU = 0.77ns
tU = 1.25ns
Example 6, FNOM = 80MHz
—
—
tU = 0.78ns
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on
input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the
higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected
to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided
output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
Skew (Pair #1, #2)
Skew (Pair #3)
Skew (Pair #4)
LL(1)
–4tU
Divide by 2
Divide by 2
LM
–3tU
–6tU
–6tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
MM
Zero Skew
Zero Skew
Zero Skew
MH
1tU
2tU
2tU
HL
2tU
4tU
4tU
HM
3tU
6tU
6tU
HH
4tU
Divide by 4
Inverted(2)
NOTES:
1. LL disables outputs if TEST = MID and GND/sOE = HIGH.
2. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when VDDQ/PE = HIGH, GND/sOE disables pair #4 LOW when VDDQ/PE = LOW.
3
IDT5992A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING RANGE
Symbol
IDT5992A-5, -7
IDT5992A-2
(Industrial)
(Commercial)
Description
Min.
Max.
Min.
Max.
Unit
VDD
Power Supply Voltage
4.5
5.5
4.75
5.25
V
TA
Ambient Operating Temperature
-40
+85
0
+70
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Conditions
Min.
Max.
Unit
VDD−1.35
—
V
—
1.35
V
VDD−1
—
V
VIH
Input HIGH Voltage
Guaranteed Logic HIGH (REF, FB Inputs Only)
VIL
Input LOW Voltage
Guaranteed Logic LOW (REF, FB Inputs Only)
VIHH
Input HIGH Voltage(1)
3-Level Inputs Only
VIMM
Input MID Voltage
3-Level Inputs Only
VDD/2−0.5
VDD/2+0.5
V
VILL
Input LOW Voltage(1)
3-Level Inputs Only
—
1
V
IIN
Input Leakage Current
VIN = VDD or GND
—
±5
µA
HIGH Level
—
±200
VIN = VDD/2
MID Level
—
±50
VIN = GND
LOW Level
—
±200
VDD = Max., VIN = GND
—
±100
µA
(1)
(REF, FB Inputs Only)
VDD = Max.
VIN = VDD
I3
3-Level Input DC Current (TEST, FS, nF1:0)
IPU
Input Pull-Up Current (VDDQ/PE)
µA
IPD
Input Pull-Down Current (GND/sOE)
VDD = Max., VIN = VDD
—
±100
µA
VOH
Output HIGH Voltage
VDD = Min., IOH = −16mA
—
—
V
VDD−0.75
—
VOL
Output LOW Voltage
VDD = Min., IOL = 46mA
—
0.45
V
IOS
Output Short Circuit
VDD = Max., VO = GND
—
N/A
mA
VDD = Min., IOH = −40mA
(2)
NOTES:
1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
2. This output is not to be shorted.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
IDDQ
Quiescent Power Supply Current
Test Conditions(1)
VDD = Max., TEST = MID, REF = LOW,
Typ.(2)
Max.
Unit
10
40
mA
GND/sOE = LOW, All outputs unloaded
∆IDD
Power Supply Current per Input HIGH
VDD = Max., VIN = 3.4V
0.4
1.5
mA
IDDD
Dynamic Power Supply Current per Output
VDD = Max., CL = 0pF
100
160
µA/MHz
ITOT
Total Power Supply Current
VDD = 5V, FREF = 20MHz, CL = 240pF(1)
43
—
VDD = 5V, FREF = 33MHz, CL = 240pF(1)
63
—
240pF(1)
117
—
VDD = 5V, FREF = 66MHz, CL =
NOTE:
1. For eight outputs, each loaded with 30pF.
4
mA
IDT5992A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Description (1)
Symbol
Min.
Max.
Unit
—
10
ns/V
tR, tF
Maximum input rise and fall times, 0.8V to 2V
tPWC
Input clock pulse, HIGH or LOW
3
—
ns
DH
Input duty cycle
10
90
%
REF
Reference Clock Input
3.75
100
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT5992A-2
Symbol
Parameter
IDT5992A-5
Min.
Typ.
Max.
Min.
Typ.
IDT5992A-7
Max.
Min.
Typ.
Max.
Unit
FNOM
VCO Frequency Range
tRPWH
REF Pulse Width HIGH(1)
3
—
—
3
—
—
3
—
—
ns
tRPWL
REF Pulse Width LOW
3
—
—
3
—
—
3
—
—
ns
0.25
—
0.1
0.25
ns
tU
See PLL Programmable Skew Range and Resolution Table
(1)
Programmable Skew Time Unit
See Control Summary Table
tSKEWPR
Zero Output Matched-Pair Skew (xQ0, xQ1)(1,2,3)
tSKEW0
Zero Output Skew (All Outputs)
tSKEW1
Output Skew
(1,4,5)
—
0.05
0.2
—
0.1
—
0.1
0.25
—
0.25
0.5
—
0.3
0.75
ns
—
0.25
0.5
—
0.6
0.7
—
0.6
1
ns
—
0.5
1.2
—
0.6
1.5
—
0.5
1.5
ns
—
0.25
0.5
—
0.5
0.7
—
0.7
1.2
ns
—
0.5
0.9
—
0.6
1.7
—
1.2
1.7
ns
—
—
0.75
—
—
1.25
—
—
1.65
ns
(Rise-Rise, Fall-Fall, Same Class Outputs)(1,3)
tSKEW2
Output Skew
(Rise-Fall, Nominal-Inverted, Divided-Divided)
tSKEW3
(1,6)
Output Skew
(Rise-Rise, Fall-Fall, Different Class Outputs)(1,6)
tSKEW4
Output Skew
(Rise-Fall, Nominal-Divided, Divided-Inverted)(1,2)
tDEV
Device-to-Device Skew(1,2,7)
tPD
REF Input to FB Propagation Delay
0.25
0.5
0.7
ns
0.5
0
1.2
−0.7
−1.5
0
0
−0.5
−1.2
0
Output Duty Cycle Variation from 50%(1)
−0.25
−0.5
0
tODCV
0
1.5
ns
tPWH
Output HIGH Time Deviation from 50%
—
—
3
—
—
4
—
—
5.5
ns
tPWL
Output LOW Time Deviation from 50%(1,11)
—
—
3
—
—
4
—
—
5.5
ns
tORISE
Output Rise Time
0.5
2
2.5
0.5
2
3.5
0.5
3
5
ns
tOFALL
Output Fall Time
0.5
2
2.5
0.5
2
3.5
0.5
3
5
ns
tLOCK
PLL Lock Time(8)
—
—
0.5
—
—
0.5
—
—
0.5
ms
RMS
—
—
25
—
—
25
—
—
25
ps
Peak-to-Peak
—
—
200
—
—
200
—
—
200
tJR
(1,9)
(1,10)
(1)
(1)
Cycle-to-Cycle Output Jitter(1)
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSKEW0 is the skew between outputs when they are selected for 0tU.
5. For IDT5992A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.45ns Max.
6. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divideby-4 mode).
7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDD ambient temperature, air flow, etc.)
8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
9. tPD is measured with REF input rise and fall times (from 0.2VDD to 0.8VDD ) of 1.5ns.
10. Measured at 0.8VDD.
11. Measured at 0.2VDD.
5
IDT5992A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TEST LOADS AND WAVEFORMS
V DD
100 Ω
Output
100 Ω
CL
C L = 50pF (C L = 30pF for -2 and -5 devices)
Test Load
tO FALL
t ORISE
0.8V DD
t PW H
t PWL
0.2V DD
CMOS Output Waveform
≤ 1.5ns
V DD
80%
Vth = 0.5V DD
20%
0V
CMOS Input Test Waveform
6
≤ 1.5ns
IDT5992A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TIMING DIAGRAM
t R PW L
t R EF
t RPW H
REF
t PD
t O DC V
t O DC V
FB
t JR
Q
t SKEW PR
t SKEW 0, 1
t SKEW PR
t SKEW 0, 1
OTH ER Q
t SKEW 2
t SKEW 2
INVER TED Q
t SKEW 3, 4
t SKEW 3, 4
t SKEW 3, 4
REF D IVIDED BY 2
t SKEW 1, 3, 4
t SKEW 2, 4
REF D IVIDED BY 4
NOTES:
V DDQ/PE: The AC Timing Diagram applies to VDDQ/PE=VDD. For VDDQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the
negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 50pF (30pF for
-2 and -5) and terminated with 50Ω to VDD/2.
tSKEWPR:
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSKEW0:
The skew between outputs when they are selected for 0tU.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.)
tODCV:
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tPWH is measured at 0.8VDD.
tPWL is measured at 0.2VDD.
tORISE and tOFALL are measured between 0.2VDD and 0.8VDD.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
7
IDT5992A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device Type
XX
Package
X
Process
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
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I
Commercial (0°C to +70°C)
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Rectangular Plastic Leaded Chip Carrier
5992A-2
5992A-5
5992A-7
Programmable Skew PLL Clock Driver TurboClock
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
8
for Tech Support:
[email protected]
(408) 654-6459