PM8355 QuadPHY-II™ 4-Channel 2.125, 2.5, and 3.125 Gbit/s Transceiver with Half-rate Support FEATURES GENERAL • 10Gbit/s, bi-directional, XAUI to XGMII link compatible with IEEE 802.3ae. • Four independent 2.125, 2.5 and 3.125 Gbit/s SERDES for Fibre Channel, Infiniband, 10 GE line cards and high-speed backplane applications. • Half/Full rate mode selectable per channel. • Integrated serializer/ deserializer, clock synthesis, clock recovery and 8B/10B encode/decode logic. • Low-power operation 1.5 W typical @ 3.125Gbit/s. AM :09 :15 TEST FEATURES 02 12 • Extensive control of loopback, BIST, and operating modes via 802.3 compliant MDC/MDIO serial interface. • On-chip packet generator/checkerprovides at-speed diagnostics. • Built-in error counters per channel. • Support for IEEE 1149.1 JTAG testing on all pins. 20 The QuadPHY-II™ is a physical layer transceiver ideal for systems requiring high-speed point-to-point communication links. It is applicable for PMAPMD connections in 10 GE, Infiniband 1 or 4 x 2.5 Gbit/s links, 1 and 2 Gbit/s Fibre Channel, as well as high speed serial backplanes for high capacity systems. • Trunking feature de-skews and aligns all four channels to form a single 10 Gbit/s logical link. tem be • Redundant high-speed serial I/O channels for convenient switching to redundant fabric. • High-speed outputs with optional preemphasis to drive longer backplanes. • High-speed I/O with on-chip termination resistors to directly drive dual-terminated 50 Ohm lines. • High-speed inputs have programmable receive equalization to eliminate the effects of Inter Symbol Interference (ISI). r, SERIAL I/O GENERAL DESCRIPTION PHYSICAL ep PARALLEL I/O ,2 0S • 10-bit Dual Data Rate (DDR) parallel interface. • Selectable source simultaneous or source synchronous transmit and receive parallel interfaces. • Convenient output clock for user friendly ASIC timing. • Interoperates with SSTL2 and 1.8 V LVCMOS standard. • 1.8V, 0.18 µ standard CMOS technology with 2.5 V tolerant I/O. • 289-ball CABGA (19 mm x 19 mm package). io nF rid ay APPLICATIONS ett TRUNKING &TIMING High speed serial backplanes 10 GE links Fibre Channel transceivers Infiniband transceivers XAUI retimers Intra-system interconnect uo fo liv • Integrated Receive FIFO synchronizes incoming data to local clock domain. • • • • • • BLOCK DIAGRAM inv ef PM8355 - QuadPHY-II yV Primary Channel TDOXPA/ TDOXNA 2 Serializer db XAUI Transmit TXDA [9:0] 8B/10B Encoder FIFO & /A/ Insert Adaptive Sampler de loa Serial Loopback RXDA [9:0] Clock Recovery DeSerializer & Byte Align 10B/8B Decoder 9 or 10 XGMII Parallel Output RXCLKA 2 Channel A Channel B Channel C Channel D RESET, MDIO/MDC Mode Strapping Pins JTAG Interface, BIST pins Clock Synthesis PLL_LOCK Common Control Logic PMC-2000791 (P6) FIFO & Trunking Logic REFCLK Do 2 RDIYPA/ RDIYNA Parallel Loopback SYSCLK wn RDIXPA/ Primary Channel RDIXNA Secondary Channel XGMII Parallel Input TXCLK Secondary Channel TDOYPA/ 2 TDOYNA XAUI Receive 9 or 10 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE © Copyright PMC-Sierra, Inc. 2002 PM8355 QuadPHY-II™ 4-Channel 2.125, 2.5, and 3.125 Gbit/s Transceiver with Half-rate Support EXAMPLE ARCHITECTURE The 10GE line cards use the QuadPHYII as a PHY supporting XAUI on the line side and mating to a 10GE MAC using XGMII. AM :09 The figure below shows a multi-service switching platform using QuadPHY-II devices for backplane interconnect and client signal physical interfaces. The other applications shown are a XAUI retimer and an XGMII extender where the MAC and Optics module separated by longer distance. 12 02 As a serial backplane transceiver, the redundant high-speed links simplify the interface to a working and protect fabric. :15 Infiniband and Fibre Channel line cards applications are also shown. The halfrate mode of the QuadPHY-II enables 1 and 2 Gbit/s support using the same device. 1Gig Fibre Channel Link Switch Fabric Module 1G Fibre Channel Card io ett liv fo uo ef inv yV db de ep 0S ,2 ay QuadPHY-II 10 GE LAN XENPAK or XPAK XAUI 4x2.5 Gig Fibre Infiniband Line Card QuadPHY-II To order documentation, send email to: [email protected] or contact the head office, Attn: Document Coordinator XAUI QuadPHY-II ASIC or FPGA XENPAK or XPAK XAUI Retimer QuadPHY-II loa MAC Infiniband ASIC Upper Layer Functions MAC XGMII Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 10 GE 4x3.125 WDM XAUI EXTENDER QuadPHY-II wn Upper Layer Functions XGMII QuadPHY-II Do Custom ASIC Redundant Switch Fabric Device QuadPHY-II • • • XENPAK or XPAK XAUI XGMII 10 Gigabit Ethernet LAN Line Card QuadPHY-II GMII/TBI MAC XGMII QuadPHY-II Upper Layer Functions nxGE MACs • • • QuadPHY-II Gigabit Ethernet Quad/ Octal PHYs QuadPHY-II Optical Xceivers Upper Layer Functions QuadPHY-II Gigabit Ethernet Card Custom ASIC WDM 10 Gigabit Ethernet LAN Line Card QuadPHY-II TBI QuadPHY-II QuadPHY-II ASIC / FPGA FiberChannel MAC + Upper Layer Functions Gigabit Ethernet • • • QuadPHY-II 2 Gig Fibre Channel Link QuadPHY-II Optical Tranceiver nF 1G / 2G Fibre Channel Card rid Switch Fabric Device QuadPHY-II TBI 2 Gig Fibre Channel Link • • • QuadPHY II 1Gig Fibre Channel Link FiberChannel MAC + Upper Layer Functions QuadPHY-II Quad/ Octal PHYs QuadPHY-II ASIC / FPGA Optical Tranceiver 10 GE 10Gig Serial LAN Serial 10 Gigabit Ethernet LAN Line Card QuadPHY-II • • • tem be r, 20 APPLICATION EXAMPLE - MULTI-SERVICE SWITCHING PLATFORM All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: [email protected] XENPAK or XPAK 4 x 2.5Gig PMC-2000791 (P6) © Copyright PMC-Sierra, Inc. 2002. All rights reserved. OctalPHY, QuadPHY, and S/UNI are registered trademarks of PMC-Sierra Inc. SPECTRA, CHESS and QuadPHY-II are trademarks of PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE